CN112736198B - Resistive random access memory and preparation method thereof - Google Patents
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Abstract
A resistance random access memory and its preparation method, said method includes depositing the first dielectric layer and flattening on the surface of first metal layer of CMOS back-end of the line; preparing and flattening a lower electrode of the resistance change memory unit in the first dielectric layer; sequentially depositing an oxide resistance change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode, preparing an upper electrode by patterning the upper electrode layer and preparing an oxide resistance change pattern by patterning the oxide resistance change layer, wherein the projection pattern of the upper electrode is overlapped with the projection pattern of the lower electrode only in partial areas, and the upper surface of the oxide resistance change pattern is overlapped with the lower surface of the upper electrode; depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process; and preparing a contact hole of the CMOS back-end process and a second metal layer in the second dielectric layer to lead out an upper electrode of the resistance change memory unit, wherein a lower electrode of the resistance change memory unit is led out through the first metal layer. Therefore, the invention limits the formation area of the oxygen vacancy conductive channel in the resistance change layer so as to improve the uniformity of the device.
Description
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a resistive random access memory and a preparation method thereof.
Background
The resistive random access memory (Resistive Random Access Memory, RRAM) is a novel nonvolatile memory, which has advantages of high speed, low power consumption, nonvolatile property, high integration, compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, and the like, and has become one of research hotspots in the field of novel memories in recent years, and even commercial products have appeared.
Resistive memory cells, which are the core of resistive memory technology and are based on transition metal oxides, have been widely studied for their high compatibility with mainstream CMOS processes, and generally adopt a structure similar to a parallel plate capacitor, i.e. a sandwich structure comprising an upper Electrode (Top Electrode), a resistive Layer (Switch Layer) and a lower Electrode (Bottom Electrode), wherein the upper and lower electrodes are conductive metals and the resistive Layer is generally a non-stoichiometric transition metal oxide.
In terms of process implementation, the sandwich structure can be directly embedded into the back-end structure of the mainstream CMOS process, i.e., the RRAM structure is directly inserted between two layers of metal on the basis of not changing the standard CMOS back-end process parameters, thereby achieving complete compatibility with the standard CMOS logic process (as shown in fig. 1). The upper electrode, the lower electrode and the transition metal oxide of the resistive element are usually metal materials and oxide materials compatible with the CMOS back-end process.
The resistance change mechanism of the resistance change device based on the transition metal oxide is as follows:
referring to fig. 1, fig. 1 is a schematic diagram of a prior art resistive memory cell fully compatible with standard CMOS logic processes. As shown, the left is Logic device (Logic) and the right is the cross-sectional structure of a resistive random access memory cell (RRAM). The conductive filament channel based on oxygen vacancies (shown by two S-shaped lines in the oxide resistive layer) is formed by inducing an external electric field in the oxide resistive layer, and the connection and disconnection of the conductive filament channel are further controlled by different operation voltages of the upper electrode and the lower electrode, so that a stable high-low resistance state is formed. It can be seen that, because the overlapping area of the upper and lower electrodes is too large (almost equal from the figure), the oxygen vacancy conduction channel formed in the oxide resistive layer is generally very uncontrollable, which further results in that the electrical characteristics of the resistive memory cell are also very discrete, which severely restricts the industrial application of the resistive memory.
Therefore, how to improve the uniformity of the resistive switching device, especially to realize the controllable formation of the oxygen vacancy conductive channel in terms of device structure and process manufacturing, has become an important exploration direction in the industry for improving the characteristics of the RRAM device, and is one of key technologies for pushing the RRAM technology to realize the industrialized application.
Disclosure of Invention
Aiming at the defect of the capability of the prior art, the invention provides a resistive random access memory compatible with a CMOS (complementary metal oxide semiconductor) process, a preparation method thereof and an upper electrode structure and a lower electrode structure with adjustable overlapped area size prepared based on a standard CMOS process, thereby limiting the formation area of an oxygen vacancy conductive channel in a resistive random access layer and realizing the remarkable improvement of the unit consistency of the resistive random access device.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a preparation method of a resistive random access memory comprises the steps of at least one resistive random access memory unit; the method comprises the following steps:
step S1: depositing a first dielectric layer on the surface of a first metal layer of the CMOS back-end process and flattening the first dielectric layer;
step S2: preparing a lower electrode of a resistance change memory unit in the first dielectric layer and flattening the lower electrode;
step S3: sequentially depositing an oxide resistance change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode;
step S4: patterning an upper electrode of the upper electrode layer for preparing a resistive random access memory unit and patterning the oxide resistive random access layer for preparing an oxide resistive random access pattern, wherein the projection pattern of the upper electrode and the projection pattern of the lower electrode are overlapped only in partial areas, and the number of the overlapped areas is the same as that of the resistive random access memory unit; the upper surface of the oxide resistance change pattern is overlapped with the lower surface of the upper electrode;
step S5: depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process;
step S6: and preparing a contact hole of the CMOS back-end process and a second metal layer in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
Further, the step S2 includes:
s21: defining a lower electrode pattern of the resistance change memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer through a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed.
Further, in step S3, an oxide resistive layer and an upper electrode layer are sequentially deposited on the surfaces of the first dielectric layer and the lower electrode, and a physical vapor deposition process is adopted to implement the method.
Further, the lower surface size of the upper electrode is the same as the upper surface size of the oxide resistance change pattern; the size of the partial overlapping area in the step S4 is smaller than the size of the lower surface of the oxide resistance change pattern and is larger than or equal to zero; wherein the partial overlap region is zero when one side edge of the lower electrode coincides with the opposite side edge of the upper electrode.
Further, the step S5 specifically includes:
step S51: depositing a barrier layer on the upper surface and the side surface of the upper electrode, the side surface of the oxide resistance change pattern, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
Further, the blocking layer material is the same as the first dielectric layer material.
Further, the dielectric constant of the first dielectric layer is higher than the dielectric constant of the second dielectric layer.
Further, the thickness of the first dielectric layer is much smaller than the thickness of the second dielectric layer.
Further, the lower electrode material of the resistive random access memory cell comprises Ta, ti, cu, W, taN or TiN.
Further, the upper electrode material includes Ta, ti, taN or TiN, and the oxide resistive layer material includes TaOx, hfOx, or TiOx.
A resistive random access memory, the resistive random access memory comprising at least one resistive random access memory cell; the resistive random access memory cell is characterized by comprising:
a first dielectric layer and a lower electrode prepared on the first dielectric layer;
an oxide resistive pattern and an upper electrode sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; the projection patterns of the upper electrode and the projection patterns of the lower electrode are overlapped only in partial areas, and the number of the overlapped areas is the same as that of the resistive random access memory units.
Further, the resistive random access memory further includes:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
the second dielectric layer, the contact hole of the CMOS back-end process prepared on the second dielectric layer and the second metal layer are used for leading out the upper electrode;
wherein two adjacent resistive memory cells share one lower electrode or one upper electrode.
According to the technical scheme, the resistive random access memory and the preparation method thereof provided by the invention are used for preparing the partially overlapped 'upper electrode/resistive random access layer-lower electrode' structure based on the standard CMOS back-end process, and the size of the overlapped area of the upper electrode and the lower electrode is adjusted by designing the partially overlapped upper electrode layout and the lower electrode layout, so that the effective device size of the resistive random access memory unit is effectively controlled, the effective regulation and control of the formation area of the oxygen vacancy conductive channel in the resistive random access layer is realized, the discreteness of the resistive random access device unit can be obviously improved, and the consistency of the device characteristics can be improved.
In addition, the preparation method provided by the invention is completely based on the standard CMOS back-end process, the process integration mode of the resistive random access memory unit is completely compatible with the standard logic process, and the materials of the upper electrode and the lower electrode of the resistive random access memory unit and the resistive random access layer are also completely made of materials commonly used or compatible with the CMOS back-end process, so that the preparation method is very suitable for the mass production and the manufacture of future resistive random access memory chips, and has very wide application prospect.
Drawings
FIG. 1 is a schematic cross-sectional view of a resistive random access memory cell implemented based on conventional technology
FIG. 2 is a process flow diagram of a method for manufacturing a resistive random access memory according to an embodiment of the invention
Fig. 3 to 9 are schematic cross-sectional views corresponding to a method for manufacturing a resistive random access memory according to an embodiment of the invention
Detailed Description
The following describes embodiments of the present invention in further detail with reference to fig. 2-9.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view of a resistive random access memory product formed by the method for manufacturing a resistive random access memory according to the present invention. As shown, the resistive random access memory includes at least one resistive random access memory cell; the resistive random access memory cell includes:
a first dielectric layer and a lower electrode prepared on the first dielectric layer;
an oxide resistive layer and an upper electrode sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; wherein, the projection pattern of the upper electrode and the projection pattern of the lower electrode are overlapped only in partial areas, and the number of the overlapped areas is the same as that of the resistive random access memory units;
wherein the upper surface of the oxide resistance change pattern coincides with the lower surface of the upper electrode.
And, the resistance random access memory, it still includes:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
the second dielectric layer, the contact hole of the CMOS back-end process prepared on the second dielectric layer and the second metal layer are used for leading out the upper electrode;
wherein two adjacent resistive memory cells share one lower electrode or one upper electrode.
The invention also adopts a structure similar to a parallel plate capacitor, namely a sandwich structure comprising an upper Electrode (Top Electrode), a resistive Layer (Switch Layer) and a lower Electrode (Bottom Electrode), wherein the upper Electrode and the lower Electrode are conductive metals, and the resistive Layer is usually transition metal oxide with non-stoichiometric ratio.
In terms of process implementation, the sandwich structure can be directly embedded into a back-end structure of a mainstream CMOS process, namely, the RRAM structure is directly inserted between two layers of metals on the basis of not changing the parameters of the standard CMOS back-end process, so that the complete compatibility with the standard CMOS logic process is ensured, wherein the upper electrode, the lower electrode and the transition metal oxide of the resistance change unit are usually made of metal materials and oxide materials compatible with the CMOS back-end process.
Unlike the prior art, the technical scheme of the invention realizes the controllable formation of the oxygen vacancy conductive channel in terms of device structure and process manufacturing, and becomes an important exploration direction for improving the consistency of the resistive random access device. Specifically, a partially overlapped 'upper electrode/resistance change layer-lower electrode' structure is prepared based on a standard CMOS back-end process, the size of an upper electrode overlapping region and a lower electrode overlapping region is adjusted by designing the partially overlapped upper electrode layout and the partially overlapped lower electrode layout, and the effective device size of a resistance change memory unit is effectively controlled, so that the effective regulation and control of an oxygen vacancy conductive channel forming region in the resistance change layer is realized, the discreteness of the resistance change device unit can be obviously improved, and the consistency of device characteristics is improved.
It is apparent to those skilled in the art that the resistive random access memory may include at least one resistive random access memory cell due to the advantage of the semiconductor integrated process, and in the embodiment of the present invention, the resistive random access memory is described by taking an example that the resistive random access memory includes two resistive random access memory cells.
Referring to fig. 2, fig. 2 is a process flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the invention, and as shown in fig. 2, the method may include the following steps:
step S1: and depositing a first dielectric layer on the surface of the first metal layer of the CMOS back-end process and flattening.
Specifically, referring to fig. 3, a first dielectric layer is deposited on a surface of a first metal layer of a CMOS back-end process, and planarized by a CMP process, where the first metal layer is any one of interconnect metal layers, typically copper metal layers, in a standard CMOS back-end process, and the first dielectric layer is a barrier layer with a relatively high dielectric constant, typically a silicon carbide nitride (SiCN) material.
Step S2: and preparing a lower electrode of the resistance change memory unit in the first dielectric layer and flattening. Specifically, step S2 may include the steps of:
s21: defining a lower electrode pattern of the resistance change memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer through a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed, thereby completing the preparation of the lower electrode of the resistive random access memory unit in the first dielectric layer.
Referring to fig. 4, a specific process of preparing a bottom electrode of a resistive random access memory cell and performing planarization in a first dielectric layer is as follows: defining a lower electrode pattern of a resistance change memory unit in the first dielectric layer through photoetching and etching processes, depositing a lower electrode metal layer through a PVD process, and flattening through a CMP process, wherein the lower electrode material can be a common conductive material of CMOS back-end processes such as Ta, ti, cu, W, taN, tiN.
Step S3: sequentially depositing an oxide resistance change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode; preferably, in step S3, the oxide resistive layer and the upper electrode layer are sequentially deposited on the surfaces of the first dielectric layer and the lower electrode by using a physical vapor deposition process.
As shown in FIG. 5, the deposition process can be a PVD process commonly used in the CMOS back-end process, the oxide resistive layer material can be a dielectric material compatible with the CMOS back-end process such as TaOx, hfOx, tiOx, and the upper electrode material can be a conductive material commonly used in the CMOS back-end process such as Ta, ti, taN, tiN.
Step S4: patterning an upper electrode of the upper electrode layer for preparing a resistive random access memory unit and patterning the oxide resistive random access layer for preparing an oxide resistive random access pattern, wherein the projection pattern of the upper electrode and the projection pattern of the lower electrode are overlapped only in partial areas, and the number of the overlapped areas is the same as that of the resistive random access memory unit; the upper surface of the oxide resistance change pattern is overlapped with the lower surface of the upper electrode. Preferably, the dimension of the lower surface of the upper electrode is the same as the dimension of the upper surface of the oxide resistance change pattern.
In an embodiment of the present invention, the size of the partially overlapped region in the step S4 is smaller than the size of the lower surface of the oxide resistance change pattern, and is greater than or equal to zero; wherein the partial overlap region is zero when one side edge of the lower electrode coincides with the opposite side edge of the upper electrode.
Referring to fig. 6, a photolithography and etching process is used to prepare an upper electrode and an oxide resistive pattern with an adjustable size of an overlapping region with the lower electrode, where x is the size of the overlapping region of the upper electrode and the lower electrode, and the structure can be adjusted by designing partially overlapping upper and lower electrode layouts. If the dimension x of the partially overlapped region is at least zero, then one side edge of the lower electrode coincides with the opposite side edge of the upper electrode, for example, the right side edge of the lower electrode coincides with the left side edge of the upper electrode, and thus the fabrication of the resistive memory cell structure is completed.
Then, the interconnection leading-out of the upper electrode and the lower electrode of the resistive random access memory unit is needed, namely, step S5 is executed: and depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process.
Specifically, the step S5 specifically includes:
step S51: depositing barrier layers on the upper surface and the side surface of the upper electrode, the oxide resistance side surface, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
That is, the fabricated resistive random access memory cell structure needs to be protected and isolated, as shown in fig. 7, i.e., a barrier layer is deposited on the surface and the side surface of the upper electrode, the surface of the lower electrode and the surface of the first dielectric layer, where the barrier layer is made of the same material as the first dielectric layer, typically a silicon carbide nitride (SiCN) material with a higher dielectric constant, in order to ensure that the subsequent contact hole etching process is fully compatible with the standard logic process. The thickness of the first dielectric layer is smaller than that of the second dielectric layer.
Referring to fig. 8, a second dielectric layer of the CMOS back-end process is prepared and planarized, where the second dielectric layer of the CMOS back-end process is deposited and then planarized by a CMP process. Preferably, the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer; for example, the second dielectric layer is a low-k dielectric layer, typically SiCOH material, and the thickness of the second dielectric layer is typically much greater than the thickness of the first dielectric layer.
Step S6: and preparing a contact hole of the CMOS back-end process and a second metal layer in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
Specifically, as shown in fig. 9, a contact hole and a second metal layer of a CMOS back-end process are prepared, so as to realize interconnection extraction of upper and lower electrodes of a resistive random access memory cell. For example, the standard logic device region and the resistive memory cell region can be simultaneously led out by adopting a standard copper damascene process, and preferably, the etching process parameters of the contact holes can be required to be properly optimized to ensure that the etching of the contact holes of the resistive memory cell and the etching of the contact holes of the standard logic process can be simultaneously completed, thereby finally realizing the process preparation of the resistive memory cell.
In summary, as can be seen from the schematic cross-sectional view of the finally prepared resistive random access memory cell, the effective device size of the resistive random access memory cell is the size of the overlapping region of the upper electrode and the lower electrode (as shown by x in fig. 9), and the size can be adjusted by designing the non-overlapping upper electrode layout and the non-overlapping lower electrode layout, so that the formation region of the oxygen vacancy conductive channel in the resistive random access layer is greatly limited, and the purposes of improving the discreteness of the resistive random access memory cell and improving the uniformity of the device are achieved.
Meanwhile, as can be seen from the whole preparation flow of the resistive random access memory unit, the preparation method provided by the invention is completely based on the standard CMOS back-end process, the process integration mode of the resistive random access memory unit is completely compatible with the standard logic process, and the materials of the upper electrode and the lower electrode of the resistive random access memory unit and the resistive random access layer are also completely made of materials commonly used or compatible with the CMOS back-end process, so that the preparation method is very suitable for mass production and manufacture of future resistive random access memory chips, and has very wide application prospect.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.
Claims (10)
1. A method for manufacturing a resistive random access memory, the resistive random access memory comprising at least one resistive random access memory cell, the method comprising the steps of:
step S1: depositing a first dielectric layer on the surface of a first metal layer of the CMOS back-end process and flattening the first dielectric layer;
step S2: preparing a lower electrode of a resistance change memory unit in the first dielectric layer and flattening the lower electrode;
step S3: sequentially depositing an oxide resistance change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode;
step S4: patterning an upper electrode of the upper electrode layer for preparing a resistive random access memory unit and patterning the oxide resistive random access memory layer for preparing oxide resistive random access patterns, wherein the projection patterns of the upper electrode are adjacent to the projection patterns of the lower electrode, the edge projection patterns of the upper electrode and the edge projection patterns of the upper surface of the lower electrode are overlapped only in partial areas, and the number of the overlapped areas is the same as that of the resistive random access memory unit; the upper surface of the oxide resistance change pattern is overlapped with the lower surface of the upper electrode;
step S5: depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process;
step S6: and preparing a contact hole of the CMOS back-end process and a second metal layer in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
2. The method for manufacturing a resistive random access memory according to claim 1, wherein the step S2 comprises:
s21: defining a lower electrode pattern of the resistance change memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer through a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed.
3. The method for manufacturing a resistive random access memory according to claim 1, wherein in step S3, the oxide resistive random access layer and the upper electrode layer are sequentially deposited on the surfaces of the first dielectric layer and the lower electrode, and are realized by a physical vapor deposition process.
4. The method of manufacturing a resistive random access memory according to claim 1, wherein the dimension of the lower surface of the upper electrode is the same as the dimension of the upper surface of the oxide resistive pattern; the size of the part of the overlapped area in the step S4 is smaller than the size of the lower surface of the oxide resistance change pattern and is larger than or equal to zero; wherein, the case that part of the overlapping area is zero is the case that one side edge of the lower electrode coincides with the opposite side edge of the upper electrode.
5. The method for manufacturing a resistive random access memory according to claim 1, wherein the step S5 specifically comprises:
step S51: depositing a barrier layer on the upper surface and the side surface of the upper electrode, the side surface of the oxide resistance change pattern, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
6. The method of claim 5, wherein the barrier layer material is the same as the first dielectric layer material.
7. The method of claim 1, wherein the first dielectric layer has a higher dielectric constant than the second dielectric layer, and wherein the first dielectric layer has a thickness less than the second dielectric layer.
8. The method for manufacturing a resistive random access memory according to claim 1, wherein the lower electrode material of the resistive random access memory cell comprises Ta, ti, cu, W, taN or TiN; the upper electrode material includes Ta, ti, taN or TiN, and the oxide resistive layer material includes TaOx, hfOx, or TiOx.
9. A resistive random access memory comprising at least one resistive random access memory cell, the resistive random access memory cell comprising:
a first dielectric layer and a lower electrode prepared on the first dielectric layer;
an oxide resistive pattern and an upper electrode sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; the projection patterns of the upper electrode are adjacent to the projection patterns of the lower electrode, the edge projection patterns of the upper electrode are identical to the edge projection patterns of the upper surface of the lower electrode, and the number of the overlapped areas is identical to the number of the resistance change memory units;
wherein the upper surface of the oxide resistance change pattern coincides with the lower surface of the upper electrode.
10. The resistive random access memory of claim 9, further comprising:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
the second dielectric layer, the contact hole of the CMOS back-end process prepared on the second dielectric layer and the second metal layer are used for leading out the upper electrode;
wherein two adjacent resistive memory cells share one lower electrode or one upper electrode.
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