CN112736198A - Resistive random access memory and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 97
- 230000008569 process Effects 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 230000008859 change Effects 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 229910004166 TaN Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 6
- 238000007517 polishing process Methods 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 5
- 230000015654 memory Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910003070 TaOx Inorganic materials 0.000 claims description 3
- 229910003087 TiOx Inorganic materials 0.000 claims description 3
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 abstract description 9
- 239000001301 oxygen Substances 0.000 abstract description 9
- 238000000059 patterning Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 5
- 229910000314 transition metal oxide Inorganic materials 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- -1 HfOx Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000013065 commercial product Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
A resistive random access memory and a preparation method thereof are provided, the method comprises the steps of depositing a first dielectric layer on the surface of a first metal layer of a CMOS back-end process and flattening the first dielectric layer; preparing a lower electrode of the resistive random access memory unit in the first dielectric layer and flattening; depositing an oxide resistance change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode in sequence, preparing an upper electrode by patterning the upper electrode layer and preparing an oxide resistance change pattern by patterning the oxide resistance change layer, wherein the projection pattern of the upper electrode is only partially overlapped with the projection pattern of the lower electrode, and the upper surface of the oxide resistance change pattern is overlapped with the lower surface of the upper electrode; depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process; and preparing a contact hole and a second metal layer of the CMOS back-end process in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer. Therefore, the invention limits the forming area of the oxygen vacancy conduction channel in the resistance change layer so as to promote the consistency of the device.
Description
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a resistive random access memory and a preparation method thereof.
Background
Resistive Random Access Memory (RRAM) is a novel nonvolatile Memory, which has the advantages of high speed, low power consumption, non-volatility, high integration, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) processes, and the like, and has become one of the research hotspots in the field of novel memories in recent years, and even has appeared as a commercial product.
The resistive random access memory unit is the core of the resistive random access memory technology, and is widely researched due to high compatibility with the mainstream CMOS process, and generally adopts a structure similar to a parallel plate capacitor, namely, a sandwich structure including an upper Electrode (Top Electrode), a resistive Layer (Switch Layer) and a lower Electrode (Bottom Electrode), wherein the upper Electrode and the lower Electrode are conductive metals, and the resistive Layer is generally a non-stoichiometric transition metal oxide.
In terms of process implementation, the sandwich structure can be usually directly embedded into a back-end structure of a mainstream CMOS process, that is, on the basis of not changing the parameters of the back-end process of the standard CMOS, the RRAM structure is directly inserted between two layers of metal, so as to achieve complete compatibility with the standard CMOS logic process (as shown in fig. 1). The upper and lower electrodes of the resistive unit and the transition metal oxide are usually made of metal materials and oxide materials compatible with the CMOS back-end process.
The resistance change mechanism of the resistance change device based on the transition metal oxide is as follows:
referring to fig. 1, fig. 1 is a schematic diagram illustrating a resistive random access memory cell fully compatible with a standard CMOS logic process in the prior art. As shown, the left side is a Logic device (Logic), and the right side is a cross-sectional structure of a resistive random access memory cell (RRAM). An oxygen vacancy-based conductive filament channel (represented by two S-shaped lines in the oxide resistive layer) is induced and formed in the oxide resistive layer by an external electric field, and the connection and disconnection of the conductive filament channel are further controlled by different operating voltages of the upper electrode and the lower electrode, so that a stable high-low resistance state is formed. It can be seen that, since the overlapping regions of the upper and lower electrodes are too large (almost equal as seen in the figure), the oxygen vacancy conduction channel formed in the oxide resistive layer generally has great uncontrollable property, which further causes great dispersion of the electrical characteristics of the resistive random access memory cell, and this phenomenon seriously restricts the industrial application of the resistive random access memory.
Therefore, how to improve the uniformity of the resistive random access device, especially how to realize the controllable formation of the oxygen vacancy conduction channel from the aspects of device structure and process manufacturing, has become an important exploration direction for improving the characteristics of the RRAM device in the industry, and is also one of the key technologies for promoting the RRAM technology to realize the industrial application and urgent need to break through.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a resistive random access memory compatible with a CMOS (complementary metal oxide semiconductor) process and a preparation method thereof, and an upper electrode structure and a lower electrode structure with adjustable sizes of overlapping regions are prepared based on the standard CMOS process, so that the forming region of an oxygen vacancy conductive channel in a resistive layer is limited, and the unit consistency of a resistive random access device is remarkably improved.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a preparation method of a resistive random access memory comprises at least one resistive random access memory unit; which comprises the following steps:
step S1: depositing a first dielectric layer on the surface of a first metal layer of the CMOS back-end process and flattening;
step S2: preparing a lower electrode of the resistive random access memory unit in the first dielectric layer and flattening;
step S3: sequentially depositing an oxide resistance-change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode;
step S4: imaging the upper electrode layer to prepare an upper electrode of a resistive random access memory unit and imaging the oxide resistive random access layer to prepare an oxide resistive random access graph, wherein only partial areas of the projection graph of the upper electrode and the projection graph of the lower electrode are overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units; the upper surface of the oxide resistance change pattern is superposed with the lower surface of the upper electrode;
step S5: depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process;
step S6: and preparing a contact hole and a second metal layer of a CMOS back-end process in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
Further, the step S2 includes:
s21: defining a lower electrode pattern of the resistive random access memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer by a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed.
Further, the step S3 of sequentially depositing the oxide resistance change layer and the upper electrode layer on the surfaces of the first dielectric layer and the lower electrode is implemented by using a physical vapor deposition process.
Further, the size of the lower surface of the upper electrode is the same as the size of the upper surface of the oxide resistive switching pattern; the size of the partial overlapping area in the step S4 is smaller than the size of the lower surface of the oxide resistance change pattern and is greater than or equal to zero; wherein the case where the partial overlap region is zero is a case where one side edge of the lower electrode coincides with an opposite side edge of the upper electrode.
Further, the step S5 specifically includes:
step S51: depositing barrier layers on the upper surface and the side surface of the upper electrode, the side surface of the oxide resistance change pattern, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
Further, the material of the barrier layer is the same as that of the first dielectric layer.
Further, the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer.
Further, the thickness of the first dielectric layer is far smaller than that of the second dielectric layer.
Further, the lower electrode material of the resistive random access memory unit comprises Ta, Ti, Cu, W, TaN or TiN.
Further, the upper electrode material includes Ta, Ti, TaN, or TiN, and the oxide resistance change layer material includes TaOx, HfOx, or TiOx.
A resistive random access memory comprises at least one resistive random access memory unit; characterized in that the resistive random access memory unit comprises:
the device comprises a first dielectric layer and a lower electrode prepared on the first dielectric layer;
the oxide resistance change pattern and the upper electrode are sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; the projected pattern of the upper electrode and the projected pattern of the lower electrode are only partially overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units.
Further, the resistive random access memory further includes:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
a second dielectric layer, and a contact hole and a second metal layer of a CMOS back-end process prepared on the second dielectric layer to lead out the upper electrode;
and two adjacent resistive random access memory units share one lower electrode or one upper electrode.
According to the technical scheme, the resistive random access memory and the preparation method thereof provided by the invention have the advantages that the partially overlapped upper electrode/resistive layer-lower electrode structure is prepared based on the standard CMOS back-end process, the size of the overlapped area of the upper electrode and the lower electrode is adjusted by designing the partially overlapped upper electrode layout, and the effective device size of the resistive random access memory unit is effectively controlled, so that the effective regulation and control of the oxygen vacancy conductive channel forming area in the resistive layer are realized, the discreteness of the resistive random access device unit can be obviously improved, and the consistency of the device characteristics can be improved.
In addition, the preparation method provided by the invention is completely based on a standard CMOS back-end process, the process integration mode of the resistive random access memory unit is completely compatible with a standard logic process, and the materials of the upper electrode, the lower electrode and the resistive layer of the resistive random access memory unit are also completely made of materials which are commonly used in the CMOS back-end process or are compatible with the process, so that the method is very suitable for mass production of future resistive random access memory chips and has a very wide application prospect.
Drawings
FIG. 1 is a schematic cross-sectional view of a resistive random access memory cell implemented based on a conventional technical scheme
Fig. 2 is a process flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention
Fig. 3 to 9 are schematic cross-sectional views corresponding to the manufacturing method of the resistive random access memory provided in the embodiment of the present invention
Detailed Description
The following describes in further detail embodiments of the present invention with reference to fig. 2-9.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view of a resistive random access memory product formed by the method for manufacturing a resistive random access memory according to the present invention. As shown in the figure, the resistive random access memory comprises at least one resistive random access memory unit; the resistive random access memory unit includes:
the device comprises a first dielectric layer and a lower electrode prepared on the first dielectric layer;
the oxide resistance change layer and the upper electrode are sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; the projected pattern of the upper electrode and the projected pattern of the lower electrode are only partially overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units;
wherein the upper surface of the oxide resistive switching pattern is overlapped with the lower surface of the upper electrode.
In addition, the resistive random access memory further includes:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
a second dielectric layer, and a contact hole and a second metal layer of a CMOS back-end process prepared on the second dielectric layer to lead out the upper electrode;
and two adjacent resistive random access memory units share one lower electrode or one upper electrode.
Similar to the prior art, the present invention also adopts a structure similar to a parallel plate capacitor, i.e. a sandwich structure including an upper Electrode (Top Electrode), a resistance Layer (Switch Layer) and a lower Electrode (Bottom Electrode), wherein the upper and lower electrodes are conductive metals, and the resistance Layer is usually a non-stoichiometric transition metal oxide.
In terms of process implementation, the sandwich structure can be directly embedded into a back-end structure of a mainstream CMOS (complementary metal oxide semiconductor) process, namely, the RRAM structure is directly inserted between two layers of metal on the basis of not changing the parameters of the back-end process of the standard CMOS so as to ensure complete compatibility with the logic process of the standard CMOS, wherein the upper electrode, the lower electrode and the transition metal oxide of the resistive unit are made of metal materials and oxide materials compatible with the CMOS back-end process.
Different from the prior art, the technical scheme of the invention realizes the controllable formation of the oxygen vacancy conduction channel from the aspects of device structure and process manufacturing, and thus the invention becomes an important exploration direction for improving the consistency of the resistance change device. Specifically, a partially overlapped 'upper electrode/resistive layer-lower electrode' structure is prepared based on a standard CMOS back-end process, the size of an overlapped region of the upper electrode and the lower electrode is adjusted by designing a partially overlapped upper electrode layout and a partially overlapped lower electrode layout, and the size of an effective device of a resistive random access memory unit is effectively controlled, so that the effective regulation and control of an oxygen vacancy conductive channel forming region in the resistive layer are realized, the discreteness of the resistive random access device unit can be obviously improved, and the consistency of the device characteristics is improved.
It is clear to those skilled in the art that, due to the advantages of the semiconductor integration process, the resistive random access memory may include at least one resistive random access memory unit, and in the embodiment of the present invention, the resistive random access memory includes two resistive random access memory units as an example for description.
Referring to fig. 2, fig. 2 is a process flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention, and as shown in fig. 2, the method may include the following steps:
step S1: and depositing a first dielectric layer on the surface of the first metal layer of the CMOS back-end process and flattening.
Specifically, referring to fig. 3, a first dielectric layer is deposited on a surface of a first metal layer in a CMOS backend process and planarized by a CMP process, where the first metal layer is any one of interconnection metal layers in a standard CMOS backend process, and is usually a copper metal layer, and the first dielectric layer is a barrier layer with a higher dielectric constant, and is usually a silicon carbide nitride (SiCN) material.
Step S2: and preparing a lower electrode of the resistive random access memory unit in the first dielectric layer and flattening the lower electrode. Specifically, step S2 may include the steps of:
s21: defining a lower electrode pattern of the resistive random access memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer by a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed, thereby completing the preparation of the lower electrode of the resistive random access memory unit in the first dielectric layer.
Referring to fig. 4, a specific process of preparing a lower electrode of a resistive random access memory unit in a first dielectric layer and planarizing is as follows: the method comprises the steps of defining a lower electrode pattern of the resistive random access memory unit in a first dielectric layer through photoetching and etching processes, depositing a lower electrode metal layer through a PVD (physical vapor deposition) process, and finally flattening through a CMP (chemical mechanical polishing) process, wherein the lower electrode material can be conductive materials common to CMOS (complementary metal oxide semiconductor) back-end processes such as Ta, Ti, Cu, W, TaN and TiN.
Step S3: sequentially depositing an oxide resistance-change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode; preferably, the step S3 of depositing the oxide resistance change layer and the upper electrode layer on the surface of the first dielectric layer and the lower electrode in sequence is implemented by using a physical vapor deposition process.
As shown in fig. 5, the deposition process may adopt a PVD process commonly used in a CMOS backend process, the material of the oxide resistive layer may be a dielectric material compatible with the CMOS backend process, such as TaOx, HfOx, TiOx, etc., and the material of the upper electrode may be a conductive material commonly used in the CMOS backend process, such as Ta, Ti, TaN, TiN, etc.
Step S4: imaging the upper electrode layer to prepare an upper electrode of a resistive random access memory unit and imaging the oxide resistive random access layer to prepare an oxide resistive random access graph, wherein only partial areas of the projection graph of the upper electrode and the projection graph of the lower electrode are overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units; the upper surface of the oxide resistance change pattern is superposed with the lower surface of the upper electrode. Preferably, the size of the lower surface of the upper electrode is the same as the size of the upper surface of the oxide resistive switching pattern.
In the embodiment of the present invention, the size of the partial overlapping area in step S4 is smaller than the size of the lower surface of the oxide resistance change pattern and is equal to or larger than zero; wherein the case where the partial overlap region is zero is a case where one side edge of the lower electrode coincides with an opposite side edge of the upper electrode.
Referring to fig. 6, in the resistive switching pattern of the upper electrode and the oxide, which has an adjustable size of the overlapping area with the lower electrode, prepared by photolithography and etching processes, x is the size of the overlapping area of the upper electrode and the lower electrode, and the structure can be adjusted by designing partially overlapped layouts of the upper electrode and the lower electrode. If the size x of the partial overlapping area is zero at the minimum, one side edge of the lower electrode coincides with the opposite side edge of the upper electrode at this time, for example, the right side edge of the lower electrode coincides with the left side edge of the upper electrode, so that the resistive random access memory unit structure is manufactured.
Next, interconnection leading-out of the upper electrode and the lower electrode of the resistance change memory unit needs to be performed, that is, step S5 is executed: and depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process.
Specifically, the step S5 specifically includes:
step S51: depositing barrier layers on the upper surface and the side surface of the upper electrode, the oxide resistance change side surface, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
That is, a prepared resistive random access memory unit structure needs to be protected and isolated, as shown in fig. 7, that is, barrier layers are deposited on the surface and the side surface of the upper electrode, the surface of the lower electrode and the surface of the first dielectric layer, and in order to ensure that the subsequent contact hole etching process is completely compatible with the standard logic process, the barrier layer material is the same as the first dielectric layer material, and is usually a silicon nitride carbide (SiCN) material with a higher dielectric constant. The thickness of the first dielectric layer is smaller than that of the second dielectric layer.
Referring to fig. 8, a second dielectric layer of the CMOS beol process is prepared and planarized, where the second dielectric layer of the CMOS beol process is deposited first and then planarized by a CMP process. Moreover, preferably, the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer; for example, the second dielectric layer is a low-k dielectric layer, usually SiCOH, and the thickness of the second dielectric layer is usually much greater than that of the first dielectric layer.
Step S6: and preparing a contact hole and a second metal layer of a CMOS back-end process in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
Specifically, as shown in fig. 9, a contact hole and a second metal layer of a CMOS back-end process are prepared, and interconnection and extraction of upper and lower electrodes of the resistive random access memory unit are realized. For example, the standard copper damascene process can be used to simultaneously realize the interconnection and extraction of the standard logic device region and the resistive random access memory unit region, and preferably, the etching process parameters of the contact hole can be required to be properly optimized to ensure that the contact hole etching of the resistive random access memory unit and the contact hole etching of the standard logic process can be completed simultaneously, so that the process preparation of the resistive random access memory unit is finally realized.
In summary, it can be seen from the schematic cross-sectional view of the finally prepared resistive random access memory cell that the effective device size of the resistive random access memory cell is the size of the overlapping region of the upper and lower electrodes (as shown by x in fig. 9), and the size can be adjusted by designing the non-overlapping layout of the upper and lower electrodes, so that the formation region of the oxygen vacancy conductive channel in the resistive layer is greatly limited, and the purposes of improving the discreteness of the resistive random access memory cell and improving the uniformity of the device are achieved.
Meanwhile, the whole preparation process of the resistive random access memory unit shows that the preparation method provided by the invention is completely based on a standard CMOS back-end process, the process integration mode of the resistive random access memory unit is completely compatible with a standard logic process, and the materials of the upper electrode, the lower electrode and the resistive layer of the resistive random access memory unit are also completely made of materials which are commonly used in the CMOS back-end process or are compatible with the process, so that the method is very suitable for mass production of future resistive random access memory chips and has a very wide application prospect.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A preparation method of a resistive random access memory comprises at least one resistive random access memory unit, and is characterized by comprising the following steps:
step S1: depositing a first dielectric layer on the surface of a first metal layer of the CMOS back-end process and flattening;
step S2: preparing a lower electrode of the resistive random access memory unit in the first dielectric layer and flattening;
step S3: sequentially depositing an oxide resistance-change layer and an upper electrode layer on the surfaces of the first dielectric layer and the lower electrode;
step S4: imaging the upper electrode layer to prepare an upper electrode of a resistive random access memory unit and imaging the oxide resistive random access layer to prepare an oxide resistive random access graph, wherein only partial areas of the projection graph of the upper electrode and the projection graph of the lower electrode are overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units; the upper surface of the oxide resistance change pattern is superposed with the lower surface of the upper electrode;
step S5: depositing a barrier layer and preparing a second dielectric layer of the CMOS back-end process;
step S6: and preparing a contact hole and a second metal layer of a CMOS back-end process in the second dielectric layer to lead out an upper electrode of the resistive random access memory unit, wherein a lower electrode of the resistive random access memory unit is led out through the first metal layer.
2. The method for manufacturing a resistive random access memory according to claim 1, wherein the step S2 includes:
s21: defining a lower electrode pattern of the resistive random access memory unit in the first dielectric layer through photoetching and etching processes;
s22: depositing a lower electrode metal layer by adopting a physical vapor deposition process;
s23: and flattening the lower electrode metal layer by a chemical mechanical polishing process until the lower electrode metal layer above the first dielectric layer is removed.
3. The method for manufacturing a resistive random access memory according to claim 1, wherein the step S3 of sequentially depositing the oxide resistive layer and the upper electrode layer on the surfaces of the first dielectric layer and the lower electrode is implemented by a physical vapor deposition process.
4. The method for manufacturing the resistive random access memory according to claim 1, wherein the size of the lower surface of the upper electrode is the same as the size of the upper surface of the oxide resistive random access pattern; the size of the partial overlapping area in the step S4 is smaller than the size of the lower surface of the oxide resistance change pattern and is greater than or equal to zero; wherein the case where the partial overlap region is zero is a case where one side edge of the lower electrode coincides with an opposite side edge of the upper electrode.
5. The method for manufacturing the resistive random access memory according to claim 1, wherein the step S5 specifically includes:
step S51: depositing barrier layers on the upper surface and the side surface of the upper electrode, the side surface of the oxide resistance change pattern, the lower electrode and the surface of the first dielectric layer;
step S52: depositing a second dielectric layer of the CMOS back-end process;
step S53: and flattening the second dielectric layer by adopting a chemical mechanical polishing process.
6. The method for manufacturing a resistive random access memory according to claim 5, wherein the material of the barrier layer is the same as the material of the first dielectric layer.
7. The method for manufacturing a resistive random access memory according to claim 1, wherein the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer, and the thickness of the first dielectric layer is smaller than that of the second dielectric layer.
8. The method for manufacturing a resistive random access memory according to claim 1, wherein the lower electrode material of the resistive random access memory cell comprises Ta, Ti, Cu, W, TaN or TiN; the upper electrode material comprises Ta, Ti, TaN or TiN, and the oxide resistance change layer material comprises TaOx, HfOx or TiOx.
9. A Resistive Random Access Memory (RRAM) at least comprises a RRAM unit, and is characterized in that the RRAM unit comprises:
the device comprises a first dielectric layer and a lower electrode prepared on the first dielectric layer;
the oxide resistance change pattern and the upper electrode are sequentially stacked on the upper surfaces of the first dielectric layer and the lower electrode; the projected pattern of the upper electrode and the projected pattern of the lower electrode are only partially overlapped, and the number of the overlapped areas is the same as that of the resistive random access memory units;
wherein the upper surface of the oxide resistive switching pattern is overlapped with the lower surface of the upper electrode.
10. The resistance change memory according to claim 9, further comprising:
the first metal layer is positioned on the lower surfaces of the first dielectric layer and the lower electrode, and the lower electrode is led out through the first metal layer;
a second dielectric layer, and a contact hole and a second metal layer of a CMOS back-end process prepared on the second dielectric layer to lead out the upper electrode;
and two adjacent resistive random access memory units share one lower electrode or one upper electrode.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020132426A1 (en) * | 2001-03-16 | 2002-09-19 | Nec Corporation | Semiconductor memory and process for fabricating the same |
| CN101034708A (en) * | 2006-03-08 | 2007-09-12 | 三星电子株式会社 | Nanowire memory device and method of manufacturing the same |
| TW200735329A (en) * | 2005-11-11 | 2007-09-16 | Sharp Kk | Method for manufacturing nonvolatile semiconductor memory device comprising variable resistive element |
| US20090189136A1 (en) * | 2008-01-28 | 2009-07-30 | Renesas Technology Corp. | Semiconductor device and a manufacturing method of the semiconductor device |
| CN101866942A (en) * | 2009-04-20 | 2010-10-20 | 旺宏电子股份有限公司 | Ring-shaped electrode and manufacturing method for same |
| JP2010245220A (en) * | 2009-04-03 | 2010-10-28 | Panasonic Corp | Nonvolatile memory device, and manufacturing method of the same |
| US20110272664A1 (en) * | 2009-01-09 | 2011-11-10 | Munehiro Tada | Semiconductor device and method of manufacturing the same |
| US20140027701A1 (en) * | 2012-07-26 | 2014-01-30 | SK Hynix Inc. | Variable resistance memory device and method for fabricating the same |
| CN107017341A (en) * | 2017-03-28 | 2017-08-04 | 华中科技大学 | A kind of asymmetric ring-type microelectrode phase-change memory cell and device |
| US20170250222A1 (en) * | 2016-02-25 | 2017-08-31 | Samsung Electronics Co., Ltd. | Variable resistance memory devices |
| US20190058109A1 (en) * | 2017-08-18 | 2019-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a flat bottom electrode via (beva) top surface for memory |
| CN110858622A (en) * | 2018-08-24 | 2020-03-03 | 三星电子株式会社 | Variable resistance memory device |
| WO2020173727A1 (en) * | 2019-02-28 | 2020-09-03 | Tdk Electronics Ag | Capacitor, thermistor or varistor component with overlapping electrodes |
| CN112054121A (en) * | 2020-09-14 | 2020-12-08 | 清华大学 | Resistive random access memory, resistive random access memory chip and preparation method thereof |
-
2020
- 2020-12-31 CN CN202011614888.XA patent/CN112736198B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020132426A1 (en) * | 2001-03-16 | 2002-09-19 | Nec Corporation | Semiconductor memory and process for fabricating the same |
| TW200735329A (en) * | 2005-11-11 | 2007-09-16 | Sharp Kk | Method for manufacturing nonvolatile semiconductor memory device comprising variable resistive element |
| CN101034708A (en) * | 2006-03-08 | 2007-09-12 | 三星电子株式会社 | Nanowire memory device and method of manufacturing the same |
| US20090189136A1 (en) * | 2008-01-28 | 2009-07-30 | Renesas Technology Corp. | Semiconductor device and a manufacturing method of the semiconductor device |
| US20110272664A1 (en) * | 2009-01-09 | 2011-11-10 | Munehiro Tada | Semiconductor device and method of manufacturing the same |
| JP2010245220A (en) * | 2009-04-03 | 2010-10-28 | Panasonic Corp | Nonvolatile memory device, and manufacturing method of the same |
| CN101866942A (en) * | 2009-04-20 | 2010-10-20 | 旺宏电子股份有限公司 | Ring-shaped electrode and manufacturing method for same |
| US20140027701A1 (en) * | 2012-07-26 | 2014-01-30 | SK Hynix Inc. | Variable resistance memory device and method for fabricating the same |
| US20170250222A1 (en) * | 2016-02-25 | 2017-08-31 | Samsung Electronics Co., Ltd. | Variable resistance memory devices |
| CN107017341A (en) * | 2017-03-28 | 2017-08-04 | 华中科技大学 | A kind of asymmetric ring-type microelectrode phase-change memory cell and device |
| US20190058109A1 (en) * | 2017-08-18 | 2019-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a flat bottom electrode via (beva) top surface for memory |
| CN110858622A (en) * | 2018-08-24 | 2020-03-03 | 三星电子株式会社 | Variable resistance memory device |
| WO2020173727A1 (en) * | 2019-02-28 | 2020-09-03 | Tdk Electronics Ag | Capacitor, thermistor or varistor component with overlapping electrodes |
| CN112054121A (en) * | 2020-09-14 | 2020-12-08 | 清华大学 | Resistive random access memory, resistive random access memory chip and preparation method thereof |
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