JP2010245220A - Nonvolatile memory device, and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device using a resistance change layer which can improve the deterioration of a property of the resistance change layer caused by a manufacturing process. <P>SOLUTION: The nonvolatile memory device is equipped with lower layer wiring 15 formed on a substrate 11, a resistance change layer 16 formed at least in part of the lower layer wiring 15, an interlayer insulating layer 17 formed on the substrate 11 that includes the lower layer wiring 15 and the resistance change layer 16, a contact hole 26 formed so that it may penetrate the interlayer insulating layer 17 and is connected to the resistance change layer 16, an embedded electrode 19 formed in the contact hole 26 that is connected to the resistance change layer 16, upper layer wiring 20 that crosses the lower layer wiring 15 and is connected to the embedded electrode 19 on the interlayer insulating layer 17. The resistance change layer 16 at least contains a transition metal oxide of an oxygen-shortage type, and the surface layer of the resistance change layer 16 in a region to which the contact hole 26 is connected is concave-shaped compared with the surface layer of the resistance change layer 16 connected to the contact hole 26 outside the region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a cross-point type nonvolatile memory device using a resistance change layer, and more particularly to a nonvolatile memory device having a structure suitable for miniaturization and a manufacturing method thereof.

  2. Description of the Related Art In recent years, with the advancement of digital technology in electronic devices, development of large-capacity and nonvolatile semiconductor memory devices has been actively performed in order to store data such as music, images, and information. For example, a nonvolatile memory device using a ferroelectric as a capacitor element has already been used in many fields. Further, in contrast to a nonvolatile memory device using such a ferroelectric capacitor, a resistance value is changed by application of an electric pulse, and a nonvolatile memory device (hereinafter referred to as ReRAM) using a material that keeps the state. However, it is attracting attention because it is easy to achieve consistency with normal semiconductor processes.

As the resistance change material of this ReRAM, nickel oxide film (NiO), vanadium oxide film (V ₂ O ₅ ), zinc oxide film (ZnO), niobium oxide film (Nb ₂ O ₅ ), titanium oxide film (TiO ₂ ) A tungsten oxide film (WO ₃ ) or a cobalt oxide film (CoO) is used. Such a transition metal oxide film exhibits a specific resistance value when a voltage or current exceeding a threshold is applied, and the resistance value keeps the resistance value until a new voltage or current is applied. It is known that it can be manufactured using an existing DRAM process as it is.

  For example, a ReRAM having a cross-point type structure in which an active layer made of a resistance change material is interposed at the intersection of a word line and a bit line has been proposed (first conventional example; see, for example, Patent Document 1). FIG. 17 shows a representative drawing for explaining Patent Document 1. This ReRAM has a configuration in which a lower electrode is formed on a substrate, an active layer is formed thereon, and an upper electrode is formed on the active layer so as to be orthogonal to the lower electrode. A region where the lower electrode and the upper electrode intersect constitutes an individual memory element, and the lower electrode and the upper electrode function as either a word line or a bit line, respectively. In this example, the active layer made of a resistance change material is continuously formed across a plurality of memory elements without being separated into individual memory elements. As the active layer, a material whose resistance changes in response to an applied electric signal, for example, a perovskite material such as a giant magnetoresistance (GMR) material or a high-temperature superconducting material has been shown.

  Furthermore, there is also shown a configuration in which a variable resistor made of a resistance change material and a nonlinear element having nonlinear current / voltage characteristics are formed in a plug provided in a region where a word line and a bit line intersect ( Second conventional example (for example, see Patent Document 2). FIG. 18 shows a representative drawing for explaining Patent Document 2. With such a configuration, the selectivity of the memory cell is improved by the switching characteristics of the non-linear element, so that it is possible to realize a ReRAM that can be accessed at high density and at high speed.

JP 2003-68984 A JP 2006-203098 A

  In the first conventional example, as shown in FIG. 17, since the active layer is continuously formed in the region including the cross-point portion composed of the lower electrode and the upper electrode, the proximity increases as the density increases. Crosstalk between the cross points is likely to occur, and it is difficult to increase the capacity.

  Further, in the second conventional example, the selectivity of the memory cell is improved by the switching characteristics of the plug-shaped memory cell provided in the region where the word line and the bit line intersect with each other and the nonlinear element constituting the memory cell. High density and high speed access. However, in order to realize further higher density and higher capacity, it is desirable to form a memory cell using a contact hole provided in a region where a word line and a bit line intersect. However, it is very difficult to form a lower electrode, a variable resistor and an upper electrode, and a non-linear element all in a multilayer structure in a plug as shown in FIG. In addition, the transition metal oxide thin film used for the variable resistor has a problem that it is easily affected by dry etching damage or the like during the manufacturing process and the characteristic variation of the memory element tends to increase.

  Therefore, the present invention solves the above-described conventional problems, and in a ReRAM having a structure that can be miniaturized and increased in capacity, a process of removing the altered layer of the resistance change layer formed in the manufacturing process is performed. An object of the present invention is to provide a nonvolatile memory device capable of stable operation.

  In order to realize a high-density memory array, the nonvolatile memory device of the present invention selects a material suitable for resistance change of the resistance change layer for the embedded electrode formed in the contact hole, The resistance value of the resistance change layer in the contact area is changed. Therefore, the cell resistance is increased and the resistance is increased by changing the composition of the variable resistance layer in the variable resistance region by processes such as film formation and heat treatment of the variable resistance layer and heat treatment, and dry etching for forming the contact hole. There is a problem that deterioration of change characteristics is likely to occur.

  In order to achieve the above object, a method for manufacturing a nonvolatile memory device according to the present invention includes a step of forming a resistance change layer containing an oxygen-deficient transition metal oxide on a wiring layer, and the resistance change layer. Forming an interlayer insulating film thereon, forming a contact hole in the interlayer insulating film by dry etching using an etching gas containing a fluorine compound gas, and forming the variable resistance layer exposed at the bottom of the contact hole The method includes a step of removing a part of the surface layer by dry etching using an inert gas, and a step of forming a buried electrode in the contact hole.

  The method for manufacturing a nonvolatile memory device according to the present invention includes a step (A) of forming a lower layer wiring on a substrate and an oxygen-deficient transition metal oxide in at least a part of the plurality of lower layer wirings. A step (B) of forming a resistance change layer, a step (C) of forming an interlayer insulating layer on the substrate including the plurality of lower layer wirings and the resistance change layer, and an etching gas containing at least a fluorine compound gas A step (D) of forming a contact hole so as to connect to the resistance change layer through the interlayer insulating layer by dry etching used, and a surface layer of the resistance change layer exposed at the bottom of the contact hole. A step (E) of removing the portion by dry etching using an inert gas, and a step (F) of forming a buried electrode connected to the variable resistance layer in the contact hole, Wherein connected to the buried electrode in the interlayer insulating layer, characterized in that it comprises a step (G) to form the upper wiring crossing the lower interconnection.

  Step (E) of removing a part of the surface layer of the variable resistance layer in the region exposed at the bottom of the contact hole by dry etching using an inert gas after opening the contact hole connected to the variable resistance layer, which is a feature of the present invention As a result, the controllability of the cell resistance is improved, and a nonvolatile memory device that operates stably can be manufactured.

  Further, in the step (B) of the above method, the resistance change layer may be formed on the lower layer wiring in the same shape as the lower layer wiring.

  By adopting such a method, by selecting a metal electrode material suitable for the resistance change layer for the lower layer wiring, the lower layer wiring also functions as the lower electrode of the memory portion, so that the manufacturing process can be simplified.

  Further, in the above method, a step (H) of forming a non-ohmic element connected in series to the resistance change layer may be added after the step (F).

  By adopting such a method, it is possible to realize a configuration in which a sufficient current flows in the selected memory cell during reading or writing, but no current flows in the unselected memory cell. Since talk can be prevented, it is possible to manufacture a highly reliable nonvolatile memory device having excellent resistance change characteristic reproducibility.

  According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device having an interlayer insulation including a resistance change layer including an oxygen-deficient transition metal oxide layer formed on a wiring and a contact hole formed on the resistance change layer. The contact hole communicates with the variable resistance layer, and the thickness of the variable resistance layer in the region in contact with the bottom of the contact hole is in the region other than the region in contact with the bottom of the contact hole. It is characterized by being formed thinner than the thickness of the change layer.

  The nonvolatile semiconductor memory device of the present invention includes a substrate, a lower layer wiring formed on the substrate, a resistance change layer formed on at least a part of the lower layer wiring, the lower layer wiring, and the resistance change. An interlayer insulating layer formed on the substrate including a layer, a contact hole penetrating the interlayer insulating layer and connected to the variable resistance layer, and connected to the variable resistance layer, A buried electrode formed in a contact hole; and an upper wiring connected to the buried electrode and intersecting the lower wiring on the interlayer insulating layer, wherein the resistance change layer is an oxygen-deficient transition metal A shape that includes an oxide and has a surface layer portion of the variable resistance layer in a region connected to the contact hole that is recessed compared to a surface layer portion of the variable resistance layer in a region other than the region connected to the contact hole It is characterized in that is.

  By adopting such a configuration, a non-volatile memory device having good controllability of cell resistance and stable operation can be realized in a memory cell structure using contact holes that can be miniaturized and increased in capacity. Is possible. Furthermore, by selecting a material suitable for the resistance change of the variable resistance layer for the buried electrode, only one type of material is needed to be buried in the contact hole, so that the filling process is easy and the manufacturing process can be simplified.

  In the above configuration, the variable resistance layer may have the same shape as the lower layer wiring on the lower layer wiring.

  With such a configuration, by selecting a metal electrode material suitable for the resistance change layer for the lower layer wiring, the lower layer wiring also functions as the lower electrode of the storage unit, and thus the manufacturing process can be simplified.

  Further, in the above configuration, a non-ohmic element may be provided between the embedded electrode and the upper layer wiring.

  By adopting such a configuration, it is possible to realize a configuration in which a sufficient current flows in the selected memory cell during reading or writing, but no current flows in the unselected memory cell. Since talk can be prevented, a highly reliable nonvolatile memory device having excellent reproducibility of resistance change characteristics and high reliability can be realized.

  The non-volatile memory device of the present invention is a non-volatile memory capable of stable operation in a memory cell structure using contact holes, which is suitable for miniaturization and large capacity, by suppressing the change of the resistance change layer due to the manufacturing process. There is a great effect that the device can be realized.

(A) is sectional drawing which shows the structure of the non-volatile memory device for demonstrating the subject of this invention, (b) is sectional drawing which looked at the cross section in the 1A-1A line shown to (a) in the arrow direction The figure which shows the relationship between the resistance value of the non-volatile memory element of FIG. 1, and the electrical pulse application frequency (A) illustrates the depth direction concentration distribution of fluorine using the fluorine-based secondary ion mass spectrometry of TaO _x film which has been subjected to dry etching with an etching gas (SIMS) is, (b) the depth of the carbon The figure which shows a direction concentration distribution, (c) is a figure which shows the depth direction concentration distribution of oxygen Schematic drawing illustrating the analytic results of fluorine contamination layer of TaO _x thin film using X-ray reflectivity measurement method (GIXR) (A) is a top view explaining the structure of the non-volatile memory device based on the 1st Embodiment of this invention, (b) is sectional drawing which looked at the cross section of the 5A-5A line of (a) in the arrow direction (A) is a top view of the elements on larger scale of the principal part for showing the structure of the memory | storage part of the non-volatile memory device in 1st Embodiment, (b) is a cross section of the 6A-6A line of (a) by the arrow Cross section viewed in the direction (A) to (c) in the method of manufacturing the nonvolatile memory device according to the first embodiment, from the formation of the interlayer insulating layer on the substrate on which the active element is formed to the formation of a plurality of lower layer wirings Of the process (A) to (c) in the method for manufacturing a nonvolatile memory device according to the first embodiment, a variable resistance layer having the same shape as a lower layer wiring is formed on a plurality of lower layer wirings, and an interlayer insulating layer is further formed. Showing the process In the method for manufacturing the nonvolatile memory device according to the first embodiment, a diagram illustrating a process of forming a contact hole at a predetermined position of an interlayer insulating layer, (a) is a plan view, (b) and (c) Sectional drawing which looked at the cross section in the 9A-9A line shown to (a) in the arrow direction FIGS. 4A and 4B are diagrams illustrating steps until a buried electrode is embedded in a contact hole in the method for manufacturing a nonvolatile memory device according to the first embodiment. In the method for manufacturing the nonvolatile memory device according to the first embodiment, a plurality of upper layer wirings are formed on the interlayer insulating layer so as to be connected to the buried electrode, (a) is a plan view, (b) Is a sectional view of the section taken along line 11A-11A shown in FIG. The figure which shows the relationship between the resistance value of the non-volatile memory element which concerns on the 1st Embodiment of this invention, and the frequency | count of an electric pulse application (A) is sectional drawing explaining the structure of the non-volatile memory device which concerns on the 2nd Embodiment of this invention, (b) is the non-ohmic element and memory | storage part of the non-volatile memory device in 2nd Embodiment Sectional drawing of the elements on larger scale of the principal part for showing the structure of (A) to (d) in the method for manufacturing a nonvolatile memory device according to the second embodiment, a plurality of lower layer wirings and variable resistance layers are formed in a stripe shape on a semiconductor interlayer insulating layer, and further thereon The figure which shows the process until it forms an interlayer insulation layer which consists of two layers, and forms a contact hole in the interlayer insulation layer FIGS. 9A to 9C are views showing steps of embedding and forming a buried electrode in a contact hole in the method of manufacturing a nonvolatile memory device according to the second embodiment. (A) to (c) show a method of manufacturing the nonvolatile memory device according to the second embodiment, in which a lower electrode that becomes a part of a non-ohmic element is embedded and formed on the embedded electrode in the contact hole; The figure which shows the process until it laminates | stacks and forms the semiconductor layer used as a part of non-ohmic element, an upper electrode, and several upper layer wiring on the interlayer insulation layer containing a lower electrode The figure explaining the 1st prior art example (Drawing 1 of JP, 2003-68984, A) The figure explaining the 2nd prior art example (Drawing 2 of JP, 2003-68984, A)

  The inventors of the present invention have proposed the structure shown in FIG. 1 in order to provide a nonvolatile memory device that can be further miniaturized and has stable characteristics and a method for manufacturing the same.

1 includes a substrate, a plurality of stripe-shaped lower layer wirings formed on the substrate, a resistance change layer formed on at least a part of the plurality of lower layer wirings, and the plurality of lower layers. An interlayer insulating layer formed on a substrate including wiring; a contact hole formed so as to penetrate the interlayer insulating layer and connect to the resistance change layer; and connect to the resistance change layer, And a plurality of upper layer wirings having a stripe shape connected to the embedded electrodes and intersecting the plurality of lower layer wirings on the interlayer insulating layer, and the resistance change layer Is a ReRAM configured to include at least an oxygen-deficient tantalum oxide (TaO _x ).

  Here, in the present invention, “to form the lower layer wiring on the substrate” means that the lower layer wiring is formed directly on the substrate according to a general interpretation, and the other is formed on the substrate. It means both of the case where the lower layer wiring is formed via. The “interlayer insulating layer” is an interlayer insulating layer formed in one process in the manufacturing process of the nonvolatile memory element, and a plurality of interlayers formed in a plurality of processes in the manufacturing process of the nonvolatile memory element. It refers to both the interlayer insulating layer formed by combining the insulating layers into one.

  Next, a method for manufacturing the ReRAM shown in FIG. 1 will be described.

  First, a plurality of stripe-shaped first wiring layers having a two-layer structure of a lower layer wiring 15 and a resistance change layer 16 are formed on a substrate, and an interlayer insulating layer 17 is formed thereon.

  Then, a contact hole that penetrates the interlayer insulating layer 17 and is connected to the resistance change layer 16 is formed by dry etching using an etching gas containing a fluorine compound gas.

  Thereafter, a buried electrode 19 connected to the variable resistance layer is formed in the contact hole, connected to the buried electrode 19 on the interlayer insulating layer 17, and a plurality of stripe-shaped upper layer wirings 20 intersecting with the first wiring layer are formed. . In this configuration, the lower layer wiring 15 and the buried electrode 19 are the lower electrode and the upper electrode of the resistance change layer 16, respectively.

  The structure shown in FIG. 1 is suitable for miniaturization and large capacity, and a stable resistance change operation is possible in a memory cell structure using contact holes.

  However, the resistance change element described in FIG. 1 sometimes deteriorates in resistance change characteristics.

  FIG. 2 shows measurement results of resistance change when an electrical pulse is applied to the ReRAM manufactured by the above process. The horizontal axis is the number of applied electrical pulses, and the vertical axis is the resistance value. The electrical pulse applied during the measurement was 1.8 V and −1.8 V for the upper electrode with the lower electrode as a reference, and the pulse width was 100 ns.

  FIG. 2 is an example of a sample having poor resistance change characteristics when the resistance change element shown in FIG. 1 is operated. The cell resistance value is 10E + 10Ω or higher, which is much higher than a desired value, and does not show resistance change operation. The reason why the resistance value varies between 10E + 10 to 10E + 12Ω is due to noise caused by measurement because of the extremely high resistance near the detection limit. Further, even when the pulse voltage was increased to ± 5 V, no resistance change operation was shown.

  Therefore, the present inventors examined the cause and thought that there might be a problem in the process of opening a contact hole that penetrates the interlayer insulating layer and connects to the resistance change layer made of tantalum oxide. That is, when the variable resistance layer is exposed to an etching gas containing a fluorine compound gas during the dry etching process, radical fluorine contained in the etching gas plasma is mixed in the variable resistance layer, and its composition changes, and the resistance changes. We thought that the change characteristics had deteriorated. In addition, with respect to other oxygen-deficient transition metal oxides showing resistance change characteristics, it is conceivable that fluorine having a stronger oxidizing action than oxygen is likely to be mixed into defects formed due to oxygen deficiency.

  The present inventors conducted the following experiment in order to investigate the influence of an etching gas containing a fluorine compound gas on the film quality of tantalum oxide.

  First, a sample in which a tantalum oxide thin film was deposited on a substrate was prepared, and an impurity element contained in the tantalum oxide was analyzed using secondary ion mass spectrometry (SIMS).

Next, the tantalum oxide surface was dry-etched using a mixed gas of C ₅ F ₈ , O ₂ , and Ar, and then the tantalum oxide thin film was measured using SIMS. Elements measured by SIMS are F, C, and O. FIG. 3 shows the results of investigating the concentration distribution in the depth direction of fluorine, carbon, and oxygen in a tantalum oxide thin film before and after dry etching using a mixed gas of C ₅ F ₈ , O ₂ , and Ar using SIMS. Show.

  The vertical axis represents the fluorine ion count (cps), and the horizontal axis represents the depth (nm) from the surface of the tantalum oxide film. White circles represent data before dry etching, and black circles represent data after dry etching. 3A shows the concentration distribution in the depth direction of fluorine, FIG. 3B shows the concentration distribution in the depth direction of carbon, and FIG. 3C shows the concentration distribution in the depth direction of oxygen.

From the result of FIG. 3A, it became clear that fluorine is mixed into the surface layer of the tantalum oxide thin film by the dry etching process using the fluorine-based gas. Further, when estimated from the half width, it was found that fluorine was mixed in a depth region of less than 5 nm from the surface layer of the tantalum oxide film. Similar results were obtained when other fluorine compound etching gases such as CF ₄ , CHF ₃ , and SF ₆ were used. Note that fluorine ions are observed in the vicinity of the surface even before the dry etching process, which is considered to be background noise due to measurement.

  Further, from the results of FIGS. 3B and 3C, there is no significant change in the concentration distribution of carbon and oxygen in the depth direction before and after dry etching, and the carbon and oxygen contained in the etching gas have an adverse effect on the tantalum oxide. It is thought not to give.

  Therefore, even if the resistance change layer is not exposed to the fluorine compound etching gas, the device structure, or the device structure capable of this, or even if the resistance change layer is exposed to the fluorine-based etching gas and the composition of the resistance change layer is altered, the resistance change layer An additional process for returning the composition of the change layer to the original state is essential.

  Therefore, the present inventors studied a method of removing the surface layer portion of the resistance change layer mixed with fluorine by dry etching using an inert gas Ar.

  First, a sample in which a tantalum oxide thin film was deposited on a substrate was prepared, and analysis using an X-ray reflectometry (GIXR) was performed.

Next, the tantalum oxide thin film was subjected to a dry etching process using a mixed gas of C ₅ F ₈ , O ₂ , and Ar, and then the tantalum oxide thin film was analyzed using GIXR.

Further, tantalum after removing 5 nm of the surface layer of the tantalum oxide thin film subjected to the dry etching process using the mixed gas of C ₅ F ₈ , O ₂ and Ar by dry etching using only the inert gas Ar. The oxide thin film was analyzed using GIXR.

  FIG. 4 shows the results of examining the tantalum oxide thin film in these three samples using the X-ray reflectivity measurement method. In FIG. 4, the horizontal axis represents 2θ (X-ray incident angle θ), and the vertical axis represents X-ray reflectivity.

  (A) in FIG. 4 shows an X-ray reflectivity pattern in a state after the tantalum oxide thin film is deposited, and the solid line in the figure assumes that tantalum oxide exists on the substrate. Then, the result of fitting is shown. The actually measured reflectance pattern and the reflectance pattern obtained by fitting are in good agreement. Therefore, it is considered that the sample (a) is composed only of tantalum oxide.

Next, (b) shows a GIXR measurement result of a sample obtained by subjecting a tantalum oxide thin film to a dry etching process using a mixed gas of C ₅ F ₈ , O ₂ , and Ar. The measurement result of the reflectance pattern of (b) did not agree with the fitting using the model in which only tantalum oxide was present. Further, when 2θ is around 1 °, a large decrease in reflectance is observed. This suggests that a layer having a composition other than tantalum oxide is formed in the vicinity of the surface layer of tantalum oxide. Since it is clear from the results of SIMS analysis in FIG. 3 that only fluorine is mixed in the tantalum oxide thin film by dry etching using a mixed gas of C ₅ F ₈ , O ₂ , and Ar, this tantalum oxidation It can be determined that the film quality layer other than the material is a layer in which fluorine is mixed in tantalum oxide.

  And (c) has shown the X-ray reflectivity pattern of the sample which removed 5 nm of the surface layer of the tantalum oxide which fluorine mixed by dry etching using Ar. The measurement pattern in (c) agrees with the fitting by the model assuming that tantalum oxide is present on the substrate, and the decrease in reflectivity near 2 ° observed in (b) is also disappeared. is doing. From these, it can be seen that the fluorine-containing layer can be removed by dry etching using Ar.

Therefore, it became clear that the fluorine mixed layer formed on the surface layer of the tantalum oxide can be removed by dry etching using Ar gas by dry etching using a mixed gas of C ₅ F ₈ , O ₂ , and Ar. .

  In addition to dry etching using Ar gas, hydrogen annealing and nitrogen annealing were also tried, but the deteriorated layer could not be removed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected about the same element and description may be abbreviate | omitted. Further, the shapes of the transistors, the memory portions, and the like are schematic, and the numbers thereof are easily illustrated.

(First embodiment)
5A and 5B are diagrams for explaining the configuration of the nonvolatile memory device 100 according to the first embodiment of the present invention. FIG. 5A is a plan view, and FIG. 5B is along the line 5A-5A shown in FIG. Sectional drawing which looked at the cross section in the arrow direction is shown. Note that, in the plan view of FIG. 5A, a part of the uppermost insulating protective layer 21 is notched for easy understanding. 6 is a partial enlarged view of a main part for showing the configuration of the storage unit 18. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view along the line 6A-6A shown in FIG. FIG.

  The nonvolatile memory device 100 according to the present embodiment includes a substrate 11, a plurality of stripe-shaped lower layer wirings 15 formed on the substrate 11, and the same shape as the plurality of lower layer wirings 15 on the plurality of lower layer wirings 15. The resistance change layer 16 formed on the substrate 11, the interlayer insulating layer 17 formed on the substrate 11 including the plurality of lower-layer wirings 15 and the resistance change layer 16, and the interlayer insulation layer 17 to penetrate the resistance change layer 16. A contact hole formed so as to be connected, a buried electrode 19 buried in the contact hole and connected to the resistance change layer 16, and a plurality of upper layers connected to the buried electrode 19 and formed on the interlayer insulating layer 17 The variable resistance layer in the region connected to the contact hole has a feature that is recessed as compared with the variable resistance layer in the other region. In other words, the variable resistance layer in the region connected to the contact hole is thinner than the variable resistance layer in the other region.

Further, in the case of the present embodiment, a plurality of upper layer wirings 20 are formed on the interlayer insulating layer 17 in a stripe shape intersecting with the plurality of lower layer wirings 15 having a stripe shape. A plurality of lower layer wirings 15, embedded electrodes 19, and a resistance change layer 16 in a region connected to the embedded electrodes 19 constitute a storage unit 18. The resistance change layer 16 is made of a material containing an oxygen-deficient transition metal oxide that exhibits a resistance change in a nonvolatile manner when an electric signal is applied. However, the oxygen-deficient tantalum oxide (TaO _x ) changes in resistance. This is preferable from the viewpoint of stability of characteristics and reproducibility of production. As shown in FIG. 5, the plurality of upper layer wirings 20 extend outside the region where the storage unit 18 is formed in a matrix.

  Further, in this embodiment, a semiconductor circuit in which an active element 12 such as a transistor is integrated using a silicon single crystal substrate as the substrate 11 is provided. In FIG. 5, the active element 12 is a transistor including a source region 12a, a drain region 12b, a gate insulating film 12c, and a gate electrode 12d. However, not only the active element 12 but also an element generally required for a memory circuit. And including circuitry.

  The plurality of lower layer wirings 15 and the plurality of upper layer wirings 20 are respectively connected to the active elements 12 in a region different from the matrix region in which the storage unit 18 is formed. That is, in FIG. 5, the plurality of lower-layer wirings 15 are connected to the source region 12 a of the active element 12 through the buried conductors 22 and 23 and the wirings 24. The plurality of upper layer wirings 20 are also connected to other active elements (not shown) through the embedded conductors 25 in the same manner.

  The plurality of lower layer wirings 15 are formed by sputtering using, for example, Ti—Al—N alloy, aluminum (Al) or copper (Cu), and easily formed by using an exposure process and an etching process or a damascene process. it can.

For the interlayer insulating layer 18, an insulating oxide material or the like can be used. Specifically, silicon oxide (SiO ₂ ) by CVD method, TEOS-SiO ₂ film formed by CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS), silicon carbonation which is a low dielectric constant material An (SiOC) film or a silicon fluorine oxide (SiOF) film may be used.

Next, the resistance change layer 16 constituting the storage unit 18 includes not only the above TaO _x but also iron oxide, titanium oxide, vanadium oxide, cobalt oxide, nickel oxide, zinc oxide, niobium oxide film, tungsten oxide film, Alternatively, an oxygen-deficient transition metal oxide such as a hafnium oxide film or a zirconium oxide film may be used and formed by a sputtering method or the like. Such an oxygen-deficient transition metal oxide material exhibits a specific resistance value when a voltage or current exceeding a threshold is applied, and the resistance value is newly applied with a pulse voltage or pulse current of a certain magnitude. Until it is done, the resistance value is maintained.

  Next, a method for manufacturing the nonvolatile memory device 100 of the present embodiment will be described with reference to FIGS.

  FIG. 7 is a diagram showing a process from forming the semiconductor interlayer insulating layer 14 on the substrate 11 on which the active element 12 is formed, and further forming a plurality of lower layer wirings 15 and embedded conductors 22. Sectional drawing of the state which formed the semiconductor interlayer insulation layer 14 on the board | substrate 11 in which the active element 12 was formed, (b) is a wiring groove | channel 15a of stripe shape in the predetermined position of the semiconductor interlayer insulation layer 14, and semiconductor electrode wiring FIG. 6C is a cross-sectional view of a state in which a contact hole 22a for connecting to the semiconductor layer 24 is formed, and FIG. 8C is a cross-sectional view of a state in which a plurality of lower-layer wirings 15 and embedded conductors 22 are embedded in the semiconductor interlayer insulating layer 14 by a dual damascene method. is there.

  In FIG. 8, a resistance change layer 16 having the same shape as the lower layer wiring 15 is formed on the plurality of lower layer wirings 15, and further interlayer insulation is formed on the semiconductor interlayer insulating layer 14 including the plurality of lower layer wirings 15 and the resistance change layer 16. FIG. 6A is a diagram illustrating a process until a layer 17 is formed, and FIG. 5A is a cross-sectional view illustrating a state in which a resistance thin film layer 16a to be a resistance change layer 16 is formed on a semiconductor interlayer insulating layer 14 including a plurality of lower wirings 15. (B) is a cross-sectional view of a state in which the resistance change layer 16 is patterned and formed in the same shape as the lower layer wiring 15, and (c) is an interlayer insulation on the semiconductor interlayer insulating layer 14 including the plurality of lower layer wirings 15 and the resistance change layer 16. It is sectional drawing of the state in which the layer 17 was formed.

  Next, FIG. 9 is a diagram showing a process until a contact hole 26 connected to the resistance change layer 16 is formed at a predetermined position of the interlayer insulating layer 17, and FIG. 9A shows a contact with the predetermined position of the interlayer insulating layer. The top view of the state which formed the hole 26, (b) And (c) is sectional drawing which looked at the cross section in the 9A-9A line | wire shown to (a) in the arrow direction. In (b), the contact hole 26 is formed up to the point where the variable resistance layer 16 is exposed. Further, in (c), a part of the surface layer of the resistance change layer 16 exposed at the bottom of the contact hole 26 is removed by dry etching using an inert gas, so that the surface layer of the resistance change layer 16 has a concave shape. It is sectional drawing of the state which became.

  FIG. 10 is a diagram showing a process until the buried electrode 19 is buried in the contact hole 26. FIG. 10A shows an electrode thin film layer 19a that becomes the buried electrode 19 on the interlayer insulating film 17 including the contact hole 26. FIG. 4B is a cross-sectional view in a state where the electrode thin film layer 19a on the interlayer insulating film 17 is removed by CMP.

  Further, FIG. 11 is a view showing a state in which a plurality of upper layer wirings 20 are formed on the interlayer insulating layer 17 so as to be connected to the buried electrode 19, wherein (a) is a plan view and (b) is 11A shown in (a). It is sectional drawing which looked at the cross section in the -11A line in the arrow direction.

  First, as shown in FIG. 7A, a semiconductor interlayer insulating layer 14 is formed on a substrate 11 on which a plurality of active elements 12, embedded conductors 23, semiconductor electrode wirings 24, and a semiconductor interlayer insulating layer 13 are formed. . Conventionally, W is used for the buried conductor 23, and Al is mainly used for the semiconductor electrode wiring 24. However, recently, Cu that can realize low resistance even when miniaturized is used. Further, the semiconductor interlayer insulating layers 13 and 14 also have a fluorine-containing oxide (for example, SiOF), a carbon-containing nitride (for example, SiCN), or an organic resin material (for example, polyimide) in order to reduce parasitic capacitance between wirings. Is used. Also in the present embodiment, for example, Cu can be used as the semiconductor electrode wiring 24, and SiOF, which is a fluorine-containing oxide, can be used as the semiconductor interlayer insulating layers 13 and 14, for example.

  Next, as shown in FIG. 7C, the plurality of lower-layer wirings 15 are embedded in the semiconductor interlayer insulating layer 14, but this can be formed as follows. As shown in FIG. 7B, stripe-shaped wiring grooves 15 a for embedding a plurality of lower layer wirings 15 in the semiconductor interlayer insulating layer 14 and contact holes 22 a for connecting to the semiconductor electrode wirings 24 are formed. These can be easily formed by using a technique used in a general semiconductor process. After forming such wiring trenches 15a and contact holes 22a, after forming a plurality of lower layer wirings 15 and conductor films that will become the buried conductors 22, for example, by performing CMP, the shape as shown in FIG. A plurality of lower layer wirings 15 and embedded conductors 22 can be embedded. In addition, in order to make the plurality of lower layer wirings 15 function as a lower electrode of the storage unit 18, for example, Ti, TiN, TaN, Al, Ti—Al alloy, Ti—Al—N alloy, or these other than Cu described above A stacked configuration may be used.

Next, as illustrated in FIG. 8A, a resistive thin film layer 16 a is formed on the semiconductor interlayer insulating layer 14 including the plurality of lower wirings 15. The resistance thin film layer 16a is made of a material containing an oxygen-deficient transition metal oxide that exhibits a resistance change in a nonvolatile manner when an electric signal is applied. In particular, when the resistive thin film layer 16a is made of tantalum oxide (TaO _x ), reactive sputtering using a tantalum target material is performed, and by adjusting the oxygen gas flow rate ratio relative to the Ar gas flow rate during sputtering, The value of X in the chemical formula of TaO _x can be adjusted.

If it demonstrates according to the process at the time of specific sputtering, first, a board | substrate will be installed in a sputtering device and the inside of a sputtering device will be evacuated to about 7 * 10 <^-4> Pa. Then, using tantalum as a target, sputtering is performed with a power of 250 W, a total gas pressure of Ar gas and oxygen gas of 3.3 Pa, and a set temperature of the substrate of 30 ° C. The film thickness is preferably 30 nm to 100 nm. When the oxygen partial pressure ratio is changed from 1% to 7%, the oxygen content in the tantalum oxide layer changes from about 40% (TaO _0.66 ) to about 70% (TaO _2.3 ). The composition of the tantalum oxide layer can be measured using Rutherford backscattering method. A preferable range is TaO _x (0.8 ≦ x ≦ 1.9).

  As a film forming method, not only sputtering but also CVD method, ALD method, or the like may be used.

  Next, by using an exposure process and dry etching used in a general semiconductor process, a plurality of resistance change layers 16 are formed on a plurality of lower layer wirings 15 as shown in FIG. The lower layer wiring 15 is patterned in the same shape.

Further, as shown in FIG. 8C, an interlayer insulating layer 17 made of TEOS-SiO ₂ is formed on the substrate 11 including the plurality of lower layer wirings 15 and the resistance change layer 16 by using, for example, a CVD method. . As the interlayer insulating layer 17, various materials can be used as described above.

  Further, thereafter, as shown in FIGS. 9A, 9B, and 9C, contact holes 26 are formed in the interlayer insulating layer 17 on the resistance change layer 16 at a constant arrangement pitch. As can be seen from FIG. 9A, the contact hole 26 has an outer shape smaller than the width of the plurality of lower-layer wirings 15 and the resistance change layer 16 formed thereon. In the figure, a quadrangular shape is used, but it may be a circular shape, an elliptical shape, or another shape.

When forming the contact hole 26, as shown in FIG. 9B, first, the interlayer insulating layer 17 is removed by dry etching. For this dry etching, in order to improve the perpendicularity of the contact hole shape, for example, a fluorine-based gas such as CF ₄ , C ₄ F ₆ , or C ₅ F ₈ is generally used.

However, as described above, fluorine is mixed into the surface layer of the TaO _x layer by dry etching using a fluorine-based etching gas.

  Therefore, the surface layer of the resistance change layer 16 in the region exposed at the bottom of the contact hole 26 is further removed by dry etching using only an inert gas such as Ar. As a result, as shown in FIG. 9C, the variable resistance layer in the region exposed at the bottom of the contact hole has a recessed shape as compared with other regions. In the above process, of course, all the contact holes 26 may be formed by using dry etching of an inert gas, but there are problems with the etching rate and the selectivity with the resist, which is not practical.

From the SIMS results in FIG. 3, it can be seen that fluorine is mixed into the depth region of less than 5 nm from the surface layer of the TaO _x film. Therefore, it is preferable to remove the variable resistance layer 16 in the region exposed at the bottom of the contact hole by 5 nm or more from the surface layer by dry etching using an inert gas.

When TaO _x is used as the resistance change layer 16 and is removed by dry etching using Ar gas, the TaO _x film is etched when the Ar flow rate is 100 sccm, the chamber pressure is 2.0 Pa, and the RF power is 900 W. The rate is about 60 nm / min. It is.

  Next, as shown in FIG. 10A, an electrode thin film layer 19 a to be a buried electrode 19 is formed on the interlayer insulating layer 17 including the contact hole 26. The electrode thin film layer 19a serves as an upper electrode of the storage unit 18, and is an electrode material suitable for the resistance change layer. In this embodiment, Pt, Ir, Pd, TaN, Cu, or the like is used.

  Next, as shown in FIG. 10B, the electrode thin film layer 19 a on the interlayer insulating layer 17 is removed using a CMP process, and the embedded electrode 19 is embedded in the contact hole 26. As a method for removing the electrode thin film layer 19a in this way, not only CMP but also an etch back method may be used.

  Next, as shown in FIG. 11, a plurality of upper layer wirings 20 are formed so as to be connected to the buried electrode 19. In this case, the plurality of upper layer wirings 20 are formed on the interlayer insulating layer 17 in a stripe shape that is at least larger than the contact hole 26 and intersects with the plurality of lower layer wirings 15. As the plurality of upper layer wirings 20, the same material as that of the plurality of lower layer wirings 15 can be used.

  When the plurality of upper layer wirings 20 are formed, a buried conductor 25 is also formed at the same time, and is connected to a semiconductor electrode wiring (not shown) through the buried conductor 25 and is provided at a position not shown. Electrically connected to the element.

  Thereafter, by forming an insulating protective layer 21 covering the plurality of upper layer wirings 20, the nonvolatile memory device 100 as shown in FIG. 5 can be manufactured.

  In the present embodiment, the example in which the variable resistance layer is patterned in the same shape as the lower layer wiring is described, but it is not necessarily required to have the same shape. That is, it is sufficient that the resistance change layer is formed at least in a portion communicating with the contact hole and in the vicinity thereof, and is not necessarily formed on the entire surface of the lower layer wiring. Further, the case where the lower layer wiring or the embedded electrode is formed of a single material has been described, but each may have a laminated structure, and in that case, a material suitable for the electrode may be formed on a layer in contact with the resistance change layer, For example, Pt is disposed, and materials suitable for wiring and embedded electrodes, for example, Cu and Al are disposed in the other layers, and W is disposed in the embedded electrodes.

(Example)
A nonvolatile memory device according to Embodiment 1 of the present invention was actually fabricated, and resistance change characteristics were measured.

The plurality of lower-layer wirings 15 are a laminated structure of TiN, AlCu, and TaN, the buried electrode 19 is Pt, the resistance change layer 16 is TaO _1.5 , and the thickness of the resistance change layer 16 is 50 nm. In addition, TEOS-SiO ₂ was used for the interlayer insulating layer 17.

The conditions for forming the contact hole penetrating the interlayer insulating layer and connecting to the variable resistance layer by dry etching are as follows: when removing the interlayer insulating layer, C ₅ F ₈ , O ₂ and Ar are 17 sccm / 23 sccm. The flow rate was / 500 sccm, and the chamber pressure was 2.7 Pa and the RF power was 1800 W. When removing a part of the surface layer of the variable resistance layer in the region exposed at the bottom of the contact hole, the flow rate of Ar is set to 100 sccm, the chamber pressure is set to 2.0 Pa, and the RF power is set to 900 W. Removal to a depth of 5 nm.

  Hereinafter, the measurement results of the manufactured resistance change characteristics will be described.

  FIG. 12 shows measurement results of resistance change when an electrical pulse is applied to the resistance change device manufactured by the above process. The horizontal axis is the number of applied electrical pulses, and the vertical axis is the resistance value. The electrical pulse applied during the measurement was 1.8 V and −1.8 V for the upper electrode with the lower electrode as a reference, and the pulse width was 100 ns.

  From the result of FIG. 12, it can be seen that the resistance of the memory cell in the low resistance state is about 200Ω, and the variation is small. The cell resistance in the high resistance state is a desired value of 10E + 6 to 10E + 7Ω. As for the resistance change operation, it was confirmed that the resistance change operation was repeated alternately from the low resistance state to the high resistance state and further to the low resistance state, and the operation was stable.

  Therefore, by adding a step of removing the fluorine-containing layer formed on the surface layer of the variable resistance layer, which is a feature of the present invention, compared with the measurement result (FIG. 2) when the fluorine-containing layer is not removed. The resistance change characteristics have improved dramatically.

  In this way, in a memory cell structure using contact holes suitable for miniaturization and large capacity, an altered layer that deteriorates resistance change characteristics is formed on the surface of the resistance change layer by a manufacturing process such as dry etching of contact holes. It turns out that there is a problem of being done. Therefore, in the nonvolatile memory device and the manufacturing method of the present invention, the altered layer formed on the surface layer of the variable resistance layer is removed by dry etching using only an inert gas, so that the cell resistance caused by the altered layer is reduced. There is a great effect that it is possible to realize a non-volatile memory device that can improve the ultrahigh resistance and the resistance change operation failure, can easily control the cell resistance to a desired resistance value, and can perform a stable resistance change operation.

(Second Embodiment)
13A and 13B are diagrams for explaining the configuration of the nonvolatile memory device 200 according to the second embodiment of the present invention. FIG. 13A is a cross-sectional view, and FIG. 13B is a configuration of the memory unit 18 and the non-ohmic element 27. It is an expanded sectional view of the part of the important part for showing.

  The non-volatile storage device 200 according to the present embodiment has the same basic configuration as the non-volatile storage device 100 according to the first embodiment, but includes a non-ohmic element 27 connected in series with the storage unit 18. The interlayer insulating layer 17 on the substrate 11 including the lower wiring 15 and the resistance change layer 16 has a two-layer structure.

  In addition, since the basic process of the method for manufacturing a nonvolatile memory element of this embodiment is the same as that of the method of manufacturing the nonvolatile memory element of Embodiment 1, the common process is omitted or simplified. .

  As the non-ohmic element 27, an MSM diode having a three-layer structure including a semiconductor layer and a metal electrode layer sandwiching the semiconductor layer, three layers of an insulator layer and a metal electrode layer sandwiching the insulator layer Any one of a MIM diode having a stacked structure of p, a pn junction diode having a stacked structure of two layers of a p-type semiconductor and an n-type semiconductor, or a Schottky diode having a stacked structure of two layers of a semiconductor layer and a metal electrode layer. It is good to use.

  By inserting a non-ohmic element in series with the variable resistance layer, in the case of a cross-point type ReRAM, crosstalk at the time of reading and writing the resistance value of the variable resistance layer formed at the crossing intersection is performed. Can be reduced.

  Next, the manufacturing method of the present embodiment will be described with reference to FIGS. 14 to 16, only the structure above the semiconductor interlayer insulating layer 14 is shown for simplification of the drawings.

  In FIG. 14, a plurality of lower layer wirings 15 and variable resistance layers 16 are formed in a stripe shape on a semiconductor interlayer insulating layer 14 by sputtering, exposure process, and etching process, and further an interlayer insulating layer having a two-layer structure thereon. 17A and 17B are diagrams showing a process until a contact hole 26 is formed in the interlayer insulating layer 17. FIG. 9A shows a plurality of stripe-shaped lower layer wirings 15 and a resistance change layer 16 formed on the interlayer insulating layer 14. (B) is a cross-sectional view of a state in which an interlayer insulating film 17 having a two-layer structure is formed thereon, and (c) is an interlayer insulating layer 17 having a two-layer structure using dry etching. FIG. 6D is a cross-sectional view of the state where the contact hole 26 is formed until the variable resistance layer 16 is exposed, and FIG. 4D is a dry etch using an inert gas such as Ar as described above. By a cross-sectional view of a state in which to remove a portion of the surface layer of the resistance variable layer 16 exposed in the contact hole 26 bottom.

  FIG. 15 is a diagram illustrating a process of embedding and forming the buried electrode 19 in the contact hole 26. FIG. 15A shows a state in which the electrode thin film layer 19a to be the buried electrode 19 is formed on the interlayer insulating film 17 including the contact hole 26. (B) is a cross-sectional view of the state in which the electrode thin film layer 19a on the interlayer insulating layer 17 has been removed by CMP, and (c) is a state in which the embedded electrode 19 in the contact hole 26 is further overpolished and a recess is formed on the surface layer side. It is sectional drawing of the state which formed.

  In FIG. 16, a lower electrode 28 which is a part of the non-ohmic element 27 is embedded on the embedded electrode 19 in the contact hole 26, and the non-ohmic element 27 is further formed on the interlayer insulating layer 17 including the lower electrode 28. FIG. 6A is a diagram illustrating a process until a semiconductor layer 29 and a top electrode 30 which are a part of the semiconductor layer 29 and a plurality of upper layer wirings 20 are stacked, and FIG. 9A illustrates a non-ohmic element on the interlayer insulating film 17 including the contact hole 26. 27 is a cross-sectional view in a state in which an electrode thin film layer 28a to be a lower electrode 28 is formed, FIG. 5B is a cross-sectional view in a state in which the electrode thin film layer 28a on the interlayer insulating layer 17 is removed by CMP, and FIG. 3 is a cross-sectional view of a state in which a semiconductor layer 29, an upper electrode 30, and a plurality of upper layer wirings 20 as a part of a non-ohmic element 27 are stacked on an interlayer insulating layer 17 including

First, as shown in FIG. 14A, a plurality of lower-layer wirings 15 and resistance change layers 16 are formed in a stripe shape on the semiconductor interlayer insulating layer 14, and as shown in FIG. 14B, Using a CVD method or the like, a first interlayer insulating layer 17a made of, for example, TEOS-SiO ₂ and a film type that is harder to polish in CMP than TEOS-SiO ₂ , for example, a second interlayer insulating layer 17b made of SiON are formed. Laminate. The first interlayer insulating layer 17a and the second interlayer insulating layer 17b constitute an interlayer insulating layer 17. The second interlayer insulating layer 17b acts as a stopper in the CMP process. By forming the second interlayer insulating layer 17b, the CMP when the embedded electrode 19 and the lower electrode 28 are embedded in the contact hole 26 later is formed. The process can be performed easily and reliably.

  Next, as shown in FIGS. 14C and 14D, contact holes 26 for connecting to the resistance change layer 16 are formed in the interlayer insulating layer 17 at a constant arrangement pitch. The contact hole 26 has an outer shape smaller than the width of the plurality of lower wirings 15 and the resistance change layer 16 and is the same as the shape described in FIGS.

  Also in the step of forming the contact hole 26, it is common to use dry etching with a fluorine-based gas in order to ensure the perpendicularity of the contact hole shape. As shown in FIG. The insulating layer 17b and the first interlayer insulating layer 17a are removed by dry etching using a fluorine-based gas, and the contact hole 26 is formed until the variable resistance layer 16 is exposed.

  Further, as shown in FIG. 14D, a part of the surface layer of the resistance change layer 16 exposed at the bottom of the contact hole 26 is removed by dry etching using an inert gas such as Ar.

  Next, as shown in FIG. 15A, an electrode thin film layer 19 a to be a buried electrode 19 is formed on the interlayer insulating layer 17 including the contact hole 26. The electrode thin film layer 19a serves as an upper electrode of the storage unit 18 in the present embodiment, and Pt, Ir, Pd, TaN, Cu, or the like can be used.

  Next, as shown in FIG. 15B, the electrode thin film layer 19 a on the interlayer insulating layer 17 is removed by using a CMP process, and the embedded electrode 19 is embedded in the contact hole 26. In this case, since the second interlayer insulating layer 17b is provided in the interlayer insulating layer 17, the second interlayer insulating layer 17b effectively functions as a CMP stopper, and the interlayer insulating layer 17 is hardly polished. In addition, only the electrode thin film layer 19a can be reliably removed. As a method of removing the electrode thin film layer 19a on the interlayer insulating layer 17 and embedding the buried electrode 19 in this way, etch back may be used instead of CMP.

  Thereafter, as shown in FIG. 15C, further overpolishing is performed to remove a part of the buried electrode 19 in the contact hole 26 on the surface layer side. Even during this overpolishing, the second interlayer insulating layer 17b is provided so that the interlayer insulating layer 17 is hardly polished. In addition, as a method of removing a part of the embedded electrode 19 in this way, not only over-polishing but also a method of etching back may be used.

  Next, as shown in FIG. 16A, an electrode thin film layer 28 a to be the lower electrode 28 of the non-ohmic element 27 is formed on the interlayer insulating layer 17 including the contact hole 26. In the present embodiment, TaN, TiN, or W is formed by sputtering as the electrode thin film layer 28a.

  Next, as shown in FIG. 16B, the electrode thin film layer 28 a on the interlayer insulating layer 17 is removed using a CMP process, and the lower electrode 28 is embedded in the contact hole 26. Also in this case, since the second interlayer insulating layer 17b is provided in the interlayer insulating layer 17, this second interlayer insulating layer 17b effectively acts as a stopper in the CMP process, and the interlayer insulating layer 17 is almost polished. Accordingly, it is possible to reliably remove only the electrode thin film layer 28a.

Next, as shown in FIG. 16C, a semiconductor layer 29 and a top electrode 30 that are part of the non-ohmic element 27 are stacked on the interlayer insulating layer 17 so as to be connected to the bottom electrode 28. Further, a plurality of upper layer wirings 20 are formed on the non-ohmic element 27. In the present embodiment, the semiconductor layer 29, the upper electrode 30, and the plurality of upper layer wirings 20 are formed in a stripe shape intersecting with the plurality of lower layer wirings 15. In the present embodiment, TaN, TiN, or W can be used for the upper electrode 30, and the same material as the lower layer wiring 15 can be used for the upper layer wiring 20. Also, nitrogen-deficient silicon nitride (SiN _x) used as the semiconductor layer 29, forms a MSM diode by the semiconductor layer 29 and the lower electrode 28 and upper electrode 30 which sandwich it.

Note that the SiN _x film having such semiconductor characteristics can be formed by reactive sputtering in a nitrogen gas atmosphere using a Si target, for example. For example, if the chamber pressure is 0.1 Pa and the Ar / N ₂ flow rate is 13 sccm / ₂ sccm at room temperature, an SiN _x film with x = 0.34 can be formed.

When SiN _x having semiconductor characteristics is produced under the above conditions and with a thickness of 16 nm, a current density of 2.5 × 10 ³ A / cm ² is obtained by applying a voltage of 1.6 V, and 0.8 V When the voltage is applied, a current density of 5 × 10 ² A / cm ² is obtained. Therefore, when these voltages are used as a reference, the on / off ratio is 5, which can be sufficiently used as a non-ohmic element of a nonvolatile memory device.

  Through such a process, the storage unit 18 is configured by the plurality of lower-layer wirings 15, the resistance change layer 16, and the embedded electrode 19, and the non-ohmic element 27 is configured by the lower electrode 28, the semiconductor layer 29, and the upper electrode 30. Further, after that, an insulating protective layer (not shown) for protecting the plurality of upper layer wirings 20 is formed. Thereby, the nonvolatile memory device by the manufacturing method of this embodiment can be manufactured.

  Since the nonvolatile memory device of the present invention is a cross-point type memory capable of increasing the capacity, it is useful in various electronic equipment fields using the nonvolatile memory device.

100,200 Nonvolatile memory device (ReRAM)
DESCRIPTION OF SYMBOLS 11 Substrate 12 Active element 12a Source region 12b Drain region 12c Gate insulating film 12d Gate electrode 13, 14 Semiconductor interlayer insulating layer 15 Lower layer wiring 15a Wiring groove 16 Resistance change layer 16a Resistance thin film layer 17 Interlayer insulating layer 17a First interlayer insulating layer 17b Second interlayer insulating layer 18 Storage portion 19 Embedded electrode 19a Electrode thin film layer 20 Upper layer wiring 21 Insulating protective layer 22, 23, 25 Embedded conductor 22a Contact hole 24 Wiring 26 Contact hole 27 Non-ohmic element 28 Lower electrode 29 Semiconductor layer 30 Upper electrode

Claims (8)

Forming a resistance change layer including an oxygen-deficient transition metal oxide on the wiring layer;
Forming an interlayer insulating film on the variable resistance layer;
Forming a contact hole in the interlayer insulating film by dry etching using an etching gas containing a fluorine compound gas;
Removing a part of the surface layer of the variable resistance layer exposed at the bottom of the contact hole by dry etching using an inert gas;
Forming a buried electrode in the contact hole;
A method for manufacturing a non-volatile memory device comprising: Forming a lower layer wiring on the substrate (A);
Forming a resistance change layer containing an oxygen-deficient transition metal oxide on at least a part of the plurality of lower-layer wirings (B);
Forming an interlayer insulating layer on the substrate including the plurality of lower-layer wirings and the resistance change layer;
By dry etching using an etching gas containing at least a fluorine compound gas,
Forming a contact hole so as to penetrate the interlayer insulating layer and connect to the variable resistance layer (D);
Removing a part of the surface layer of the variable resistance layer exposed at the bottom of the contact hole by dry etching using an inert gas;
Forming a buried electrode connected to the variable resistance layer in the contact hole (F);
And (G) forming an upper layer wiring connected to the buried electrode and intersecting the lower layer wiring on the interlayer insulating layer. 3. The method of manufacturing a nonvolatile memory device according to claim 2, wherein, in the step (B), the variable resistance layer is formed on the lower layer wiring in the same shape as the lower layer wiring. The nonvolatile memory according to claim 1, further comprising a step (H) of forming a non-ohmic element between the buried electrode and the upper layer wiring after the step (F). Device manufacturing method. A resistance change layer including an oxygen-deficient transition metal oxide layer formed on the wiring;
An interlayer insulating film having a contact hole formed on the variable resistance layer;
The contact hole leads to the variable resistance layer;
The nonvolatile memory device, wherein a thickness of the variable resistance layer in a region in contact with the bottom of the contact hole is thinner than a thickness of the variable resistance layer in a region other than a region in contact with the bottom of the contact hole. A substrate,
A lower layer wiring formed on the substrate;
A resistance change layer formed on at least a part of the lower layer wiring;
An interlayer insulating layer formed on the substrate including the lower layer wiring and the resistance change layer;
A contact hole formed through the interlayer insulating layer and connected to the resistance change layer;
A buried electrode connected to the variable resistance layer and formed in the contact hole;
An upper layer wiring connected to the buried electrode and intersecting the lower layer wiring on the interlayer insulating layer,
The variable resistance layer includes an oxygen-deficient transition metal oxide, and a surface layer portion of the variable resistance layer in a region other than a region where a surface layer portion of the variable resistance layer in a region connected to the contact hole is connected to the contact hole A non-volatile memory device characterized by having a concave shape as compared with a portion. The nonvolatile memory device according to claim 6, wherein the variable resistance layer is formed in the same shape as the lower layer wiring on the lower layer wiring. The nonvolatile memory device according to claim 6, further comprising a non-ohmic element between the embedded electrode and the upper layer wiring.

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