WO2022143886A1

WO2022143886A1 - Resistive memory and preparation method therefor

Info

Publication number: WO2022143886A1
Application number: PCT/CN2021/143023
Authority: WO
Inventors: 郭奥
Original assignee: 上海集成电路装备材料产业创新中心有限公司; 上海集成电路研发中心有限公司
Priority date: 2020-12-31
Filing date: 2021-12-30
Publication date: 2022-07-07
Also published as: CN112701222A; CN112701222B

Abstract

A resistive memory and a preparation method therefor. The method comprises: depositing a first dielectric layer on a surface of a first metal layer of a CMOS back-end process; preparing a bottom electrode contact hole in the first dielectric layer; sequentially depositing a bottom electrode layer and an isolation dielectric layer in the first dielectric layer and the bottom electrode contact hole, so as to prepare a linear bottom electrode of a resistive memory cell; sequentially depositing an oxide resistance switching layer and a top electrode layer, and preparing a top electrode and an oxide resistance switching pattern, so as form a resistive memory cell; depositing a protection layer on surfaces and side faces of the top electrode and the oxide resistance switching pattern as well as a surface of the first dielectric layer, and preparing a second dielectric layer of the CMOS back-end process; and preparing a second metal layer and a contact hole of the CMOS back-end process on the second dielectric layer, so as to lead out a top electrode of the resistive memory cell, and a bottom electrode of the resistive memory cell being led out by means of the first metal layer.

Description

A kind of resistive memory and preparation method thereof

cross reference

This application claims the priority of the Chinese Patent Application No. 202011614887.5 filed on December 31, 2020. The contents of the aforementioned applications are incorporated herein by reference.

technical field

The invention belongs to the field of integrated circuit manufacturing, and in particular relates to a resistive memory and a preparation method thereof.

technical background

Resistive Random Access Memory (RRAM) is compatible with Complementary Metal Oxide Semiconductor (CMOS) process.

FIG. 1 is a schematic structural diagram of a resistive memory cell in the prior art. An oxygen vacancy-based conductive filament channel is induced in the oxide resistive switching layer by an external electric field (in the figure, two S-type resistive switching layers are formed in the oxide resistive switching layer). Lines), and further control the connection and disconnection of the conductive filament channels through different operating voltages of the upper and lower electrodes to form a stable high and low resistance state. However, the oxygen vacancy conduction channel formed in the oxide resistive switching layer is usually very uncontrollable due to the excessively large overlapping area of the upper and lower electrodes, resulting in a large dispersion of electrical characteristics, which seriously restricts the industrial application of resistive memory.

Therefore, improving the consistency of resistive switching devices and realizing the controllable formation of oxygen vacancy conduction channels from the aspects of device structure and process manufacturing is one of the key technologies to promote the industrial application of RRAM technology.

Summary of Invention

The invention proposes a method for preparing a resistive memory that is compatible with CMOS technology, and prepares an upper and lower electrode structure with adjustable overlapping area size based on a standard CMOS process, so as to limit the formation area of an oxygen vacancy conduction channel in the resistive layer, and improve the resistive device unit. consistency.

A method for preparing a resistive memory, the resistive memory comprising at least one resistive memory cell; comprising the following steps:

S1: depositing a first dielectric layer on the surface of the first metal layer in the CMOS back-end process and planarizing the first dielectric layer;

S2: preparing a lower electrode contact hole of the resistive memory cell in the first dielectric layer;

S3: sequentially depositing a lower electrode layer and an isolation dielectric layer in the first dielectric layer and the lower electrode contact hole; planarizing the isolation dielectric layer through a chemical mechanical polishing process to remove the dielectric layer above the first dielectric layer an electrode layer to form a linear lower electrode of the resistive memory cell;

S4: depositing an oxide resistive switching layer and an upper electrode layer in sequence, and preparing the upper electrode and oxide resistive switching pattern, so as to form the resistive switching memory cell; wherein, the upper surface of the oxide resistive switching pattern and the The lower surfaces of the upper electrodes overlap, and the linear lower electrodes in the lower electrode contact holes are in contact with the lower surface of the oxide resistive layer;

S5: depositing a protective layer on the surface of the upper electrode and the oxide resistive pattern, and on the surface of the first dielectric layer, and preparing the second dielectric layer of the CMOS back-end process;

S6: Prepare a contact hole and a second metal layer of the CMOS back-end process on the second dielectric layer to lead out the upper electrode of the resistive memory cell, and the lower electrode of the resistive memory cell passes through the first metal layer extraction.

Further, the S3 includes:

S31: the lower electrode layer is first deposited by physical vapor deposition or atomic layer deposition process on the surface of the first dielectric layer and the lower electrode contact hole, wherein the lower electrode material includes Ta, Ti, TaN or TiN;

S32: depositing an isolation dielectric layer on the surface of the lower electrode layer using a chemical vapor deposition process;

S33: Using a chemical mechanical polishing process to planarize the isolation dielectric layer to remove the electrode layer above the first dielectric layer, so as to form a linear lower electrode of the resistive memory cell.

Further, the material of the isolation dielectric layer is the same as the material of the first dielectric layer,

Further, the thickness of the isolation dielectric layer is greater than the height of the lower electrode contact hole.

Further, the size of the lower surface of the upper electrode is the same as the size of the upper surface of the oxide resistive pattern; the width of the lower electrode formed by S4 is determined by the thickness of the deposition of the lower electrode layer.

Further, the oxide resistance change layer and the upper electrode layer are sequentially deposited by a physical vapor deposition process, the upper electrode material includes Ta, Ti, TaN or TiN, and the oxide resistance change layer material includes TaOx, HfOx, or TiOx.

Further, in the step S5, photolithography and etching processes are used to prepare the upper electrode and the oxide resistance change pattern, and the etching stop layer is the first dielectric layer.

Further, the material of the protective layer is the same as that of the first dielectric layer.

Further, the first dielectric layer and the second dielectric layer are common dielectric materials between two interconnect metal layers in a standard CMOS process, wherein the dielectric constant of the first dielectric layer is higher than that of the second dielectric The dielectric constant of the layer.

Further, the thickness of the first dielectric layer is much smaller than the thickness of the second dielectric layer.

Another technical solution of the present invention includes: a resistive memory, the resistive memory includes at least one resistive memory unit; characterized in that, the resistive memory unit includes:

The first dielectric layer is provided with a lower electrode contact hole, the lower electrode contact hole includes a linear lower electrode and an isolation dielectric layer, and one side of the linear lower electrode is close to a side wall of the lower electrode contact hole, so The other side of the linear lower electrode is close to the isolation dielectric layer;

A resistive oxide pattern and an upper electrode are sequentially stacked on the upper surface of the first dielectric layer; wherein, the top surface of the resistive oxide pattern and the bottom surface of the top electrode are overlapped, and the contact hole of the bottom electrode is in the contact hole. The top of the line-shaped lower electrode is in contact with the lower surface of the oxide resistive switching layer.

Further, the resistive memory also includes:

a first metal layer, in contact with the bottom lower surface of the line-shaped lower electrode, the line-shaped lower electrode is drawn out through the first metal layer; wherein, two adjacent line-shaped lower electrodes are located in one of the lower In the electrode contact hole, the bottom of the line-shaped lower electrode is connected, and the top of the line-shaped lower electrode in the lower electrode contact hole is in contact with the lower surface of the oxide resistive pattern;

The second metal layer is located on the upper surface of the upper electrode to lead out the upper electrode.

The method for preparing a resistive memory of the present invention prepares an asymmetric "upper electrode/resistive layer-lower electrode" structure based on a standard CMOS back-end process, wherein the upper electrode and the resistive layer are of a flat plate structure, and the lower electrode is of a linear structure, The effective device size of the resistive memory cell is adjusted by the thickness of the lower electrode film deposition, and the oxygen vacancy conduction channel formation area in the resistive switching layer is effectively regulated, which significantly improves the discreteness of the resistive switching device unit and improves the consistency of device characteristics.

The preparation method of the present invention is based on the standard CMOS back-end process, the process integration method of the resistive memory cell is fully compatible with the standard logic process, and the upper and lower electrodes and the resistive layer pattern of the resistive memory cell are commonly used or compatible with the CMOS back-end process. The material is suitable for the mass production of resistive memory chips in the future.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a resistive memory based on a conventional technical solution.

2 is a process flow diagram of a method for manufacturing a resistive memory device proposed in an embodiment of the present invention

3 to 12 are schematic cross-sectional views of products corresponding to the method for manufacturing a resistive memory proposed in an embodiment of the present invention

SUMMARY OF THE INVENTION

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings 2-12.

FIG. 11 is a schematic cross-sectional view of a resistive memory product formed by the resistive memory manufacturing method proposed in the present invention. As shown in the figure, the resistive memory includes at least one resistive memory unit; the resistive memory unit includes:

The resistive memory also includes a first metal layer and a second metal layer, the first metal layer is in contact with the bottom lower surface of the linear lower electrode, and the linear lower electrode is drawn out through the first metal layer; Wherein, two adjacent line-shaped lower electrodes are located in one of the lower electrode contact holes, the bottoms of the line-shaped lower electrodes are connected, and the top of the line-shaped lower electrodes in the lower electrode contact hole is connected to the oxide The lower surface of the resistance change pattern is in contact; the second metal layer is located on the upper surface of the upper electrode to lead out the upper electrode.

The present invention also adopts a structure similar to a parallel plate capacitor, that is, a sandwich structure including an upper electrode (Top Electrode), a resistive layer (Switch Layer) and a lower electrode (Bottom Electrode), wherein the upper and lower electrodes are conductive Alteration layers are typically non-stoichiometric transition metal oxides.

In terms of process implementation, the sandwich structure can usually be directly embedded in the back-end structure of the mainstream CMOS process, that is, the RRAM structure can be directly inserted between the two layers of metal without changing the standard CMOS back-end process parameters, so as to ensure the compatibility with the standard CMOS process parameters. The CMOS logic process is fully compatible, and the upper and lower electrodes and transition metal oxides of the resistive switching unit are usually selected from metal materials and oxide materials that are compatible with the CMOS back-end process.

The technical solution in the present invention realizes the controllable formation of the oxygen vacancy conduction channel from the aspects of device structure and process manufacturing, which can improve the consistency of the resistive switching device. Specifically, the sandwich structure of the present invention is based on the standard CMOS back-end process to prepare an asymmetric "upper electrode/resistance switching layer-lower electrode" structure, wherein the upper electrode and the resistive switching layer are plate structures, and the lower electrode is a linear structure, In addition, the lower electrode can adjust the effective device size of the resistive memory cell through the thickness of the deposited film of the bottom electrode, so as to effectively control the formation area of the oxygen vacancy conduction channel in the resistive switching layer, which can significantly improve the discreteness of the resistive switching device unit. , to improve the consistency of device characteristics.

Based on the advantages of the semiconductor integration process, the resistive memory may include at least one resistive memory cell. In this embodiment, the resistive memory includes two resistive memory cells as an example for description.

Please refer to FIG. 12 in conjunction with FIG. 2 . FIG. 12 is a process flow diagram of a method for fabricating a resistive memory according to an embodiment of the present invention. It should be noted that, in FIG. 2 , for example, T5 represents that this step is represented by the cross section shown in FIG. 5 . As shown in Figure 12, the method for preparing a resistive memory includes:

S1: depositing a first dielectric layer on the surface of the first metal layer in the CMOS back-end process and planarizing the first dielectric layer.

Referring to FIG. 3, a first dielectric layer is deposited on the surface of the first metal layer of the CMOS back-end process and planarized by a CMP process. The first metal layer is any interconnect metal layer in the standard CMOS back-end process. It is usually a copper metal layer; the first dielectric layer is a barrier layer with a higher dielectric constant, usually a silicon carbide nitride (SiCN) material.

S2: Prepare a lower electrode contact hole of the resistive memory cell in the first dielectric layer. In this embodiment, a photolithography and etching process in a standard CMOS process can be used to prepare the lower electrode contact hole of the resistive memory cell in the first dielectric layer.

S3: sequentially depositing a lower electrode layer and an isolation dielectric layer in the first dielectric layer and the lower electrode contact hole; planarizing the isolation dielectric layer through a chemical mechanical polishing process to remove the dielectric layer above the first dielectric layer electrode layer to form the linear lower electrode of the resistive memory cell (as shown in FIG. 5 ).

S3 specifically includes:

S31: firstly deposit the lower electrode layer on the surface of the first dielectric layer and the lower electrode contact hole by using a physical vapor deposition or atomic layer deposition process, wherein the lower electrode material includes Ta, Ti, TaN or TiN;

In this embodiment, the PVD or ALD process is used to deposit the lower electrode layer, and the lower electrode material can be selected from Ta, Ti, TaN, TiN and other conductive metal materials commonly used in CMOS back-end processes; then, CVD is used on the surface of the lower electrode layer. process to deposit an isolation dielectric layer, wherein the thickness of the isolation dielectric layer is recommended to be greater than the height of the lower electrode contact hole, so as to avoid the formation of voids in the lower electrode contact hole region by the subsequent chemical mechanical polishing (CMP) planarization process. In addition, preferably, the material of the isolation dielectric layer needs to be the same as the material of the first dielectric layer, usually silicon carbide nitride (SiCN), so that the subsequent integration process of the resistive memory cell region is fully compatible with the CMOS standard logic process, and finally , using a CMP planarization process to prepare a linear lower electrode pattern of a resistive memory cell. Specifically, the lower electrode layer and the isolation dielectric layer above the first dielectric layer are completely removed by the CMP process, and only the lower electrode layer and the isolation dielectric layer in the lower electrode contact hole are retained, so that a linear shape can be formed on the sidewall of the lower electrode contact hole. The lower electrode pattern (as shown in FIG. 6 ), wherein the width of the lower electrode is determined by the thickness of the deposition of the lower electrode layer.

S4: depositing an oxide resistive switching layer and an upper electrode layer in sequence, and preparing the upper electrode and oxide resistive switching pattern, so as to form the resistive switching memory cell; wherein, the upper surface of the oxide resistive switching pattern and the The lower surfaces of the upper electrodes overlap, and the line-shaped lower electrodes in the lower electrode contact holes are in contact with the lower surface of the oxide resistive switching layer.

Specifically, the above steps are used to prepare the resistive switching layer and the upper electrode layer of the resistive switching memory cell. As shown in Figure 7, the PVD process is used to deposit the oxide resistive layer and the upper electrode layer in turn. The upper electrode material can be selected from Ta, Ti, TaN, TiN and other conductive metal materials commonly used in CMOS back-end processes. The resistive layer material can be selected from dielectric materials compatible with CMOS back-end processes such as TaOx, HfOx, and TiOx. Subsequently, the photolithography and etching processes in the standard CMOS process flow are used to prepare the upper electrode and the oxide resistance change pattern. Preferably, the etching stop layer is the above-mentioned first dielectric layer, thereby forming the resistance change memory cell structure, such as shown in Figure 8.

Further, the size of the lower surface of the upper electrode is the same as the upper surface of the oxide resistive layer; the width of the lower electrode formed in step S3 is determined by the thickness of the lower electrode layer deposited.

Further, perform interconnection and extraction of the upper electrode of the resistive memory cell, that is, perform S5: deposit a protective layer on the surface of the upper electrode and the oxide resistive pattern, and on the surface of the first dielectric layer, and prepare CMOS The second dielectric layer of the back-end process.

Specifically, the prepared resistive memory cell structure is first protected and isolated. As shown in FIG. 9 , barriers are first deposited on the surface and side surfaces of the upper electrode layer, the lower electrode layer and the surface of the first dielectric layer. In order to ensure that the subsequent contact hole etching process is fully compatible with the standard logic process, the material of the barrier layer here can be the same as the material of the first dielectric layer, which is usually a silicon carbide nitride (SiCN) material with a higher dielectric constant.

Next, please refer to FIG. 10 , the second dielectric layer of the CMOS back-end process is prepared and planarized. Here, the second dielectric layer of the CMOS back-end process is deposited first, and then the CMP process is used for planarization. The second dielectric layer is The LK dielectric layer with a lower dielectric constant is usually a SiCOH material, and the thickness of the second dielectric layer is usually much larger than that of the first dielectric layer.

Finally, the contact holes and the second metal layer of the CMOS back-end process are prepared to realize the interconnection and extraction of the upper electrodes of the resistive memory cell (as shown in FIG. 11 ). That is, S6 is performed: the contact holes and the second metal layer of the CMOS back-end process are prepared in the second dielectric layer, so as to lead out the upper electrode of the resistive memory cell, and the lower electrode of the resistive memory cell passes through the first A metal layer leads out.

In this embodiment, a standard copper damascene process can be used to realize the interconnection extraction of the standard logic device region and the resistive memory cell region at the same time, and the etching process parameters of the contact holes also need to be properly optimized to ensure the resistive change. The etching of the contact hole of the memory cell and the etching of the contact hole of the standard logic process can be completed at the same time, and finally the process preparation of the resistive memory cell is realized.

In summary, the effective device size of the resistive memory cell is the width of the line-shaped lower electrode (as shown by x in Figure 11), which can be directly adjusted by the thickness of the PVD-deposited film, with very high process flexibility , the formation area of the oxygen vacancy conduction channel in the resistive switching layer can also be flexibly adjusted.

The above descriptions are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and drawings of the present invention shall be included in the The invention is within the scope of protection of the appended claims.

Claims

A method for preparing a resistive memory, the resistive memory comprising at least one resistive memory cell, characterized in that it includes the following steps:

S1: depositing a first dielectric layer on the surface of the first metal layer in the CMOS back-end process and planarizing the first dielectric layer;

S2: preparing a lower electrode contact hole of the resistive memory cell in the first dielectric layer;

S3: sequentially depositing a lower electrode layer and an isolation dielectric layer in the first dielectric layer and the lower electrode contact hole; planarizing the isolation dielectric layer through a chemical mechanical polishing process to remove the dielectric layer above the first dielectric layer an electrode layer to form a linear lower electrode of the resistive memory cell;

S4: depositing an oxide resistive switching layer and an upper electrode layer in sequence, and preparing an upper electrode and an oxide resistive switching pattern, so as to form the resistive switching memory cell; wherein, the upper surface of the oxide resistive switching pattern and the upper electrode are The lower surface of the lower electrode is overlapped, and the linear lower electrode in the lower electrode contact hole is in contact with the lower surface of the oxide resistive pattern;

S5: depositing a protective layer on the surface of the upper electrode and the oxide resistive pattern, and on the surface of the first dielectric layer, and preparing the second dielectric layer of the CMOS back-end process;

S6: Prepare a contact hole and a second metal layer of the CMOS back-end process on the second dielectric layer to lead out the upper electrode of the resistive memory cell, and the lower electrode of the resistive memory cell passes through the first metal layer extraction.
The method according to claim 1, wherein the step S3 comprises:

S31: firstly deposit the lower electrode layer on the surface of the first dielectric layer and the lower electrode contact hole by using a physical vapor deposition or atomic layer deposition process, wherein the lower electrode material includes Ta, Ti, TaN or TiN;

S32: depositing an isolation dielectric layer on the surface of the lower electrode layer by using a chemical vapor deposition process;

S33: Using a chemical mechanical polishing process to planarize the isolation dielectric layer to remove the electrode layer above the first dielectric layer, so as to form a linear lower electrode of the resistive memory cell.
The method according to claim 2, wherein the material of the isolation dielectric layer is the same as the material of the first dielectric layer.
The method according to claim 2, wherein the thickness of the isolation dielectric layer is greater than the height of the lower electrode contact hole. In the step S5, photolithography and etching processes are used to prepare the upper electrode and the oxide resistance change pattern, and the etching stop layer is the first dielectric layer.
The method according to claim 1, wherein the size of the lower surface of the upper electrode is the same as the size of the upper surface of the oxide resistive pattern; the width of the lower electrode formed in step S4 is determined by the thickness of the deposition of the lower electrode layer Sure.
The method according to claim 1, wherein the oxide resistive layer and the upper electrode layer are sequentially deposited by a physical vapor deposition process, the upper electrode material comprises Ta, Ti, TaN or TiN, and the oxide The material of the resistance switching layer includes TaOx, HfOx, or TiOx.
The method according to claim 1, wherein the material of the protective layer is the same as the material of the first dielectric layer.
The method according to claim 1, wherein the dielectric constant of the first dielectric layer is higher than the dielectric constant of the second dielectric layer, and the thickness of the first dielectric layer is smaller than that of the second dielectric layer thickness.
A resistive memory, the resistive memory includes at least one resistive memory unit, characterized in that the resistive memory unit includes:

The first dielectric layer is provided with a lower electrode contact hole, the lower electrode contact hole includes a linear lower electrode and an isolation dielectric layer, and one side of the linear lower electrode is close to a side wall of the lower electrode contact hole, so The other side of the linear lower electrode is close to the isolation dielectric layer;

A resistive oxide pattern and an upper electrode are sequentially stacked on the upper surface of the first dielectric layer; wherein, the top surface of the resistive oxide pattern and the bottom surface of the top electrode are overlapped, and the contact hole of the bottom electrode is in the contact hole. The top of the line-shaped lower electrode is in contact with the lower surface of the oxide resistive pattern.
The resistive memory according to claim 9, further comprising:

a first metal layer, in contact with the bottom lower surface of the line-shaped lower electrode, and the line-shaped lower electrode is drawn out through the first metal layer; wherein, two adjacent line-shaped lower electrodes are located in one of the lower In the electrode contact hole, the bottom of the line-shaped lower electrode is connected, and the top of the line-shaped lower electrode in the lower electrode contact hole is in contact with the lower surface of the oxide resistive pattern;

The second metal layer is located on the upper surface of the upper electrode to lead out the upper electrode.