CN101572248A - Resistance memory and method for fabricating integrated circuit with same - Google Patents
Resistance memory and method for fabricating integrated circuit with same Download PDFInfo
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- CN101572248A CN101572248A CNA2008101053104A CN200810105310A CN101572248A CN 101572248 A CN101572248 A CN 101572248A CN A2008101053104 A CNA2008101053104 A CN A2008101053104A CN 200810105310 A CN200810105310 A CN 200810105310A CN 101572248 A CN101572248 A CN 101572248A
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Abstract
The invention relates to a method for fabricating an integrated circuit with a resistance memory, comprising the following steps: providing an interlaminar dielectric layer comprising a core component area and a peripheral circuit area; forming a first interconnection structure and a second interconnection structure in the interlaminar dielectric layer; respectively forming a first dielectric layer and a second dielectric layer on the surface of the first interconnection structure and on the surface of the second interconnection structure; forming first conductive layers covering the interlaminar dielectric layer, the first dielectric layer and the second dielectric layer; removing a first conductive layer and a second conductive layer on the peripheral circuit area to expose the second interconnection structure and only keeping the first conductive layer on the first dielectric layer in the core component area; and respectively forming a second conductive layer and a third conductive layer on the first conductive layer of the first dielectric layer and on the second interconnection structure. Due to the adoption of the method for fabricating the integrated circuit with the resistance memory, when the resistance memory is formed, the interlaminar interconnection structure of the core component area and the peripheral circuit area can be also formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of Memister, contain integrated circuit of Memister and preparation method thereof.
Background technology
Current, it is low that exploitation has a cost, and speed is fast, and the storage density height is made simple and is subjected to worldwide extensive concern with the compatible good novel memory technology of current CMOS (Complementary Metal Oxide Semiconductor) (CMOS) semiconductor integrated circuit technique.Memory techniques based on the resistive random access memory (RRAM) of the metal oxide with resistance switch characteristic is the emphasis that at present how tame device manufacturer is developed, because this technology can provide more high density, the more low-cost and Nonvolatile memory of low power consumption more.The memory cell of RRAM resistance value after applying pulse voltage can produce great changes, and this resistance value still can be kept down behind deenergization.In addition, RRAM has performances such as anti-irradiation, high-low temperature resistant, against violent vibration are moving, anti-electronic jamming.
Document " non-volatile resistive switching for advanced memory application " (AnChen, et, al., IEDM Technical Digest, Dec.2005, Page 746) provided a kind of Memister structure, with reference to the accompanying drawings shown in 1, has Semiconductor substrate 100, be formed with in the described substrate and comprise source electrode 110 and drain electrode 120 and be positioned on the Semiconductor substrate 100 grid structure 130 across source electrode 110 and drain electrode 120, tungsten plug 140 and interconnection copper cash 150 are used for inter-level interconnects, 160 is the bottom electrode of described Memister, it for example is tungsten, metallic copper etc., the storage medium of 170 resistance-variables that form for the described bottom electrode of oxidation is tungsten oxide for example, materials such as cupric oxide, 180 is the top electrode that forms on storage medium 170, can be the double-decker of Ti/TiN, it is interconnected that interconnection copper cash or interconnection aluminum steel 190 are used for interlayer.
And, the manufacture craft of described Memister normally forms bottom electrode 160 in dielectric layer, with the described lower electrode material of rear oxidation, form storage medium 170, subsequently, on described storage medium 170, form photomask, exposure, the described photomask that develops exposes described storage medium 170, deposition forms top electrode 180 on described storage medium, and is last, removes described photomask, described technology is after forming storage medium 170, on storage medium 170, carry out repeatedly semiconductor fabrication process, can cause unnecessary damage to the interfacial structure of storage medium 170, influenced the performance of described Memister.
And in the prior art, for the integrated circuit that contains Memister, the interconnection structure of other memory carries out separately respectively in the formation technology of Memister and the integrated circuit, therefore, and complex manufacturing technology.
Summary of the invention
In view of this, the technical problem that the present invention solves provides a kind of manufacture craft that contains the integrated circuit of Memister, makes the interconnection structure of other memory of described Memister and integrated circuit simultaneously.
The present invention also provides a kind of Memister.
The invention provides a kind of manufacture method that contains the integrated circuit of Memister, comprising:
Semiconductor substrate is provided and is positioned at interlayer dielectric layer on the Semiconductor substrate, described Semiconductor substrate and interlayer dielectric layer comprise core devices zone and peripheral circuit region;
In the interlayer dielectric layer in core devices zone, form first interconnection structure, in the interlayer dielectric layer of peripheral circuit region, form second interconnection structure, first interconnection structure is used to be electrically connected the semiconductor device in core devices zone, and second interconnection structure is used to be electrically connected the semiconductor device of peripheral circuit region;
On first interconnection structure, form first dielectric layer, on second interconnection structure, form second dielectric layer;
Form first conductive layer that covers interlayer dielectric layer and first dielectric layer and second dielectric layer;
Remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure,, remove first conductive layer on the interlayer dielectric layer, keep first conductive layer on first dielectric layer in the core devices zone;
On first conductive layer and second interconnection structure, form second conductive layer and the 3rd conductive layer respectively.
Wherein, remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, remove first conductive layer on the interlayer dielectric layer, the processing step that keeps first conductive layer on first dielectric layer is:
Formation is positioned at core devices zone and the mask corresponding with the position of first dielectric layer;
Etching first conductive layer, second dielectric layer are until exposing second interconnection structure;
Remove described mask.
Wherein, remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, remove first conductive layer on the interlayer dielectric layer, the processing step that keeps first conductive layer on first dielectric layer is:
Formation is positioned at core devices zone and the mask corresponding with the position of first dielectric layer;
Etching first conductive layer is to exposing interlayer dielectric layer;
Remove described mask;
Remove second dielectric layer of peripheral circuit region.
Wherein, described first dielectric layer is the dielectric film with binary resistance characteristic that oxidation forms the metal formation of described first interconnection structure, the dielectric film with binary resistance characteristic of perhaps described first dielectric layer for forming by depositing operation.
Described first conductive layer is metallic aluminium or titanium nitride, tantalum nitride or metal Pt.The thickness of first conductive layer is 20nm to 80nm.
Described second conductive layer be in metallic aluminium, titanium nitride or the tantalum nitride any one or several.Preferably, described second conductive layer composite construction that is titanium nitride-aluminium-titanium nitride.
Wherein, described first interconnection structure and second interconnection structure are metallic copper or tungsten.
Wherein, the described manufacture method that contains the integrated circuit of Memister also is included in the processing step that forms the dielectric layer that covers second conductive layer and the 3rd conductive layer on the interlayer dielectric layer.
A kind of Memister comprises, as first interconnection structure of bottom electrode, as first dielectric layer of storage medium layer and as first conductive layer and second conductive layer of top electrode.
Wherein, described first interconnection structure is metallic copper or tungsten.
Described first dielectric layer is the dielectric film with binary resistance characteristic that oxidation forms the metal formation of described first interconnection structure, the dielectric film with binary resistance characteristic of perhaps described first dielectric layer for forming by depositing operation.
Described first conductive layer directly adopts depositing operation to be formed on first conductive layer surface, is metallic aluminium or titanium nitride, tantalum nitride or metal Pt, and thickness is 20nm to 80nm.
Described second conductive layer be in metallic aluminium, titanium nitride or the tantalum nitride any one or several, preferred, described second conductive layer is the composite construction of titanium nitride-aluminium-titanium nitride.
Compared with prior art, such scheme has the following advantages:
The manufacture method that contains the integrated circuit of Memister provided by the invention when forming Memister, can realize the inter-level interconnects structure of core devices zone and peripheral circuit region, and technology is simple.
And, adopting the described process of present embodiment, the bottom electrode of formed Memister is the interior inter-level interconnects structure of dielectric layer of integrated circuit, has simplified the manufacture craft of Memister; Storage medium layer can be the metal oxide that the direct oxidation bottom electrode forms, and also can adopt chemical vapour deposition (CVD) or physical gas-phase deposition to form on bottom electrode, the process flexible and controllable, and material selectivity is wide.
During metal oxide that described storage medium layer forms for the direct oxidation bottom electrode, because the pollution that subsequent technique is not received at the interface of bottom electrode/storage medium layer has higher interface quality.
Compared with prior art, the top electrode of Memister of the present invention is made of jointly first conductive layer and second conductive layer, when making described Memister and integrated circuit, the influence of subsequent technique is not received at the interface of first conductive layer and storage medium layer, interface quality is good, therefore, the Memister that present embodiment provides has the good bottom electrode/storage medium layer and the contact interface of storage medium layer/top electrode, the better performances of the Memister of formation.
Description of drawings
Fig. 1 is the structural representation of prior art Memister;
Fig. 2 to Figure 10 contains the cross section structure schematic diagram of manufacture method of the integrated circuit of Memister for the present invention.
Embodiment
The object of the present invention is to provide a kind of manufacture method that contains the integrated circuit of Memister, described method is carried out the manufacture craft of interconnect architecture of the peripheral circuit of Memister and integrated circuit simultaneously, has simplified the processing step of integrated circuit.
The present invention also aims to provide a kind of Memister, the contact surface of the storage medium of described Memister and top electrode and bottom electrode has better surface properties.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Embodiment 1
Present embodiment provides a kind of manufacture method that contains the integrated circuit of Memister, comprising:
Semiconductor substrate is provided and is positioned at interlayer dielectric layer on the Semiconductor substrate, described Semiconductor substrate and interlayer dielectric layer comprise core devices zone and peripheral circuit region;
In the interlayer dielectric layer in core devices zone, form first interconnection structure, in the interlayer dielectric layer of peripheral circuit region, form second interconnection structure, first interconnection structure is used to be electrically connected the semiconductor device in core devices zone, and second interconnection structure is used to be electrically connected the semiconductor device of peripheral circuit region;
On first interconnection structure, form first dielectric layer, on second interconnection structure, form second dielectric layer;
Form first conductive layer that covers interlayer dielectric layer and first dielectric layer and second dielectric layer;
Remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure,, remove first conductive layer on the interlayer dielectric layer, keep first conductive layer on first dielectric layer in the core devices zone;
On first conductive layer and second interconnection structure, form second conductive layer and the 3rd conductive layer respectively.
Remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, remove first conductive layer on the interlayer dielectric layer, the processing step that keeps first conductive layer on first dielectric layer is: formation is positioned at core devices zone and the mask corresponding with the position of first dielectric layer; Etching first conductive layer, second dielectric layer are until exposing second interconnection structure; Remove described mask.
Remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, remove first conductive layer on the interlayer dielectric layer, keep first conductive layer on first dielectric layer processing step can also for: form and be positioned at core devices zone and the mask corresponding with the position of first dielectric layer; Etching first conductive layer is to exposing interlayer dielectric layer; Remove described mask; Remove second dielectric layer of peripheral circuit region.
With reference to the accompanying drawings shown in 2, Semiconductor substrate 200 is provided and is positioned at interlayer dielectric layer 211 on the Semiconductor substrate 200, described Semiconductor substrate 200 can be doped silicon or semi-conducting materials such as silicon-on-insulator and SiGe.
Described interlayer dielectric layer 211 is located immediately on the Semiconductor substrate 200, and in multilevel integration, described interlayer dielectric layer 211 can also be one deck in the multilayer insulation dielectric material on the Semiconductor substrate.
Be formed with semiconductor device for example memory, transistor etc. in described Semiconductor substrate and the interlayer dielectric layer, can also be formed with other input or output circuit or line.
The material of described interlayer dielectric layer 211 can be silicon dioxide or fluorine silex glass insulating material such as (FSG), adopts chemical vapor deposition method to be formed on Semiconductor substrate or the described first dielectric material layer usually.
In the present embodiment, for the convenience of describing, described Semiconductor substrate 200 and interlayer dielectric layer 211 are divided into two zones, as shown in accompanying drawing 2, area I, be the core devices zone, be used to form the core devices of semiconductor device, Memister for example, area I I, be peripheral circuit region, be used to form the peripheral circuit of semiconductor device.
In an embodiment of present embodiment, Semiconductor substrate 200 is provided, described Semiconductor substrate is doped silicon or silicon-on-insulator, interlayer dielectric layer 211 is positioned on the described Semiconductor substrate 200, be formed with semiconductor device in described Semiconductor substrate and the interlayer dielectric layer, at core devices zone I, described semiconductor device is NMOS or PMOS, with the PMOS device is example, be formed with N trap 201 in the core devices zone I of Semiconductor substrate, described PMOS device also has the grid structure 203 that is positioned on the Semiconductor substrate 200, be arranged in the source electrode 204 and the drain electrode 205 of N trap of the Semiconductor substrate 200 of grid structure 203 both sides, also be formed with isolation structure 202 in the described Semiconductor substrate, described isolation structure is fleet plough groove isolation structure or deep trench isolation structure, is used for the isolation between the active area.
In the present embodiment, the peripheral circuit region II of Semiconductor substrate 200 and interlayer dielectric layer 211, the peripheral circuit that forms is transistor for example, as shown in Figure 2, be formed with N trap or P trap 210 in the peripheral circuit region II of Semiconductor substrate 200, described transistor also has the grid structure 213 that is positioned on the Semiconductor substrate 200, is arranged in the source electrode 214 and the drain electrode 215 of the Semiconductor substrate 200 of grid structure 213 both sides.
Be formed with first interconnection structure 206 and second interconnection structure 216 respectively on regional I of the core devices of described interlayer dielectric layer 211 and peripheral circuit region II, the metal material of described formation first interconnection structure 206 is unrestricted, can use W, Pt, Al, Cu, Ni, Co, Mo, Au, Ru, Ir, Ag, Pd, Ti etc. are suitable as the metal material of Memister hearth electrode and integrated circuit interlayer line, preferably, select metallic copper or tungsten for use.
In the present embodiment, the source electrode of the semiconductor device of described first interconnection structure 206 and core devices zone I or drain electrode or grid are electrically connected, and second interconnection structure 216 is electrically connected with the peripheral circuit of peripheral circuit region II, second interconnection structure 216 is electrically connected with grid shown in the accompanying drawing, in fact, can also be connected with the source electrode of peripheral circuit region device or drain electrode and other position that need be electrically connected, in the present embodiment, the metal material that forms second interconnection structure 216 can be W, Pt, Al, Cu, Ni, Co, Mo, Au, Ru, Ir, Ag, Pd, Ti etc., preferable alloy tungsten.
For the metallic atom that prevents described first interconnection structure 206 and second interconnection structure 216 spreads to the electric connection structure of source electrode, drain electrode and the grid structure of adjacent interlayer dielectric layer 211 or electrical connection, inwall at first interconnection structure 206 and second interconnection structure 216 also is formed with barrier layer (not indicating among the figure) respectively, and the material on described barrier layer is titanium nitride for example.
The formation method on described barrier layer is a prior art, the preparation method of first interconnection structure 206 and second interconnection structure 216 is also unrestricted, can have the preparation method who fills the hole ability for chemical vapor deposition (CVD), ald (ALD), magnetron sputtering, physical deposition, electron beam evaporation, thermal evaporation etc., preferably, adopt chemical vapor deposition method.
Present embodiment provides a kind of embodiment, for example, in described interlayer dielectric layer, form first opening and second opening (not marking among the figure) respectively, described first opening is positioned at core devices zone I, with the source electrode of semiconductor device or being electrically connected of drain electrode, described second opening is positioned at peripheral circuit region II, be electrically connected with the grid structure of peripheral circuit device, adopt chemical vapor deposition method on first opening and the second opening inwall and interlayer dielectric layer 211, to form the barrier layer, on described barrier layer, adopt the chemical vapour deposition technique deposits conductive material then, adopt barrier layer and electric conducting material on the CMP (Chemical Mechanical Polishing) process removal interlayer dielectric layer 211 at last, form first interconnection structure 206 and second interconnection structure 216 respectively, expose interlayer dielectric layer 211.
With reference to the accompanying drawings shown in 3, on first interconnection structure 206 and second interconnection structure, 216 surfaces, form first dielectric layer 207 and second dielectric layer 217, the technology that forms first dielectric layer 207 and second dielectric layer 217 is preferably: first interconnection structure 206 of oxidation core devices zone and peripheral circuit region and second interconnection structure, 216 lip-deep electric conducting materials, the preferred thermal oxidation technology of described oxidation technology, first dielectric layer 207 of formation and the thickness range of second dielectric layer 217 are 10-30nm.
Owing to first dielectric layer 207 is that described first interconnection structure 206 of direct heat oxidation forms, therefore, the first dielectric layer/contact interface of first interconnection structure is not received the influence of other semiconductor fabrication process, and is functional.
The material of described first dielectric layer 207 and second dielectric layer 217 is the dielectric films with binary resistance characteristic, and the character of semi-conducting material is generally arranged.
When the electric conducting material of first interconnection structure 206 and second interconnection structure 216 was tungsten, described first dielectric layer and second dielectric layer were tungsten oxide (WO
X), when the electric conducting material of first interconnection structure 206 and second interconnection structure 216 was metallic copper, described first dielectric layer and second dielectric layer were cupric oxide (CuO
X).
On the other hand, the formation technology of described first dielectric layer 207 and second dielectric layer 217 can also be: adopt the technology of chemical vapour deposition (CVD) or physical vapour deposition (PVD), directly deposit WO on first interconnection structure 206 and second interconnection structure 216
X, TiO
2, NiO, ZrO
2, HfO
2, CeO
2, RuO
X, CuO
X, SrZrO
3Or (Pr, Ca) MnO
3Have the material of switching effect etc. any resistance, described material can switch between high-impedance state and low resistance state under outer field action.
With reference to the accompanying drawings shown in 4, form first conductive layer 212 that covers interlayer dielectric layer 211 and first dielectric layer 207 and second dielectric layer 217, the material of described first conductive layer 212 is a metallic aluminium, metal nitride such as titanium nitride, tantalum nitride, perhaps noble metal such as metal Pt and other are suitable as the electric conducting material of Memister top electrode.
The thickness of described first conductive layer 212 is 20nm to 80nm, and the formation technology of described first conductive layer 212 is chemical vapor deposition method or physical gas-phase deposition etc. for example.
On first dielectric layer 207, directly deposit first conductive layer 212, and, the described subsequently processing step of present embodiment does not all have influence on the contact interface of first dielectric layer/first conductive layer, and therefore, the contact interface of first dielectric layer/first conductive layer is functional.
Accompanying drawing 5 to accompanying drawing 9 has provided first conductive layer and second dielectric layer of removing peripheral circuit region, expose second interconnection structure, in the core devices zone, the first kind of embodiment that only keeps first conductive layer on first dielectric layer, with reference to the accompanying drawings shown in 5, on first conductive layer 212, form mask layer 218, described mask layer 218 for example is a photoresist layer, with reference to the accompanying drawings shown in 6, exposure, described photoresist layer 218 develops, remove the photoresist layer outside the photoresist of peripheral circuit region II and the core devices zone I position corresponding with first interconnection structure 206, only keep the photoresist layer on first conductive layer corresponding with first interconnection structure 206, with reference to the accompanying drawings shown in 7, with described photoresist layer 218 is mask, etching first conductive layer 212, expose interlayer dielectric layer 211, after the etching, have only first conductive layer 212 on core devices zone I and first dielectric layer, 206 correspondence positions to be retained, the technology of etching first conductive layer 212 is any prior art well known to those skilled in the art, for example dry etching; Shown in 8, remove photoresist layer with reference to the accompanying drawings, technology for example adopts photoresist ashing technology.
With reference to the accompanying drawings shown in 9, with first conductive layer 212 is mask, core devices zone I and peripheral circuit region II are carried out etching, until second dielectric layer 217 of removing peripheral circuit region II fully, etching is removed in the technology of second dielectric layer 217, also can remove the interlayer dielectric layer of part, after etching technics is finished, as shown in Figure 9, at core devices zone I, have first dielectric layer 207 and first conductive layer 212 on first interconnection structure 206 successively, at peripheral circuit region II, second dielectric layer 217 and first conductive layer 212 on second interconnection structure 216 are removed fully, and therefore, realization peripheral circuit region second interconnection structure 216 is electrically connected with external circuit.
Adopt described first conductive layer 212 as mask, etching is removed after second dielectric layer, and in the core devices zone, the contact interface of first dielectric layer and first conductive layer is not subjected to the influence of etching technics, and interface quality is good.
Adopt first kind of embodiment, avoided the trickle influence to the second interconnection structure surface of the cineration technics of photoresist is kept the second good interconnection structure surface.
On the other hand, remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, the second kind of embodiment that only keeps first conductive layer on first dielectric layer, can be: with reference to the accompanying drawings shown in 5, on first conductive layer 212, form mask layer 218, described mask layer 218 for example is a photoresist layer, with reference to the accompanying drawings shown in 6, exposure, described photoresist layer 218 develops, remove the photoresist layer outside the photoresist of peripheral circuit region II and the core devices zone I position corresponding with first interconnection structure 206, only keep the photoresist layer on first conductive layer corresponding with first interconnection structure 206, then, with described photoresist layer is mask, etching is removed first conductive layer outside the position of first interconnection structure, 206 correspondences, afterwards, continue etching, until second dielectric layer 217 of removing peripheral circuit region fully, expose second interconnection structure 216 of peripheral circuit region, at last, adopt the technology of ashing to remove described photoresist layer, directly form the integrated circuit structure shown in the accompanying drawing 9.
Adopt described second kind of embodiment, directly etching is removed second interconnection structure of first conductive layer and peripheral circuit region, and afterwards, described photoresist layer is removed in ashing again, simplified processing step, and, when the ashing photoresist, second interconnection structure there is trickle oxidation, but, after photoresist ashing, conventional cleaning is all arranged, cleaning can be removed the pettiness oxide layer on the second interconnection structure surface.
With reference to the accompanying drawings shown in 10, deposits conductive material on second interconnection structure of first conductive layer of core devices zone I and peripheral circuit region II forms second conductive layer 209 and the 3rd conductive layer 219 respectively.The technology that forms described second conductive layer 209 and the 3rd conductive layer 219 is chemical vapour deposition (CVD) or physical vapour deposition (PVD) etc.
Described second conductive layer 209 and the 3rd conductive layer 219 materials are metallic aluminium, titanium nitride, tantalum nitride, metal Pt etc. are suitable as the electric conducting material of Memister top electrode, can also be in the described material one or several, for example, described second conductive layer 209 and the 3rd conductive layer 219 are the composite construction of titanium nitride-aluminium-titanium nitride.
At core devices zone I, the common formation of first interconnection structure, first dielectric layer, first conductive layer and second conductive layer has variable-resistance Memister, wherein, first interconnection structure is the bottom electrode of described Memister, first dielectric layer is the storage medium layer of Memister, and first conductive layer and second conductive layer constitute the top electrode of Memister jointly.
At peripheral circuit region II, second interconnection structure and the 3rd conductive layer are realized the inter-level interconnects of peripheral circuit as the interlayer wiring of peripheral circuit region.
Adopt the described process of present embodiment, when forming Memister, can realize the inter-level interconnects structure of core devices zone and peripheral circuit region, technology is simple.
And, adopting the described process of present embodiment, the bottom electrode of formed Memister is the interior inter-level interconnects structure of dielectric layer of integrated circuit, has simplified the manufacture craft of Memister; Storage medium layer can be the metal oxide that the direct oxidation bottom electrode forms, and also can adopt chemical vapour deposition (CVD) or physical gas-phase deposition to form on bottom electrode, the process flexible and controllable, and material selectivity is wide.
During metal oxide that described storage medium layer forms for the direct oxidation bottom electrode, because the pollution that subsequent technique is not received at the interface of bottom electrode/storage medium layer has higher interface quality.
Compared with prior art, top electrode is made of jointly first conductive layer and second conductive layer, when making described Memister and integrated circuit, the influence of subsequent technique is not received at the interface of first conductive layer and storage medium layer, interface quality is good, therefore, the Memister that present embodiment provides has the good bottom electrode/storage medium layer and the contact interface of storage medium layer/top electrode, the better performances of the Memister of formation.
And second conductive layer is formed directly on first conductive layer, and the scope that material is selected compares broad.
Embodiment 2
Present embodiment provides a kind of Memister, shown in 10, comprises with reference to the accompanying drawings, as first interconnection structure 206 of bottom electrode, as first dielectric layer 207 of storage medium layer and as first conductive layer 212 and second conductive layer 209 of top electrode.
Wherein, described first interconnection structure 206 is metallic copper or tungsten, forms simultaneously with second interconnection structure 216 of the peripheral circuit region of accompanying drawing 10 described integrated circuits, and forming technology is any prior art well known to those skilled in the art.
Described first dielectric layer 207 can be that direct oxidation first interconnection structure 206 forms preferred thermal oxidation technology.Or the technology of employing chemical vapour deposition (CVD) or physical vapour deposition (PVD), the directly WO of deposition on first interconnection structure 206
X, TiO
2, NiO, ZrO
2, HfO
2, CeO
2, RuO
X, CuO
X, SrZrO
3Or (Pr, Ca) MnO
3Have the material of switching effect etc. any resistance, described material can switch between high-impedance state and low resistance state under outer field action.
The Memister of present embodiment forms the first dielectric layer process flexible and controllable, and material selectivity is wide.During metal oxide that described storage medium layer forms for the direct oxidation bottom electrode, because the pollution that subsequent technique is not received at the interface of bottom electrode/storage medium layer has higher interface quality.
The thickness of described first conductive layer 212 is 20nm to 80nm, directly adopt depositing operation to be formed on first conductive layer surface, described depositing operation comprises physical vapour deposition (PVD) and chemical vapour deposition (CVD), and material is for being suitable as the material of Memister top electrode for metal nitride such as metallic aluminium or titanium nitride, tantalum nitride or metal Pt and other.
Described second conductive layer be metal nitrides such as metallic aluminium or titanium nitride, tantalum nitride or metal Pt and other be suitable as in the material of Memister top electrode any one or several.For example, described second conductive layer composite construction that is titanium nitride-aluminium-titanium nitride.
Compared with prior art, top electrode is made of jointly first conductive layer and second conductive layer, when making described Memister, the influence of subsequent technique is not received at the interface of first conductive layer and storage medium layer, interface quality is good, therefore, the Memister that present embodiment provides has the good bottom electrode/storage medium layer and the contact interface of storage medium layer/top electrode, the better performances of the Memister of formation.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (19)
1. a manufacture method that contains the integrated circuit of Memister is characterized in that, comprising:
Semiconductor substrate is provided and is positioned at interlayer dielectric layer on the Semiconductor substrate, described Semiconductor substrate and interlayer dielectric layer comprise core devices zone and peripheral circuit region;
In the interlayer dielectric layer in core devices zone, form first interconnection structure, in the interlayer dielectric layer of peripheral circuit region, form second interconnection structure, first interconnection structure is used to be electrically connected the semiconductor device in core devices zone, and second interconnection structure is used to be electrically connected the semiconductor device of peripheral circuit region;
On first interconnection structure, form first dielectric layer, on second interconnection structure, form second dielectric layer;
Form first conductive layer that covers interlayer dielectric layer and first dielectric layer and second dielectric layer;
Remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure,, remove first conductive layer on the interlayer dielectric layer, keep first conductive layer on first dielectric layer in the core devices zone;
On first conductive layer and second interconnection structure, form second conductive layer and the 3rd conductive layer respectively.
2. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that, remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, the processing step that only keeps first conductive layer on first dielectric layer is:
Formation is positioned at core devices zone and the mask corresponding with the position of first dielectric layer;
Etching first conductive layer, second dielectric layer are until exposing second interconnection structure;
Remove described mask.
3. according to the described manufacture method that contains the integrated circuit of Memister of claim 1, it is characterized in that, remove first conductive layer and second dielectric layer of peripheral circuit region, expose second interconnection structure, in the core devices zone, the processing step that only keeps first conductive layer on first dielectric layer is:
Formation is positioned at core devices zone and the mask corresponding with the position of first dielectric layer;
Etching first conductive layer is to exposing interlayer dielectric layer;
Remove described mask;
Remove second dielectric layer of peripheral circuit region.
4. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that first dielectric layer is the dielectric film with binary resistance characteristic that forms the metal formation of described first interconnection structure by oxidation.
5. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that first dielectric layer is the dielectric film with binary resistance characteristic that forms by depositing operation.
6. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that described first conductive layer is metallic aluminium or titanium nitride, tantalum nitride or metal Pt.
7. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that the thickness of first conductive layer is 20nm to 80nm.
8. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that, described second conductive layer be in metallic aluminium, titanium nitride or the tantalum nitride any one or several.
9. the described according to Claim 8 manufacture method that contains the integrated circuit of Memister is characterized in that described second conductive layer is the composite construction of titanium nitride-aluminium-titanium nitride.
10. according to each described manufacture method that contains the integrated circuit of Memister in the claim 1 to 3, it is characterized in that described first interconnection structure and second interconnection structure are metallic copper or tungsten.
11. a Memister comprises, as first interconnection structure of bottom electrode, as first dielectric layer of storage medium layer and as first conductive layer and second conductive layer of top electrode.
12. Memister according to claim 11 is characterized in that, described first dielectric layer is the dielectric film with binary resistance characteristic that oxidation forms the metal formation of described first interconnection structure.
13. Memister according to claim 11 is characterized in that, the dielectric film with binary resistance characteristic of described first dielectric layer for forming by depositing operation.
14. Memister according to claim 11 is characterized in that, described first conductive layer directly adopts depositing operation to be formed on the first dielectric layer surface.
15. Memister according to claim 11 is characterized in that, described first interconnection structure is metallic copper or tungsten.
16. Memister according to claim 11 is characterized in that, described first conductive layer is metallic aluminium or titanium nitride, tantalum nitride or metal Pt.
17. Memister according to claim 11 is characterized in that, the thickness of described first conductive layer is 20nm to 80nm.
18. Memister according to claim 11 is characterized in that, described second conductive layer be in metallic aluminium, titanium nitride or the tantalum nitride any one or several.
19. Memister according to claim 18 is characterized in that, described second conductive layer is the composite construction of titanium nitride-aluminium-titanium nitride.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101053104A CN101572248B (en) | 2008-04-28 | 2008-04-28 | Resistance memory and method for fabricating integrated circuit with same |
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|---|---|---|---|
| CN2008101053104A CN101572248B (en) | 2008-04-28 | 2008-04-28 | Resistance memory and method for fabricating integrated circuit with same |
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