CN106486484A - Semiconductor structure and its manufacture method - Google Patents
Semiconductor structure and its manufacture method Download PDFInfo
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- CN106486484A CN106486484A CN201510553281.8A CN201510553281A CN106486484A CN 106486484 A CN106486484 A CN 106486484A CN 201510553281 A CN201510553281 A CN 201510553281A CN 106486484 A CN106486484 A CN 106486484A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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Abstract
The invention discloses a kind of semiconductor structure and its manufacture method.This kind of semiconductor structure includes an access device, a dielectric layer, a barrier layer, one first interlayer conductor, one first potential barrier lining, one second interlayer conductor, one second potential barrier lining, a memory element and a top electrode layer.Access device has two terminals.Dielectric layer overlap access device.Barrier layer is arranged on the dielectric layer.First and second interlayer conductor is respectively connecting to two terminals.First and second potential barrier lining is separately positioned on the side wall of first and second interlayer conductor.Memory element is arranged on the first interlayer conductor.Top electrode layer is arranged on barrier layer and memory element, and covers memory element.
Description
Technical field
The present invention be with regard to a kind of semiconductor structure and its manufacture method.The present invention is especially with regard to one kind
Semiconductor structure and its manufacture method including barrier structure, the barrier structure are particularly the barrier junction of hydrogen
Structure.
Background technology
Variable resistance type memory (RRAM) is a type of nonvolatile memory, and which provides letter
The structure, little memory cell size of list, scalability (scalability), ultrahigh speed operation, low work(
Rate operation, high-durability (endurance), good retentivity (retention), big on-off ratio, CMOS
Compatible, inexpensive the advantages of.One type of RRAM includes memory element, such as a metal oxygen
Compound layer.For example, by applying electric pulse, the resistance of memory element can be two or more are steady
Change between fixed resistance range.
In CMOS technology, some steps may be carried out under the atmosphere for including hydrogen (H-2).This
Outward, for example, during the high-temperature step in technique, some elements in manufactured structure may
Release hydrogen.Hydrogen may be unfavorable for the retentivity of memory element.
Content of the invention
In view of above-mentioned situation, here provides a kind of semiconductor structure and its manufacture method.The semiconductor
Structure particularly includes a barrier structure, especially the barrier structure of hydrogen.
According to some embodiments, the semiconductor structure includes an access device, a dielectric layer, a potential barrier
Layer, one first interlayer conductor, one first potential barrier lining, one second interlayer conductor, one second potential barrier lining
Layer, a memory element and a top electrode layer.Access device has two terminals.Dielectric layer overlap access
Device.Barrier layer is arranged on the dielectric layer.First interlayer conductor extends through barrier layer and dielectric layer.
First interlayer conductor is connected to the one of which of two terminals.First potential barrier lining is arranged on the first interlayer
On the side wall of conductor.First interlayer conductor and dielectric layer are physically separated by the first potential barrier lining
Come.Second interlayer conductor extends through barrier layer and dielectric layer.Second interlayer conductor is connected to two ends
The another one of son.Second potential barrier lining is arranged on the side wall of the second interlayer conductor.Second interlayer conductor
Physically separated by the second potential barrier lining with dielectric layer.Memory element is arranged on the first interlayer
On conductor.Top electrode layer is arranged on barrier layer and memory element.Top electrode layer covers memory element.
According to some embodiments, the manufacture method comprises the following steps.One preliminary structure is provided.This is first
Step structure includes a dielectric layer of an access device and overlap access device, and wherein access device has two
Individual terminal.Form a barrier layer on the dielectric layer.Two holes are formed by barrier layer and dielectric layer.
Two holes expose a part for two terminals respectively.One first potential barrier lining and one second is formed respectively
Potential barrier lining is on the side wall of two holes.Form one first interlayer conductor respectively and one second interlayer is led
Body is in two holes.First interlayer conductor is connected to the one of which of two terminals, and the first interlayer is led
Body and dielectric layer are physically separated by the first potential barrier lining.Second interlayer conductor is connected to two
The another one of individual terminal, the second interlayer conductor and dielectric layer are physically separated by the second potential barrier lining
Come.Then, a memory element is formed on the first interlayer conductor.A top electrode layer is formed in potential barrier
On layer and memory element, the top electrode layer covers memory element.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below：
Description of the drawings
Fig. 1 illustrates the semiconductor structure according to embodiment.
Fig. 2A～Fig. 2 J illustrates the manufacture method of the semiconductor structure according to embodiment.
【Symbol description】
102：Substrate
104：Access device
106：Source/drain regions
108：Source/drain regions
110：Gate electrode
112：Gate dielectric
114：Upper strata
116：Lower floor
118：Drift region is lightly doped
120：Drift region is lightly doped
122：Dielectric layer
124：Barrier layer
126：First interlayer conductor
128：First potential barrier lining
130：Second interlayer conductor
132：Second potential barrier lining
134：Conductor between third layer
136：3rd potential barrier lining
138：Memory element
140：Top electrode layer
142：Metal level
200：Preliminary structure
202：Substrate
204：Transistor
206：Source/drain regions
208：Source/drain regions
210：Gate electrode
212：Trap
214：Gate dielectric
216：Upper strata
218：Lower floor
220：Sept
222：Drift region is lightly doped
224：Drift region is lightly doped
226：Dielectric layer
228：Non-boundary contact layer
230：Barrier layer
232：Hard mask layer
234：Hole
236：First potential barrier lining
238：Second potential barrier lining
240：3rd potential barrier lining
242：First interlayer conductor
244：Second interlayer conductor
246：Conductor between third layer
248：Memory element
250：Memory element
252：Top electrode layer
254：Top electrode layer
256：Metal level
A：Array area
P：Zhou Bianqu
Specific embodiment
Hereinafter with reference to schema, a kind of semiconductor structure and its manufacture method are described.On describing
Convenient, this specification is to be absorbed in the semiconductor structure including RRAM device.However, the present invention
It is not limited to this.For example, barrier structure discussed below can be used in other structures.Will
It is noted that being clearly understood to provide, in institute's accompanying drawings, the size of element may be not anti-
Reflect its actual size.
Fig. 1 illustrates the semiconductor structure according to embodiment.The semiconductor structure includes an access device
104.Access device 104 has two terminals (106 and 108).For RRAM device, deposit
Take device and could typically be transistor or diode.In FIG, access device 104 is depicted as one
Transistor (a such as NMOS), which includes two source/drain regions, 106,108 and one gate electrode
110.More specifically, semiconductor structure may include a substrate 102, source/drain regions 106,108
It is arranged in substrate 102, and two i.e. described terminals of source/drain regions 106,108.Grid electricity
Pole 110 is arranged on substrate 102, between source/drain regions 106,108, and gate electrode
110 and substrate 102 separated by a gate dielectric 112 of transistor.According to an embodiment,
As shown in figure 1, gate electrode 110 may include a upper strata 114 and a lower floor 116, upper strata 114 is wrapped
Include metal silicide, such as CoSixOr WSix, lower floor 116 includes polysilicon.Transistor can also be wrapped
Include two and drift region 118,120 is lightly doped.
Semiconductor structure also includes a dielectric layer 122.122 overlap access device 104 of dielectric layer.Lift
For example, dielectric layer 122 is arranged on substrate 102 and access device 104, and overlap access device
104.Here, dielectric layer 122 can be used as an interlayer dielectric layer.
Semiconductor structure also includes a barrier layer 124.Barrier layer 124 is arranged on dielectric layer 122.
Barrier layer 124 may include the material with hydrogen blocking effect, such as silicon nitride (SiNx).
Semiconductor structure also includes one first interlayer conductor 126, one first potential barrier lining 128,1
Two interlayer conductors 130 and one second potential barrier lining 132.First interlayer conductor 126 extends through potential barrier
Layer 124 and dielectric layer 122.First interlayer conductor 126 is connected to the one of which (106) of two terminals.
First potential barrier lining 128 is arranged on the side wall of the first interlayer conductor 126, wherein the first interlayer conductor
126 and dielectric layer 122 physically separated by the first potential barrier lining 128.Second interlayer is led
Body 130 extends through barrier layer 124 and dielectric layer 122.Second interlayer conductor 130 is connected to two
The another one (108) of terminal.Second potential barrier lining 132 is arranged on the side wall of the second interlayer conductor 130,
Wherein the second interlayer conductor 130 and dielectric layer 122 are physically separated by the second potential barrier lining 132
Come.It is that semiconductor structure may also include a third layer in the example of transistor in access device 104
Between conductor 134 and one the 3rd potential barrier lining 136.Between third layer, conductor 134 extends through barrier layer 124
With dielectric layer 122.Between third layer, conductor 134 is connected to gate electrode 110.3rd potential barrier lining 136
It is arranged on the side wall of conductor 134 between third layer, conductor 134 and dielectric layer 122 wherein between third layer
Physically separated by the 3rd potential barrier lining 136.Here, when description one element " connection
To " another element when, the element " electrically on be connected to, be optionally also physically connected to "
Another element.Conductor 134 between the first interlayer conductor 126, the second interlayer conductor 130 and third layer
May include tungsten (W).First potential barrier lining 128, the second potential barrier lining 132 and the 3rd potential barrier lining 136
May include the material with hydrogen blocking effect, such as silicon nitride (SiNx).
Semiconductor structure also includes a memory element 138 and a top electrode layer 140.Memory element 138
It is arranged on the first interlayer conductor 126.Top electrode layer 140 is arranged on barrier layer 124 and memory element
On 138, and top electrode layer 140 covers memory element 138.In order to apply for RRAM, storage
Element 138 with programmable resistance (programmable resistance), and can be used in being formed and deposit
The material of storage element 138 includes tungsten oxide, nickel oxide, aluminum oxide, magnesia, cobalt oxide, oxidation
Titanium, titanium oxide nickel, zirconium oxide and cupric oxide etc..Memory element 138 particularly may include tungsten oxide,
Such as WO3、W2O5、WO2Or the WO with oxygen gradientx.Consequently, it is possible to semiconductor structure is
Including a RRAM device, the RRAM device includes memory element 138, and top electrode layer 140
Top electrode and the hearth electrode of memory element 138 are provided respectively with the first interlayer conductor 126.By first
Interlayer conductor 126 and the connection of the one of terminal of access device 104 (106), memory element 138 can
It is controlled by access device 104.In certain embodiments, memory element 138 is connected to the leakage of transistor
Polar region.Top electrode layer 140 may include a conductive material, to provide top electrode.Additionally, top electrode layer
140 may include the material with hydrogen blocking effect.According to some embodiments, top electrode layer 140 can be wrapped
Include titanium (Ti), titanium nitride (TiN) or TiAlN (TiAlN).According to an embodiment, memory element 138
Can have aboutExtremelyThickness, for exampleFor example, barrier layer 124 can
For aboutExtremelyTypically aboutExtremelyMemory element 138 can be about
ExtremelyTypically aboutTop electrode layer 140 can be aboutExtremelyTypical case
Be for aboutExtremely
Semiconductor structure may also include a metal level 142, be arranged on dielectric layer 122.Metal level 142
It is connected to conductor 134 between top electrode layer 140, the second interlayer conductor 130 and third layer.
Semiconductor structure may include an array area A and one week border area P.Said elements are typically positioned at
In the A of array area.However, in general, in addition to memory element 138 and top electrode layer 140,
Other elements can also similar fashion be arranged in Zhou Bianqu P.
According to embodiment, the first potential barrier lining 128, the second potential barrier lining 132, the 3rd potential barrier lining
136th, barrier layer 124 and top electrode layer 140 can be configured to the obstacle of hydrogen.More specifically,
One potential barrier lining 128, the second potential barrier lining 132 and the 3rd potential barrier lining 136 are avoided respectively from dielectric
The hydrogen of conductor 134 between 122 to the first interlayer conductor 126 of layer, the second interlayer conductor 130 and third layer
Diffusion.Barrier layer 124 and top electrode layer 140 are avoided from processing atmosphere or other elements to memory element
138 hydrogen diffusion.Thus, you can with avoid semiconductor structure (being particularly its memory element) because
The deterioration that hydrogen spreads and causes.
Next it will be described for the manufacture method of the semiconductor structure according to embodiment.Refer to Fig. 2A,
One preliminary structure 200 is provided.Preliminary structure 200 includes the one of an access device and overlap access device
Dielectric layer 226 (a such as interlayer dielectric layer).
In certain embodiments, as shown in Figure 2 A, access device can be a transistor 204, for example
One NMOS.Transistor 204 includes two source/drain regions, 206,208 and one gate electrode 210
Wherein two source/drain regions 206,208 are two described terminals.According to some embodiments,
Semiconductor structure may include a substrate 202, and source/drain regions 206,208 are formed in substrate 202.
More specifically, source/drain regions 206,208 may be formed at the trap 212 being arranged in substrate 202
In.Gate electrode 210 is formed on a substrate 202, between source/drain regions 206,208,
And gate electrode 210 and substrate 202 are separated by a gate dielectric 214 of transistor 204.
According to an embodiment, as shown in Figure 2 A, gate electrode 210 may include a upper strata 216 and a lower floor
218, upper strata 216 includes metal silicide, such as CoSixOr WSix, lower floor 218 includes polycrystalline
Silicon.Transistor may also include sept 220, be formed on the side wall of gate electrode 210.Transistor
May also include two and drift region 222,224 is lightly doped, respectively adjacent to source/drain regions 206,208.
It should be noted that preliminary structure 200 may include multiple transistors 204, some of them are formed in
In the array area A of preliminary structure 200, and others are then formed in the Zhou Bianqu P of preliminary structure 200.
Below step, unless there are particularly pointing out, otherwise can be in both array area A and Zhou Bianqu P all
Carry out it.
According to some embodiments, as shown in Figure 2 B, optionally enter under the atmosphere for including hydrogen
One technique of row.The technique can be a N2-H2 alloy formation process.Which can be used to form dielectric layer
Before 226, the non-boundary contact layer (borderless being conformally located on transistor 204 is formed
contact layer)228.Such process advan allows model in obtaining larger technique on contact etch
Enclose (process window).
Referring now to Fig. 2 C, after preliminary structure 200 is provided, forms a barrier layer 230 and exist
On dielectric layer 226.According to some embodiments, barrier layer 230 substantially covers Jie in the A of array area
Electric layer 226 is overall, and it is overall optionally to cover the dielectric layer 226 in Zhou Bianqu P.Barrier layer 230
May include the material with hydrogen blocking effect, such as but not limited to silicon nitride (SiNx).For example,
Barrier layer 230 can be under low pressure by SiNxFormed in the temperature higher than 400 DEG C, the temperature is e.g. about
600 DEG C to 700 DEG C.By such high temperature formation process, using the teaching of the invention it is possible to provide the low barrier layer of hydrogen content
230.According to an embodiment, barrier layer 124 can be aboutExtremelyTypically about
ExtremelyIn certain embodiments, as shown in Figure 2 C, it is possible to provide a hard mask layer 232 is in gesture
In barrier layer 230.Hard mask layer 232 can be made up of oxide.
Fig. 2 D is refer to, and multiple holes 234 is formed by hard mask layer 232, barrier layer 230 and is situated between
Electric layer 226.Its each expose source/drain regions 206 a part (that is, part of a terminal),
One of the part (that is, part of another terminal) or gate electrode 210 of source/drain regions 208
Point (this be using in the case of transistor 204).
Fig. 2 E is refer to, and multiple potential barrier linings is formed respectively on the side wall of those holes 234.Should
A little potential barrier linings include one first potential barrier lining 236 and one second potential barrier lining 238.First potential barrier is served as a contrast
On the side wall of the hole 234 that layer 236 is formed in some for exposing source/drain regions 206.Second gesture
Build on the side wall of the hole 234 that lining 238 is formed in some for exposing source/drain regions 208.?
In example using transistor 204, those potential barrier linings also include one the 3rd potential barrier lining 240.The
Three potential barrier linings 240 are formed on the side wall of the hole 234 of some for exposing gate electrode 210.
Potential barrier lining may include the material with hydrogen blocking effect, such as but not limited to silicon nitride (SiNx).Gesture
Build lining to be formed by deposition and etch process.Each potential barrier lining can have aboutExtremely
Thickness, typically about
Fig. 2 F is refer to, and a conductive material is filled to hole 234, to form multiple interlayer conductors.
Those interlayer conductors include one first interlayer conductor 242 and one second interlayer conductor 244.First interlayer
Conductor 242 is connected to source/drain regions 206 (that is, one of which of two terminals), and the first interlayer
Conductor 242 and dielectric layer 226 are physically separated by the first potential barrier lining 236.The second layer
Between conductor 244 be connected to source/drain regions 208 (that is, another one of two terminals), and the second interlayer
Conductor 244 and dielectric layer 226 are physically separated by the second potential barrier lining 238.Using
In the example of transistor 204, those interlayer conductors also include conductor 246 between a third layer.Third layer
Between conductor 246 be connected to gate electrode 210, and conductor 246 and dielectric layer 226 pass through between third layer
3rd potential barrier lining 240 is physically separated.Conductive material may include tungsten (W).Conductive material
May also include titanium (Ti) and titanium nitride (TiN).The step may include depositing and subsequent for conductive material
Cmp (CMP) technique.Additionally, hard mask layer 232 also can be removed by the CMP.
Then, a memory element 248 will be formed on the first interlayer conductor 242, and one will be formed and push up
On barrier layer 230 and memory element 248, wherein top electrode layer 254 covers storage to electrode layer 254
Element 248.
Fig. 2 G is refer to, and multiple memory elements is formed respectively on interlayer conductor.Those memory elements
Including the memory element 248 being formed on the first interlayer conductor 242 in the A of array area.Those storages
Element also includes that the interlayer on other interlayer conductors being formed in the A of array area or in Zhou Bianqu P is led
Other memory elements 250 on body.Memory element can be by aoxidizing the top section of interlayer conductor come shape
Become.For example, memory element can be formed by tungsten oxide, its be by aoxidize interlayer conductor tungsten come
Formed.Oxidation technology can be rapid thermal oxidation (RTO), plasma oxidation or PRP (plasma
- RTO- plasma) technique etc..According to an embodiment, memory element can be about 10 to
E.g., from about
Fig. 2 H is refer to, is formed 230 entirety of the covering of a top electrode layer 252 barrier layer and deposits with all of
Storage element 248,250.In certain embodiments, top electrode layer 252 can be conformally formed.Top electrode
Layer 252 may include the material with hydrogen blocking effect, such as but not limited to titanium nitride (TiN) or titanium nitride
Aluminium (TiAlN).For example, top electrode layer 252 can be by physical vapour deposition (PVD) (PVD) by TiN shape
Become.According to an embodiment, top electrode layer 252 can be aboutExtremelyTypically about Extremely
Fig. 2 I is refer to, most top electrode layer 252 is removed, leave behind and be formed in memory element 248
On part (that is, top electrode layer 254).Top electrode layer 254 covers memory element 248.In addition and move
Except all memory elements 250 for exposing.The step for example can be carried out by etch process.Afterwards,
Plasma cleaning technique is optionally carried out, with the metal for providing with formed in the step under connecing
More preferably interface between layer 256.
Consequently, it is possible to the RRAM device including memory element 248 is provided, and top electrode layer
254 and first interlayer conductor 242 top electrode and the hearth electrode of memory element 248 are provided respectively.Pass through
With the connection of source/drain regions 206, memory element 248 can be controlled by transistor 204.In some realities
Apply in example, source/drain regions 206 are the drain regions of transistor 204.
Fig. 2 J is refer to, and a metal level 256 is formed on dielectric layer 226.Metal level 256 is connected to
Conductor 246 between top electrode layer 254, the second interlayer conductor 244 and third layer.Metal level 256 can lead to
Cross and be deposited and patterned technique and formed.For example, metal level 256 can be formed by PVD
Ti/TiN/Al/Ti/TiN five-layer structure.
Above-mentioned step is compatible in typical CMOS technology.After metal level 256 is formed, can
Carry out traditional back segment (BEOL) technique.
Sum it up, according to embodiments described herein, providing the gesture of a barrier structure, particularly hydrogen
Build structure.Potential barrier lining is avoided from dielectric layer to the diffusion of the hydrogen of interlayer conductor.Barrier layer and top electrode layer
Sealed storage element, and therefore avoid spreading from the hydrogen of processing atmosphere or other elements to memory element.
Barrier layer particularly avoids the hydrogen from the element (such as dielectric layer) for being arranged on lower from spreading.Additionally,
Metal level can also provide the barrier functionality of hydrogen.Thus, you can to avoid semiconductor structure from expanding because of hydrogen
The deterioration for dissipating and causing.The deterioration that can particularly avoid memory element from causing because hydrogen spreads.
In sum, although the present invention is disclosed above with preferred embodiment, so which is not limited to
The present invention.Persond having ordinary knowledge in the technical field of the present invention, in the spirit without departing from the present invention
In scope, when can be used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on enclosing
Being defined of being defined of right.
Claims (10)
1. a kind of semiconductor structure, including：
One access device, with two terminals；
One dielectric layer, covers the access device；
One barrier layer, is arranged on the dielectric layer；
One first interlayer conductor, extends through the barrier layer and the dielectric layer, and the first interlayer conductor connects
It is connected to the one of which of two terminals；
One first potential barrier lining, is arranged on the side wall of the first interlayer conductor, wherein first interlayer
Conductor and the dielectric layer are physically separated by the first potential barrier lining；
One second interlayer conductor, extends through the barrier layer and the dielectric layer, and the second interlayer conductor connects
It is connected to the another one of two terminals；
One second potential barrier lining, is arranged on the side wall of the second interlayer conductor, wherein second interlayer
Conductor and the dielectric layer are physically separated by the second potential barrier lining；
One memory element, is arranged on the first interlayer conductor；And
One top electrode layer, is arranged on the barrier layer and the memory element, and the top electrode layer covers this and deposits
Storage element.
2. semiconductor structure according to claim 1, wherein the first potential barrier lining, this
Two potential barrier linings, the barrier layer and the top electrode layer are configured to the obstacle of hydrogen.
3. semiconductor structure according to claim 1, the wherein barrier layer include silicon nitride,
The first potential barrier lining and the second potential barrier lining include silicon nitride, and the top electrode layer includes titanium, nitridation
Titanium or TiAlN.
4. semiconductor structure according to claim 1, the wherein memory element have programmable
Resistance.
5. semiconductor structure according to claim 1, the wherein access device are a transistor,
The transistor includes two source/drain regions and a gate electrode, two source/drain regions for this two
Individual terminal.
6. semiconductor structure according to claim 5, further includes：
Conductor between one third layer, extends through the barrier layer and the dielectric layer, and between the third layer, conductor connects
It is connected to the gate electrode；And
One the 3rd potential barrier lining, is arranged on the side wall of conductor between the third layer, wherein between the third layer
Conductor and the dielectric layer are physically separated by the 3rd potential barrier lining.
7. semiconductor structure according to claim 6, further includes：
One metal level, is arranged on the dielectric layer, the metal level be connected to the top electrode layer, this second
Conductor between interlayer conductor and the third layer.
8. semiconductor structure according to claim 1, including a RRAM device, the RRAM
Device includes the memory element.
9. a kind of manufacture method of semiconductor structure, including：
A preliminary structure is provided, the preliminary structure includes an access device and covers the one of the access device
Dielectric layer, the wherein access device have two terminals；
A barrier layer is formed on the dielectric layer；
Two holes are formed by the barrier layer and the dielectric layer, two holes expose this two respectively
A part for terminal；
One first potential barrier lining and one second potential barrier lining are formed respectively on the side wall of two holes；
One first interlayer conductor and one second interlayer conductor are formed respectively in two holes, this first
Interlayer conductor is connected to the one of which of two terminals, and the first interlayer conductor and the dielectric layer pass through
The first potential barrier lining is physically separated, and the second interlayer conductor is connected to two terminals
Another one, the second interlayer conductor and the dielectric layer are physically separated by the second potential barrier lining
Come；
A memory element is formed on the first interlayer conductor；And
A top electrode layer is formed on the barrier layer and the memory element, the top electrode layer covers the storage
Element.
10. the manufacture method of semiconductor structure according to claim 9, further includes：
Before the step of forming the barrier layer, under the atmosphere for including hydrogen, carry out a technique.
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| CN109904187B (en) * | 2017-12-08 | 2021-08-13 | 旺宏电子股份有限公司 | Tungsten oxide resistance type random access memory with barrier-free structure |
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