CN103094245A - Integrated circuit device and method for establishing electrical conductor in integrated circuit device - Google Patents
Integrated circuit device and method for establishing electrical conductor in integrated circuit device Download PDFInfo
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- CN103094245A CN103094245A CN2011103393634A CN201110339363A CN103094245A CN 103094245 A CN103094245 A CN 103094245A CN 2011103393634 A CN2011103393634 A CN 2011103393634A CN 201110339363 A CN201110339363 A CN 201110339363A CN 103094245 A CN103094245 A CN 103094245A
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Abstract
The invention discloses an integrated circuit device and a method for establishing an electrical conductor in the integrated circuit device. The integrated circuit device comprises a lamination layer composed of a plurality of contact layers, a dielectric liner which surrounds an electric conductor and a conducting layer pit portion, wherein the each contact layer comprises a conducting layer and an insulating layer, the dielectric liner is located in an opening, through parts of the lamination layer, of the lamination layer, the electric conductor is insulated with the conducting layer of each contact layer in an electrical property mode, and the conducting layer pit portion is located at the opening is a pit portion of the conducting layer relative to adjacent insulating layers. The dielectric liner can be provided with an extension portion which partly extends between the adjacent insulating layers.
Description
Technical field
The invention relates to a kind of high density integrated circuit device, and particularly reach relevant for a kind of multi-level 3-D stacks formula integrated circuit (IC) apparatus the method for setting up electric conductor in this integrated circuit (IC) apparatus.
Background technology
In the manufacturing of high density memory devices, the data volume of its per unit area of integrated circuit is a key factor.So when the threshold size of storage arrangement had been approached the restriction that the etching skill states, the multilayer laminated technology of memory cell was suggested, to reach larger storage density and lower position cost.
Along with the size decline of different elements in all multi-level 3-D stacks formula devices, due to the thickness reduction of each insulating barrier, the problem relevant with breakdown voltage and current leakage begins to occur.For these problems, for example, can increase and be positioned at an interconnect area being electrically insulated around the thickness of embolism or other electric conductor by different contact layer.Yet such way can reduce the sectional area of embolism, thereby causes its resistance to rise.Or can keep the sectional area of embolism, but can increase the distance between embolism, and therefore reduce device density.Similarly problem also appears at and is positioned at this interconnect area also by embolism or other interlayer embolism between the ground plane of part or total contact layer.By minimizing the sectional area of interlayer embolism, can reach effective space utilization, but must make the sacrifice of the conductive layer Contact area of embolism and each contact layer between limiting layer.And the sectional area that increases the interlayer embolism can cause the reduction of device density.
Summary of the invention
The invention relates to that a kind of multi-level 3-D stacks formula integrated circuit (IC) apparatus reaches the method for setting up electric conductor in this integrated circuit (IC) apparatus.
One embodiment is relevant a kind of integrated circuit (IC) apparatus, comprising: a lamination that is consisted of by a plurality of contact layer, and each contact layer includes a conductive layer and an insulating barrier; Around a dielectric medium lining of an electric conductor, be arranged in an opening that passes through the part lamination of this lamination, and electric conductor sees through, and dielectric medium serves as a contrast and the conductive layer of each contact layer is electrically insulated; And the conductive layer depressed part, be the part that this conductive layer seems and caves in respect to its adjacent insulating barrier.In some embodiment, also comprise an electrical insulation layer that is positioned on this lamination; And the electric conductor epitaxy part by electrical insulation layer, this electric conductor epitaxy part and with the electric conductor electrical contact.In certain embodiments, the dielectric medium lining comprises an epitaxy part, and this dielectric medium lining epitaxy part extends between adjacent insulating barrier.In certain embodiments, this epitaxy part is generally annular.
Another embodiment is relevant a kind of 3-D stacks formula integrated circuit (IC) apparatus, comprising: a lamination that is consisted of by the first contact layer, the second contact layer, the 3rd contact layer and the 4th contact layer at least, and wherein each contact layer includes a conductive layer and an insulating barrier; The first electric conductor, the second electric conductor, the 3rd electric conductor and the 4th electric conductor are arranged in the contact openings by this lamination of part, and this first, second, third and the 4th electric conductor extends respectively and has electrical contact to the first, second, third and the 4th contact layer; One dielectric medium lining, around second, third and the 4th electric conductor, so that the second electric conductor and the first contact layer electrical isolation, the 3rd electric conductor and first, second contact layer electrical isolation, the 4th electric conductor and first, second and third contact layer electrical isolation; And the conductive layer depressed part, be conductive layer in adjacency contact openings place with respect to the seem part of depression of its adjacent insulating barrier.Part dielectric medium lining extends between aforesaid adjacent insulating barrier, and the dielectric medium that is electrically insulated with foundation serves as a contrast epitaxy part, and being electrically insulated between the opposed conductive layer of reinforcement and electric conductor is provided.
Another embodiment is relevant a kind of method of setting up electric conductor in an integrated circuit (IC) apparatus, and this integrated circuit (IC) apparatus comprises a lamination that is made of a plurality of contact layer, and wherein each contact layer includes a conductive layer and an insulating barrier.The method comprises: form the contact openings by this lamination of part, set up thus a conductive layer edge that exposes and insulating barrier edge; Set up a depressed part of conductive layer in the conductive layer edge that exposes, to set up the conductive layer edge of a depression; Form a dielectric medium lining in contact openings, cover by this conductive layer edge of this a plurality of insulating barriers edge and this depression, and the material that is electrically insulated that forms the dielectric medium lining deposits in this depressed part, the dielectric medium lining is set up a lining contact openings; Use an electric conducting material, set up an electric conductor in this lining contact openings, the material that is electrically insulated in depressed part makes the conductive layer edge electric sexual isolation of this electric conductor and this depression, provides thus the reinforcement electric conductor to reach around being electrically insulated between the conductive layer of this electric conductor; And be electrically connected electric conductor and under conductive layer.In certain embodiments, form the dielectric medium lining comprise being electrically insulated material at least essence fill this depressed part.Before some embodiment more is included in the formation of dielectric medium lining, the conductive layer edge that oxidation should be caved in.
An embodiment is relevant a kind of method of setting up electric conductor in a 3-D stacks formula integrated circuit (IC) apparatus again, this 3-D stacks formula integrated circuit (IC) apparatus comprises a lamination that is made of the first contact layer, the second contact layer, the 3rd contact layer and the 4th contact layer at least, and wherein each contact layer includes a conductive layer and an insulating barrier.the method comprises: form the contact openings by this lamination of part, set up thus the conductive layer edge that exposes and insulating barrier edge, in between two adjacent insulating barriers of these a plurality of contact openings, set up the depressed part of conductive layer at the conductive layer edge of these a plurality of exposures, to set up the conductive layer edge of depression, form the dielectric medium lining in these a plurality of contact openings, these a plurality of dielectric medium linings cover the conductive layer edge of this a plurality of insulating barriers edge and these a plurality of depressions, and the material that is electrically insulated that forms the dielectric medium lining deposits in these a plurality of depressed parts, dielectric medium lining definition lining contact openings, use an electric conducting material, set up the first electric conductor in these a plurality of lining contact openings, the second electric conductor, the 3rd electric conductor and the 4th electric conductor, the material that is electrically insulated in these a plurality of depressed parts makes the conductive layer electrical isolation of the second electric conductor and the first contact layer, make the conductive layer electrical isolation of the 3rd electric conductor and first and second contact layer, and make the 4th electric conductor and first, the conductive layer electrical isolation of second and third contact layer, provide by this these a plurality of electric conductors of reinforcement to reach around being electrically insulated between the conductive layer of these a plurality of electric conductors, first, second, the the 3rd and the 4th electric conductor extends respectively and is electrically connected to first, second, the conductive layer of the 3rd and the 4th contact layer.
For there is better understanding above-mentioned and other aspect of the present invention, embodiment cited below particularly, and coordinate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is the profile of an example of a 3-D stacks formula integrated circuit (IC) apparatus, and this 3-D stacks formula integrated circuit (IC) apparatus is to describe according to the present invention, and comprises a lamination in an interconnect area.
Fig. 2 is the diagrammatic sectional view of the interconnect area of a 3-D stacks formula integrated circuit (IC) apparatus, describes a lamination that is made of mutual conductive layer and insulating barrier.
Fig. 3 illustrates the deposition of carrying out clearance layer for the structure of Fig. 2.
Fig. 4 illustrates the structure for Fig. 3, sets up one first photoresist mask with mask open, and passes through the first conductive layer in these a plurality of opening part etchings.
Fig. 5 illustrates the structure for Fig. 4, sets up one second photoresist mask with mask open, and passes through two conductive layers in these a plurality of opening part etchings.
Fig. 6 describes the second photoresist mask in Fig. 5 structure is removed.
Fig. 7 illustrates for different contact layer it and is exposed to outer conductive layer and carries out the sidewall etching, sets up depressed part between two insulating barriers of up and down.
Fig. 8 illustrates and removes interlayer embolism open bottom and this clearance layer that is electrically insulated of the first embolism open bottom, and second, third and the 4th embolism opening part cover the insulating layer material of second, third and the 4th conductive layer.
Fig. 9 illustrates the structure for Fig. 8, makes nonconducting clearance layer deposition of material fill these a plurality of depressed parts and is these a plurality of embolism opening linings.
The clearance layer material that Figure 10 illustrates each embolism open bottom in Fig. 9 structure removes.
Figure 11 illustrates the structure for Figure 10, sets up the 3rd photoresist mask and carries out etching.
Figure 12 illustrates the structure for Figure 11, and between etch layer, the embolism opening part is exposed to outer insulating barrier, so that it sets up depressed part between two conductive layers up and down in these a plurality of insulating barriers, and removes subsequently the 3rd photoresist mask.
Figure 13 illustrates the structure for Figure 12, electric conducting material is filled in interlayer embolism opening and embolism opening, with the first, second, third and the 4th embolism of setting up an interlayer embolism and laying respectively at the first, second, third and the 4th embolism opening, wherein this interlayer embolism and each conductive layer electrical contact, this first, second, third and the 4th embolism is electrically connected respectively and causes the first, second, third and the 4th conductive layer.
Figure 14 to Figure 17 describe 3-D stacks formula integrated circuit (IC) apparatus the second embodiment structure with and preparation method thereof.
Figure 14 illustrates and is similar to a structure shown in Figure 9, but is not etching mode as shown in Figure 8, and the embolism opening is the insulating barrier that etching is passed through covering second, third and the 4th conductive layer of part, deposits subsequently nonconducting clearance layer material.
Figure 15 illustrates the structure for Figure 14, and etching is by part this second, third and the 4th conductive layer.
Figure 16 illustrates the structure for Figure 15, deposits one the 3rd photoresist mask in the mode that is similar to Figure 11.
Figure 17 illustrates the structure for Figure 16, and between etch layer, the embolism opening part is exposed to outer insulating barrier, to set up depressed part between lower thereon two conductive layers.
Figure 18 to Figure 20 describe 3-D stacks formula integrated circuit (IC) apparatus the 3rd embodiment structure with and preparation method thereof.
Figure 18 illustrates the structure that is similar to structure shown in Figure 7, but the concave edges of this first, second and third conductive layer of oxidation.
Figure 19 illustrates the structure for Figure 18, in the bottom etching of second, third and the 4th embolism opening by first, second and third insulating barrier, to expose second, third and the 4th conductive layer.
Figure 20 illustrates the structure for Figure 19, is electrically insulated clearance layer as embolism opening lining take one, this clearance layer and fill the conductive layer depressed part that is positioned between two insulating barriers of up and down of being electrically insulated.
[main element symbol description]
10: 3-D stacks formula integrated circuit (IC) apparatus
11: lamination
17: interconnect area
18.1,18.2,18.3,18.4: contact layer
19: substrate
25: dielectric layer
29: oxide layer
30: oxide layer
32: clearance layer
34.1,34.2,34.3,34.4: conductive layer
36.1,36.2,36.3,36.4: insulating barrier
37: annular recess
39: annular recess
42: the first photoresist masks
43: mask open
44: interlayer embolism opening
46,46.1,46.2,46.3,46.4: the embolism opening
48: the second photoresist masks
49: mask open
50: annular section
51.1,51.2,51.3,51.4: the embolism epitaxy part
52: interlayer dielectric
54.1,54.2,54.3,54.4: embolism
55: the interlayer embolism
56: interlayer embolism epitaxy part
58: the bottom transverse size
60: the associated transverse size
61: the dielectric side walls wall
62: the clearance layer material
63: conductive layer surface
64: upper surface
65: surface of insulating layer
66: the three photoresist masks
67: mask open
70: hole
74: oxidized portion
Embodiment
Fig. 1 is a profile of describing 3-D stacks formula integrated circuit (IC) apparatus 10, and an interconnect area (interconnect region) 17 comprises a lamination (stack) 11 that is made of the first, second, third and the 4th contact layer (contact levels) 18 at least.One integrated circuit (IC) apparatus has usually far more than the contact layer of four layers.Each contact layer 18 all comprises a conductive layer 34 and an insulating barrier 36, be contained in this first, second, third and the 4th contact layer 18.1,18.2,18.3 and 18.4 conductive layer is respectively 34.1,34.2,34.3 and 34.4, and insulating barrier is respectively 36.1,36.2,36.3 and 36.4.For other following Various Components, also stipulate in a similar manner its designated reference symbol in graphic.
One interlayer embolism (interlevel plug) 55 extends through the lamination 11 of part, and is electrically connected to each conductive layer 34.This interlayer embolism 55 is also sometimes referred to as interlayer conductor (interlevel conductor), can be or can not be a ground connection embolism.The partial insulative layer 36 of embolism 55 between adjoining course is with respect to the conductive layer 34 that the is adjacent depression that seems, to form annular recess 37 as shown in figure 12.The annular section 50 of interlayer embolism 55 (this part be generally annular) extends to above-mentioned annular recess 37, with enter on it and under it 18 of contact layer and with these a plurality of contact layer 18 electrical contacts.This kenel provides the electrical contact of 34, embolism 55 and conductive layer between reinforced layer.
One dielectric layer 25 is positioned under lamination 11, and an oxide layer 29 is between dielectric layer 25 and a substrate 19.The material of dielectric layer 25 is generally silicon nitride (SiN), and the material of oxide layer 29 is generally silicon dioxide (SiO
2), and substrate 19 is generally silicon substrate.One oxide layer 30 and a clearance layer 32 are positioned on this lamination 11.The material of oxide layer 30 is generally silicon dioxide, and the material of clearance layer 32 is generally silicon nitride.Interlayer dielectric 52 is positioned on clearance layer 32, and its composition is generally oxide, for example silicon dioxide.Embolism epitaxy part (plug extension) 51.1-51.4 is to contact respectively embolism 54.1-54.4 by interlayer dielectric 52 and clearance layer 32.One interlayer embolism epitaxy part (interlevel plug extension) 56 by interlayer dielectric 52 and clearance layer 32 with embolism between contact layer 55.
Bottom transverse size 58 (being commonly called diameter 58) is the associated transverse size 60 (being commonly called diameter 60) less than the clearance layer material 62 (being illustrated in Fig. 9) that is deposited on annular recess 39 (being illustrated in Fig. 8).Due to when a contact is also unjustified, the clearance layer material 62 that is deposited on annular recess 39 can help to stop the contact hole etching, and therefore such size relationship is conducive to process window.
Fig. 2-Figure 13 be describe a 3-D stacks formula integrated circuit (IC) apparatus 10 the first embodiment structure with and preparation method thereof.Fig. 2 is the diagrammatic sectional view of the interconnect area 17 of a 3-D stacks formula integrated circuit (IC) apparatus 10, describes a lamination 11 that is made of mutual conductive layer 34 and insulating barrier 36.Each conductive layer 34 reaches an adjacent with it insulating barrier 36 and jointly sets up a contact layer 18.Oxide layer 30 is positioned on the superiors' conductive layer 34.1.Oxide layer 30 has an interlayer embolism opening 44 and a series of embolism opening 46, and typically uses a photoresist mask and coordinate lithographic technique to form this interlayer embolism opening 44 and embolism opening 46.Interlayer embolism opening 44 is arranged to hold a following interlayer embolism 55 and the embolism 54 of a series of tool conductivity with these a plurality of embolism openings 46.On practice, interconnect area 17 has the interlayer embolism 55 more than usually, and each conductive layer 18 in interconnect area 17 all has an embolism 54 at least.
Fig. 3 illustrates the structure for Fig. 2, waits the tropism to deposit the result of clearance layer 32.The material of this clearance layer 32 is generally silicon nitride.Fig. 4 is illustrated in the structure of Fig. 3 and sets up one first photoresist mask 42, and this first photoresist mask 42 is to have mask open 43 at the second embolism opening 46.2 and the 4th embolism opening 46.4 places.After the first photoresist mask 42 forms, the first conductive layer 34.1 be etched in the second and the 4th embolism opening 46.2 and 46.4 places by.
In Fig. 5, be to adjust the structure of Fig. 4 by the foundation of one second photoresist mask 48, the second photoresist mask 48 is to have mask open 49 at the 3rd embolism opening 46.3 and the 4th embolism opening 46.4 places.In the 3rd and the 4th embolism opening 46.3 and 46.4 places, all there is two conductive layers 34 to be etched.Particularly be etched for first and second conductive layer 34.1 and 34.2 at the 3rd embolism opening 46.3 places, and be etched for second and third conductive layer 34.2 and 34.3 at the 4th embolism opening 46.4 places.Fig. 6 describes result that the second photoresist mask 48 in Fig. 5 structure is removed.
Fig. 7 illustrates the result of carrying out the sidewall etching for second, third and the 4th embolism opening 46.2,46.3 and 46.4, is that it is exposed to outer conductive layer 34 and carries out etching for different contact layer 18.The sidewall etching is also sometimes referred to as multiple pulling back (poly pull back), forms annular recess 39 (be generally annular, be also sometimes referred to as depressed part) in 36 of up and down two insulating barriers.As described below, these a plurality of annular recess 39 will be by the Material Filling that is electrically insulated, with in embolism 54 and around the thicker insulating material of 34 formation of conductive layer of these a plurality of embolisms 54, these a plurality of embolisms 54 are to build in embolism opening 46.Please refer to Fig. 7, amount of recess is the be etched horizontal ranges of 65 of surface of insulating layer of the conductive layer surface 63 of recessed conductive layer 34 and insulating barrier 36 of embolism opening 46 places, this amount of recess more preferably greater than 10 nanometers to reach better insulation effect.
Fig. 8 illustrates and removes second, third and the 4th embolism opening 46.2,46.3 and 46.4 places and cover second, third and the 4th conductive layer 38.2,38.3 and 38.4 part first, second and third insulating barrier 36.1,36.2 and 36.3 result.Because the material of insulating barrier 36 is generally oxide, this one removes step and is also sometimes referred to as oxide and penetrates (oxide breaktlrough).
In Fig. 9, nonconducting clearance layer material 62 is deposited on the structure of Fig. 8 and fills these a plurality of annular recess 39, and these a plurality of clearance layer materials 62 are generally silicon nitride.Clearance layer material 62 is also that embolism opening 46 linings are to form dielectric side walls wall 61.
In structure shown in Figure 9, the clearance layer material 62 that is positioned at interlayer embolism opening 44 and each embolism opening 46 bottoms is removed in subsequent step, as shown in figure 10.Because the composition of clearance layer material 62 is generally silicon nitride, this one removes step and is also sometimes referred to as silicon nitride and penetrates.Remove outside conductive layer that step makes following part is exposed to: the 4th conductive layer 34.4 at the 3rd conductive layer 34.3 at second conductive layer 34.2 at first conductive layer 34.1 at interlayer embolism opening 44 and the first embolism opening 46.1 places, the second embolism opening 46.2 places, the 3rd embolism opening 46.3 places and the 4th embolism opening 46.4 places.
Figure 11 illustrates the result of one the 3rd photoresist mask 66 after the structure formation of Figure 10, and the 3rd photoresist mask 66 covers these a plurality of embolism openings 46 and provides a mask open 67 in interlayer embolism opening 44 places.After the 3rd photoresist mask 66 is shaped, namely in interlayer embolism opening 44 place's etchings by contact layer 18.1-18.3, until stop when contacting the 4th conductive layer 34.4.
Illustrate monoxide depressed part etch step in Figure 12, the oxide in this embodiment is insulating barrier 36.Figure 12 shows the structure for Figure 11, and between etch layer, embolism opening 44 places are exposed to first, second and third outer insulating barrier 36.1-36.3.This etching behavior provides interlayer embolism opening 44 annular recess 37 (be generally annular), and this annular recess 37 is thereon and the depressed part of 34 foundation of the conductive layer under it.Subsequently and remove the 3rd photoresist mask 66.
Figure 13 illustrates in Figure 12, after the electric conducting material that is generally polysilicon is filled in interlayer embolism opening 44, forms the structure of an interlayer embolism 55, and this interlayer embolism 55 is and each conductive layer 34.1-34.4 electrical contact.The existence of annular recess 37 makes interlayer embolism 55 have annular section 50, this annular section 50 extend on it and under it 34 of conductive layers and with these a plurality of conductive layer 34 electrical contacts.The electrical contact surface of 34 of interlayer embolism 55 and conductive layers is surperficial much larger than the electrical contact that only in embolism opening 44, this interlayer embolism of deposition can form between general cylindrical layer shown in Figure 11.Therefore the electrical contact that has 34 of the interlayer embolism 55 of annular section 50 and conductive layers is stronger.
Figure 13 also illustrates the shaping of embolism 54.1-54.4 in embolism opening 46.1-46.4.The first, second, third and the 4th embolism 54.1-54.4 is electrically connected to respectively the first, second, third and the 4th conductive layer 34.1-34.4.After deposits conductive material, namely carry out chemico-mechanical polishing to set up upper surface shown in Figure 13 64.Deposit again subsequently interlayer dielectric 52, and in the interior perforation of setting up embolism 55 and embolism 54.1-54.4 between aligned layer of interlayer dielectric 52.The interlayer embolism epitaxy part 56 of tool conductivity and embolism epitaxy part 51.1-51.4 form in perforation, to set up structure shown in Figure 1.
Figure 14 to Figure 17 describe a 3-D stacks formula integrated circuit (IC) apparatus 10 the second embodiment structure with and preparation method thereof.Figure 14 illustrates and is similar to a structure shown in Figure 9, but these a plurality of embolism opening 46.2-46.4 only etching by first, second and third insulating barrier 36.1-36.3 of part, but not as the aforementioned fully etching by insulating barrier 36.1-36.3 to form second, third and the 4th embolism opening 46.2-46.4 as shown in Figure 8.First, second and third insulating barrier 36.1-36.3 still covers second, third and the 4th conductive layer 34.2-34.4.To be similar to the mode of Fig. 9 relevant discussion, deposit the clearance layer material 62 that is electrically insulated subsequently, these a plurality of clearance layer materials 62 are generally silicon nitride.
The clearance layer material 62 of the interlayer embolism opening 44 in Figure 14 structure and each embolism opening 46 bottoms, be etched in Figure 15 by.Figure 15 also illustrates etching by the result of part this second, third and the 4th conductive layer 34.2-34.4.This etching step is also sometimes referred to as silicon nitride/oxide and penetrates.
Figure 16 illustrates the structure for Figure 15, deposits one the 3rd photoresist mask 66 in the mode that is similar to Figure 11.Figure 17 illustrates the structure for Figure 16, and between etch layer, embolism opening 44 places are exposed to outer insulating barrier 36.1-36.4.This etching step is the mode that is similar to Figure 12, forms annular recess 37 between two conductive layers of up and down.Figure 12 and two embodiment shown in Figure 17 all need monoxide depression step setting up annular recess 37, and oxide depression step is called again the oxide step of pulling back.Generally speaking, can use buffered hydrofluoric acid solution (BOE/HF) to reach this purpose.The difference of this two embodiment is: in Figure 17, pull back step when carrying out in oxide, the nontarget area is protected by the 3rd photoresist mask 66; And in the embodiment shown in fig. 12 and no third photoresist mask 66, oxide is pulled back step when carrying out, and is to be provided by silicon nitride gap layer 32 for the protection of nontarget area.Due in the embodiment of Figure 12 and Figure 17, provide by clearance layer 32 for the protection of sidewall; The difference of this two embodiment in protection should be not too many.Yet in Figure 16, the silicon nitride gap layer has some for 32 times and is exposed to outer oxide, and therefore compared to the embodiment of Figure 12, the embodiment of Figure 17 pulls back in oxide and has more protection when step is carried out.Remaining step of the second embodiment is the relevant discussion corresponding to Figure 12 and Figure 13.
Figure 18 to Figure 20 illustrate a 3-D stacks formula integrated circuit (IC) apparatus 10 the 3rd embodiment structure with and preparation method thereof.Figure 18 illustrates the structure that is similar to structure shown in Figure 7, but the depressed part of oxidation first, second and third polysilicon conducting layers 34.1-34.3, to set up oxidized portion 74.When conductive layer 34 consist of polysilicon the time, this oxidation step is also sometimes referred to as polysilicon oxidation (poly oxidation).Set up annular recess 39 and therefore the second embolism opening 46.2 and the first conductive layer 34.1 be electrically insulated, the 3rd embolism opening 46.3 is electrically insulated with first and second conductive layer 34.1 and 34.2, and the 4th embolism opening 46.4 and first, second and third conductive layer 34.1-34.3 are electrically insulated.
In Figure 19, the structure of Figure 18 in this second, third and the bottom etching of the 4th embolism opening 46.2-46.4 by first, second and third insulating barrier 36.1-36.3, to expose second, third and the 4th conductive layer 34.2-34.4.This step is also sometimes referred to as oxide and penetrates.
Figure 20 illustrates the structure for Figure 19, and take a dielectric side walls wall 61 that is electrically insulated as embolism opening 46 linings, this dielectric side walls wall 61 is also filled the annular recess 39 that embolism opening 46 places are positioned at 36 of up and down two insulating barriers.The composition of dielectric side walls wall 61 is generally silicon nitride.Remaining step of the 3rd embodiment is the relevant discussion corresponding to Figure 12 and Figure 13.
In certain embodiments, opening up owing to pulling back and fall forward learning (pullback topology), a plurality of holes 70 that may be in interlayer embolism 55 illustrate with dotted line in just like Fig. 1 are established.The existence of hole 70 can be used as the index that interlayer embolism 55 has been established, sets up this interlayer embolism 55 as the etching insulating barrier 36 that passes through of teachings of the present invention.
Any, and all patents of mentioning in above content, patent application and printed publication are that form with list of references invests this specification.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.
Claims (22)
1. integrated circuit (IC) apparatus comprises:
One lamination is made of a plurality of contact layer, and wherein each contact layer includes a conductive layer and an insulating barrier;
One dielectric medium lining is arranged in an opening of this lamination and around an electric conductor, this opening is by this lamination of part, and this electric conductor is to be electrically insulated by the conductive layer of this dielectric medium lining with each contact layer; And
One conductive layer depressed part is adjacent to this opening part, for this conductive layer with respect to its adjacent insulating barrier seem the depression part.
2. integrated circuit (IC) apparatus according to claim 1 more comprises:
One electrical insulation layer is positioned on this lamination; And
One electric conductor epitaxy part, be by this electrical insulation layer and with this electric conductor electrical contact.
3. integrated circuit (IC) apparatus according to claim 2, wherein:
This dielectric medium lining comprises an epitaxy part, and this epitaxy part of this dielectric medium lining is positioned between adjacent insulating barrier and around this electric conductor;
This electric conductor epitaxy part has one first lateral dimension in the part that contacts with this electric conductor; And
This epitaxy part of this dielectric medium lining has one second lateral dimension, and this second lateral dimension is greater than this first lateral dimension.
4. integrated circuit (IC) apparatus according to claim 1, wherein this dielectric medium lining comprises an epitaxy part, this epitaxy part of this dielectric medium lining is positioned between adjacent insulating barrier.
5. integrated circuit (IC) apparatus according to claim 4, wherein this epitaxy part of this dielectric medium lining be annular.
6. integrated circuit (IC) apparatus according to claim 1, wherein its depression with respect to the insulating barrier that is adjacent of this conductive layer depressed part is at least 10 nanometers.
7. 3-D stacks formula integrated circuit (IC) apparatus comprises:
One lamination is made of one first contact layer, one second contact layer, one the 3rd contact layer and four layers of contact layer of one the 4th contact layer at least, and wherein each contact layer includes a conductive layer and an insulating barrier;
One first electric conductor, one second electric conductor, one the 3rd electric conductor and one the 4th electric conductor, all be arranged in a contact openings, these a plurality of contact openings are by this lamination of part, and this first electric conductor, this second electric conductor, the 3rd electric conductor and the 4th electric conductor extend respectively and have electrical contact to this first contact layer, this second contact layer, the 3rd contact layer and the 4th contact layer;
One dielectric medium lining, around this second electric conductor, the 3rd electric conductor and the 4th electric conductor, so that this second electric conductor and this first contact layer are electrically insulated, the 3rd electric conductor and this first contact layer and this second contact layer are electrically insulated, the 4th electric conductor and this first contact layer, this second contact layer and the 3rd contact layer are electrically insulated; And
A plurality of conductive layer depressed parts, these a plurality of conductive layers that are adjacent to this a plurality of contact openings places are with respect to the seem part of depression of its adjacent insulating barrier, and this dielectric medium lining of part extends between aforesaid adjacent insulating barrier, the dielectric medium that is electrically insulated with foundation serves as a contrast epitaxy part, and being electrically insulated between the opposed conductive layer of reinforcement and electric conductor is provided.
8. 3-D stacks formula integrated circuit (IC) apparatus according to claim 7 more comprises:
One electrical insulation layer is positioned on this lamination; And
One first electric conductor epitaxy part, one second electric conductor epitaxy part, one the 3rd electric conductor epitaxy part and one the 4th electric conductor epitaxy part, be by this electrical insulation layer and with this first electric conductor, this second electric conductor, the 3rd electric conductor and the 4th electric conductor electrical contact.
9. 3-D stacks formula integrated circuit (IC) apparatus according to claim 8, wherein:
These a plurality of electric conductor epitaxy parts have the first lateral dimension in the part that contacts with these a plurality of electric conductors; And
This dielectric medium lining comprises epitaxy part, these a plurality of epitaxy parts of this dielectric medium lining are around these a plurality of electric conductors, these a plurality of epitaxy parts of this dielectric medium lining have the second lateral dimension, and these a plurality of second lateral dimensions are at least greater than this first lateral dimension of some electric conductor epitaxy part.
10. 3-D stacks formula integrated circuit (IC) apparatus according to claim 7, wherein this first electric conductor, this second electric conductor, the 3rd electric conductor and the 4th electric conductor directly contact with these a plurality of conductive layers that are contained in this first contact layer, this second contact layer, the 3rd contact layer and the 4th contact layer respectively.
11. 3-D stacks formula integrated circuit (IC) apparatus according to claim 7, wherein these a plurality of epitaxy parts of this dielectric medium lining are annular.
12. 3-D stacks formula integrated circuit (IC) apparatus according to claim 7, wherein its depression with respect to the insulating barrier that is adjacent of some conductive layer depressed part is at least 10 nanometers at least.
13. a method is used to an integrated circuit (IC) apparatus and sets up electric conductor, this integrated circuit (IC) apparatus comprises a lamination that is made of a plurality of contact layer, and wherein each contact layer includes a conductive layer and an insulating barrier, and the method comprises:
One contact openings forms step, is a contact openings that forms by this lamination of part, sets up thus a conductive layer edge that exposes and insulating barrier edge;
One depressed part establishment step is to set up a depressed part of conductive layer in the conductive layer edge of this exposure, to set up the conductive layer edge of a depression;
One dielectric medium lining forms step, to form a dielectric medium lining in this contact openings, this dielectric medium lining covers the conductive layer edge of this a plurality of insulating barriers edge and this depression, and the material that is electrically insulated that forms this dielectric medium lining deposits in this depressed part, and this dielectric medium lining is set up a lining contact openings;
One electric conductor establishment step, to use an electric conducting material, set up an electric conductor in this lining contact openings, this material that is electrically insulated in this depressed part makes the conductive layer edge electric sexual isolation of this electric conductor and this depression, provides thus this electric conductor of reinforcement to reach around being electrically insulated between this conductive layer of this electric conductor; And
One is electrically connected step, be electrically connected this electric conductor and under conductive layer.
14. method according to claim 13, wherein this dielectric medium lining forms step and comprises with this material that is electrically insulated and fill at least this depressed part.
15. method according to claim 14 more comprises:
Form an electrical insulation layer on this lamination;
Form an electric conductor epitaxy part, this electric conductor epitaxy part by this electrical insulation layer and with this electric conductor electrical contact, and have one first lateral dimension in the part that contacts with this electric conductor; And wherein:
The execution that this depressed part establishment step and this dielectric medium lining form step is to make this depressed part around this electric conductor, and makes this material that is electrically insulated that is filled in this depressed part have one second lateral dimension, and this second lateral dimension is greater than this first lateral dimension.
16. method according to claim 13, before more being included in this dielectric medium lining formation step, the conductive layer edge that oxidation should be caved in.
17. method according to claim 13, wherein this depressed part establishment step comprises that the depression that makes this depressed part with respect to the insulating barrier that is adjacent is at least 10 nanometers.
18. method, be used to a 3-D stacks formula integrated circuit (IC) apparatus and set up electric conductor, this 3-D stacks formula integrated circuit (IC) apparatus comprises a lamination that is made of one first contact layer, one second contact layer, one the 3rd contact layer and one the 4th contact layer at least, wherein each contact layer includes a conductive layer and an insulating barrier, and the method comprises:
One contact openings forms step, is the contact openings that forms by this lamination of part, sets up thus the conductive layer edge that exposes and insulating barrier edge;
One depressed part establishment step is between two adjacent insulating barriers of these a plurality of contact openings, sets up the depressed part of conductive layer at the conductive layer edge of these a plurality of exposures, to set up the conductive layer edge of depression;
One dielectric medium lining forms step, to form the dielectric medium lining in these a plurality of contact openings, these a plurality of dielectric medium linings cover the conductive layer edge of this a plurality of insulating barriers edge and these a plurality of depressions, and the material that is electrically insulated that forms these a plurality of dielectric medium linings deposits in these a plurality of depressed parts, these a plurality of dielectric medium lining definition lining contact openings;
one electric conductor establishment step, to use an electric conducting material, set up one first electric conductor in these a plurality of lining contact openings, one second electric conductor, one the 3rd electric conductor and one the 4th electric conductor, this material that is electrically insulated in these a plurality of depressed parts makes the conductive layer electrical isolation of this second electric conductor and this first contact layer, make these a plurality of conductive layer electrical isolation of the 3rd electric conductor and this first contact layer and this second contact layer, make the 4th electric conductor and this first contact layer, a plurality of conductive layer electrical isolation of this of this second contact layer and the 3rd contact layer, provide thus these a plurality of electric conductors of reinforcement to reach around being electrically insulated between these a plurality of conductive layers of these a plurality of electric conductors, this first electric conductor, this second electric conductor, the 3rd electric conductor and the 4th electric conductor extend respectively and are electrically connected to this first contact layer, this second contact layer, a plurality of conductive layers of this of the 3rd contact layer and the 4th contact layer.
19. method according to claim 18, wherein this dielectric medium lining forms step and comprises with this material that is electrically insulated and fill at least this a plurality of depressed parts.
20. method according to claim 18 more comprises:
Form an electrical insulation layer on this lamination;
Form the electric conductor epitaxy part, these a plurality of electric conductor epitaxy parts by this electrical insulation layer and with these a plurality of electric conductor electrical contacts, and have the first lateral dimension in the part that contacts with these a plurality of electric conductors; And wherein:
The execution that this depressed part establishment step and this dielectric medium lining form step is to make these a plurality of depressed parts around these a plurality of electric conductors, and make this material that is electrically insulated that is filled in these a plurality of depressed parts have the second lateral dimension, these a plurality of second lateral dimensions are at least greater than this first lateral dimension of some electric conductor epitaxy part.
21. method according to claim 18, before wherein more being included in this dielectric medium lining formation step, the conductive layer edge of these a plurality of depressions of oxidation.
22. method according to claim 18, wherein this depressed part establishment step comprises and makes some depressed part at least be at least 10 nanometers with respect to the depression of the insulating barrier that is adjacent.
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| CN104637900B (en) * | 2013-11-12 | 2017-07-14 | 旺宏电子股份有限公司 | IC apparatus and its manufacture method |
| CN110021603A (en) * | 2019-04-11 | 2019-07-16 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof |
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| WO2010122437A2 (en) * | 2009-04-20 | 2010-10-28 | Nxp B.V. | Multilevel interconnection system |
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| CN101583250A (en) * | 2008-05-15 | 2009-11-18 | 华为技术有限公司 | Method for processing through hole of printed circuit board, printed circuit board and communication equipment |
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