WO2007007608A1 - Dispositif de mémoire en semi-conducteur et son procédé de fabrication - Google Patents

Dispositif de mémoire en semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2007007608A1
WO2007007608A1 PCT/JP2006/313393 JP2006313393W WO2007007608A1 WO 2007007608 A1 WO2007007608 A1 WO 2007007608A1 JP 2006313393 W JP2006313393 W JP 2006313393W WO 2007007608 A1 WO2007007608 A1 WO 2007007608A1
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lower electrode
memory device
film
semiconductor memory
upper electrode
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PCT/JP2006/313393
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English (en)
Japanese (ja)
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Tetsuya Ohnishi
Shigeo Ohnishi
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Sharp Kabushiki Kaisha
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Publication of WO2007007608A1 publication Critical patent/WO2007007608A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention comprises a plurality of upper electrodes extending in the same direction and a plurality of lower electrodes extending in a direction perpendicular to the extending direction of the upper electrode, and the gap between the upper electrode and the lower electrode.
  • the present invention relates to a semiconductor memory device having a cross-point structure formed by forming a memory material body for accumulating data in each layer and a method for manufacturing the same.
  • a memory with a cross-point structure is a structure in which this selection transistor is eliminated and only a memory material body for storing data is arranged at the intersection (cross point) between the bit wiring and the word wiring. Since the accumulated data at the intersection of the selected bit line and word line is directly read out, there are problems such as delay in operation speed due to parasitic current of unselected cell force and increase in current consumption. Therefore, it is attracting attention as being capable of large capacity. Further, in the memory having this cross point structure, when the memory material body for storing data is formed independently for each memory cell, crosstalk between adjacent memory cells can be reduced.
  • a material having a velovite structure has been used as a storage material body of a crosspoint memory having such a crosspoint structure.
  • These materials include giant magnetoresistive (CMR) materials and high temperature superconducting (HTSC) materials, which have electrical resistance characteristics that can be changed by external influences.
  • CMR giant magnetoresistive
  • HTSC high temperature superconducting
  • the characteristics of the CMR material and the HTSC material can be changed by applying a predetermined electrical short pulse to, for example, a thin film or a Balta material made of the CMR material or the HTSC material.
  • the applied pulse is sufficient so that the strength of the electric field or current density is sufficient to switch the physical state of the material, and that the energy does not destroy the material and cause severe damage to the material. Set low.
  • the characteristics of the material are changed.
  • multiple parameters Applying a pulse can produce a step change in material properties.
  • One of the characteristics that can be changed by applying such electrical pulses is the resistance.
  • the use of a pulse having the opposite polarity to the pulse used to induce the initial change in characteristics can at least partially invert the characteristics.
  • Patent Documents 1 to 3 are disclosed as cross-point memories using a material having a perovskite structure.
  • FIG. 12 shows a plan layout diagram of memory cells in a conventional cross-point memory.
  • FIGS. 13 (a), (b), (c), (d), (e), (f), (G) shows each manufacturing process of the conventional memory cell in order, and shows AA, a sectional view, and a BB ′ sectional view of FIG.
  • a BP SG film 5 is formed to 1500 nm on a silicon semiconductor substrate 4 on which a memory circuit is formed, and polished to lOOOnm by CMP (chemical mechanical polishing). , Flatten the surface.
  • CMP chemical mechanical polishing
  • a contact plug 6 that connects the silicon semiconductor substrate 4 and the lower electrode is formed.
  • a TiN film 7 which is a lower electrode material is deposited on the BPSG film 5 by 50 nm by sputtering, and a Pt film 8 is deposited by 150 nm on the TiN film 7 by sputtering. To do.
  • a resist (not shown) in which the TiN film 7 and the Pt film 8 to be the lower electrode 1 are turned into an LZS (line and space) shape (stripe shape) by a known photolithography technique.
  • the lower electrode 1 as shown in FIG. 13B is formed by etching the TiN film 7 and the Pt film 8 using the Furthermore, after removing the resist mask, the SiO film 18 is removed from the CV.
  • an SiO film 19 is deposited to a thickness of 300 nm on the Pt film 8 and the SiO film 18 by a CVD method.
  • a resist (not shown) having an opening 3 for forming an active layer at the intersection of the lower electrode 1 and the upper electrode is opened by a known photolithography technique.
  • the SiO film 19 in the portion where the active layer is to be formed is etched by dry etching to expose the surface of the Pt film 8.
  • the SiO film 19 and the lower electrode are formed by sputtering.
  • a Pr Ca MnO (PCMO) film 20 as a memory material is formed to 200 nm.
  • a Pt film 17 as an upper electrode material is deposited by lOOnm by sputtering.
  • the resist 14 is patterned in an LZS (line and space) shape so that the upper electrode 2 intersects the lower electrode 1 by a known photolithography technique. -Take it. Further, the Pt film 17 is etched by dry etching to form the upper electrode 2 as shown in FIG. 13 (f).
  • a SiO film 15 having a thickness of 500 nm is formed on the Pt film 17 by a CVD method.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-68984
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-68983
  • Patent Document 3 Japanese Patent Laid-Open No. 2003-197877
  • the present invention has been made in view of the above problems, and has a smaller photo process and smaller than the minimum memory cell area defined by the minimum cache size in the manufacturing process! It is an object of the present invention to provide a semiconductor memory device having a cell area and a manufacturing method thereof.
  • a semiconductor memory device having a cross-point structure includes a plurality of upper electrodes extending in the same direction and a plurality of lower electrodes extending in a direction orthogonal to the extending direction of the upper electrode.
  • a cross-point structure semiconductor storage device comprising a storage material body for storing data in a layer between the upper electrode and the lower electrode.
  • the length in the extending direction of the upper electrode is determined in a self-aligned manner by the line width of the lower electrode, and the length in the extending direction of the lower electrode is determined in a self-aligning manner by the line width of the upper electrode. It is characterized by that.
  • a semiconductor memory device having a cross-point structure according to the present invention is characterized in that the memory material body is a perovskite material.
  • the cross-point structure semiconductor memory device is characterized in that the lower electrode material force of the lower electrode includes a material that enables the perovskite material to be formed epitaxially.
  • the lower electrode material of the lower electrode is a platinum group metal noble metal simple substance, an alloy based on the noble metal, Ir, Ru, Re, Os Oxide conductors selected from among SRO (SrRuO), LSCO ((LaSr
  • the upper electrode material of the upper electrode is selected from among platinum group noble metals, Ag, Al, Cu, Ni, Ti, and Ta.
  • It contains at least one of the above-mentioned oxide conductors.
  • the semiconductor memory device having a cross-point structure includes the perovskite material power Pr, Ca, La, Sr, Gd, Nd, Bi, Ba, Y, Ce, Pb, Sm, and Dy.
  • An acid comprising at least one element selected from internal forces and at least one element selected from Ta, Ti, Cu, Mn, Cr, Co, Fe, Ni, and Ga. It is a flea.
  • the perovskite material is a Pr Ca [Mn M] 0 system (where M is selected from Cr, Co, Fe, Ni, Ga). Selected l -XX 1 -ZZ 3
  • La AE MnO system (where AE is selected from Ca, Sr, Pb, Ba) l -X X 3
  • the semiconductor memory device having a cross-point structure according to the present invention is characterized in that the memory material body is an oxide of a transition metal element.
  • the transition metal element oxide is titanium, nickel, zinc, copper, niobium, manganese, iron, cobalt, vanadium, zirconium, or tungsten. It is characterized by the fact that it is an acid of the selected element.
  • the lower electrode material of the lower electrode is titanium, nickel, zinc, copper, niobium, manganese, iron, cobalt, vanadium, zirconium, It is characterized by comprising a material selected from among tungsten.
  • the cross-point structure semiconductor memory device is characterized in that the memory material body is an oxynitride of a transition metal element.
  • the semiconductor memory device having a cross-point structure according to the present invention includes an oxynitride strength of the transition metal element, an oxynitride of an element for which a medium strength of titanium, nickel, vanadium, zirconium, tungsten, connort, and zinc is also selected. It is a thing.
  • the lower electrode material of the lower electrode includes a conductive metal containing the same element as the transition metal constituting the memory material body that is an oxynitride. It is a characteristic nitride.
  • the semiconductor memory device having a cross-point structure according to the present invention is characterized in that the memory material body is made of titanium oxide or titanium oxynitride having a crystal grain size of 30 nm or less.
  • a method of manufacturing a semiconductor memory device includes a plurality of upper electrodes extending in the same direction and a plurality of lower electrodes extending in a direction orthogonal to the extending direction of the upper electrode.
  • a first step of sequentially forming a lower electrode material of the lower electrode, the memory material body, a conductive material for connecting the upper electrode and the memory material body, and the lower electrode material and the A memory material body and the conductive material are processed using a lower electrode mask pattern to form a second electrode, and a first insulating material is deposited on the lower electrode, the memory material body, and the conductive material.
  • 3rd step to do before A fourth step of planarizing the first insulating material and exposing a surface of the conductive material; a fifth step of depositing an upper electrode material of the upper electrode on the conductive material and the first insulating material; and the memory.
  • a material body, the conductive material, and the upper electrode material are processed using an upper electrode mask pattern to form the upper electrode, and a seventh insulating material is deposited on the upper electrode. And a process.
  • the method for manufacturing a semiconductor memory device according to the present invention is characterized in that the conductive material is a laminated film of Pt, Pt and TiN, or a laminated film of Pt, Ti and TiN.
  • a method of manufacturing a semiconductor memory device includes a plurality of upper electrodes extending in the same direction and a plurality of lower electrodes extending in a direction orthogonal to the extending direction of the upper electrode.
  • a first step of sequentially forming a lower electrode material of the lower electrode and the memory material body; and the lower electrode material and the memory material body are Processing using a mask pattern to form the lower electrode; a third step of depositing a first insulating material on the lower electrode and the memory material body; and planarizing the first insulating material; A fourth step of exposing a surface of the memory material body; a fifth step of depositing an upper electrode material of the upper electrode on the memory material body and the first insulating material; and the memory material body and the upper electrode.
  • the method comprises: covering a material with an upper electrode mask pattern to form the upper electrode; and a seventh step of depositing a second insulating material on the upper electrode.
  • the method for manufacturing a semiconductor memory device according to the present invention is characterized in that the processing force by the lower electrode mask pattern includes processing by a dry etching method.
  • the method for manufacturing a semiconductor memory device according to the present invention is characterized in that the planarization includes planarization by a chemical mechanical polishing method.
  • a method for manufacturing a semiconductor memory device is characterized in that the processing force by the upper electrode mask pattern includes processing by a dry etching method.
  • the method for manufacturing a semiconductor memory device further includes a step of forming a memory circuit for driving the semiconductor memory device before forming the memory material body. .
  • the method for manufacturing a semiconductor memory device according to the present invention is characterized in that the memory material body is a velvetskite material.
  • the method for manufacturing a semiconductor memory device according to the present invention is characterized in that the memory material body is formed of an oxide of a transition metal element or an oxynitride of a transition metal element.
  • the lower electrode material of the lower electrode constitutes the memory material body in which an oxide of a transition metal element or an oxynitride of a transition metal element is used.
  • the memory material body is formed by oxidizing the surface of the lower electrode material, which contains the same element as the transition metal.
  • each memory cell has a lower electrode as shown in FIG.
  • the length in the stretching direction is 2F pitch
  • the length in the stretching direction of the upper electrode is 2F pitch.
  • the minimum cell area is 9F 2 as shown in FIG. 12, whereas in the semiconductor memory device of the cross-point structure according to the present invention, the minimum cell area force F Thus , the cell area can be reduced.
  • the memory material body is processed simultaneously or continuously when the lower electrode is formed, and simultaneously or continuously when the upper electrode is formed.
  • a separate photo process for processing the memory material body is not required.
  • the semiconductor memory device according to the prior art requires three photo processes when forming the lower electrode, the memory material body, and the upper electrode, whereas the photo process according to the present invention is performed when the lower electrode is formed and the upper electrode is formed.
  • a semiconductor memory device having a cross-point structure can be obtained with a smaller number of photo steps since the electrode is formed twice.
  • FIG. 1 is a plan layout diagram showing memory cells of a semiconductor memory device having a cross-point structure according to the present invention.
  • FIG. 2 is a process cross-sectional view showing each process in the first embodiment of the method for manufacturing a semiconductor memory device according to the present invention.
  • FIG. 3 is a process sectional view showing each process in the first embodiment of the method for manufacturing a semiconductor memory device according to the invention.
  • FIG. 4 is a process sectional view showing each process in the second embodiment of the method for manufacturing a semiconductor memory device according to the invention.
  • FIG. 5 is a process sectional view showing each process in the second embodiment of the method for manufacturing a semiconductor memory device according to the invention.
  • FIG. 6 is a process sectional view showing each process in the third embodiment of the method for manufacturing a semiconductor memory device according to the invention.
  • FIG. 7 is a process sectional view showing each process in the third embodiment of the method for manufacturing a semiconductor memory device according to the invention.
  • FIG. 8 is a process sectional view showing each process in the fourth embodiment of the method for manufacturing a semiconductor memory device according to the invention. [9] Process sectional view showing each process in the fourth embodiment of the method for manufacturing the semiconductor memory device according to the present invention
  • FIG. 10 is a process cross-sectional view showing a modification of the method for manufacturing a semiconductor memory device according to the present invention.
  • ⁇ 11 Process cross-sectional view showing each step in another modification of the method for manufacturing a semiconductor memory device according to the present invention.
  • FIG. 12 is a plan layout diagram showing memory cells of a semiconductor memory device having a cross-point structure according to the prior art.
  • FIG. 1 is a plan layout view of a memory cell of the device of the present invention.
  • the device of the present invention includes a plurality of upper electrodes 2 extending in the same direction, A cross-point structure half comprising a plurality of lower electrodes 1 extending in a direction perpendicular to the extending direction and forming a memory material body for storing data in a layer between the upper electrode 2 and the lower electrode 1
  • the length of the upper electrode 2 in the extending direction is determined in a self-aligned manner by the line width of the lower electrode 1
  • the length of the lower electrode 1 in the extending direction is determined by the upper electrode 2. It is determined in a self-aligned manner depending on the line width of.
  • FIGS. 2 (a), (b), (c), (d), FIGS. 3 (e), (f), and (g) show the respective manufacturing steps of this embodiment in order.
  • Fig. 1 shows the AA ', BB' and CC 'sectional views of Fig. 1.
  • a BPSG film 5 having a thickness of 1500 nm is formed on a silicon semiconductor substrate 4 on which a memory circuit for driving the device of the present invention is formed. Polish to lOOOnm by mechanic mechanical polishing) to flatten the surface. Next, a contact plug 6 that connects the silicon semiconductor substrate 4 and the lower electrode 1 is formed.
  • a lower electrode material of the lower electrode 1, a perovskite material as an example of the memory material body 3, and a conductive material for connecting the upper electrode 2 and the memory material body 3 are formed on the semiconductor substrate.
  • a TiN film 7 as a lower electrode material is deposited on the BPSG film 5 by 50 nm by sputtering, and a Pt film 8 is deposited by 150 nm on the TiN film 7 by sputtering.
  • the lower electrode material is made of a conductive oxide or other conductive material.
  • the conductive material is YBa Cu O (which is a material that enables epitaxial growth of the perovskite material formed on the top.
  • the lower electrode 1 is formed to a thickness in the range of about 5 nm to about 500 nm.
  • Pr C which is a perovskite material on the Pt film 8.
  • the material is a material whose resistance value changes in response to an electrical signal having a printing force tl, and is preferably a giant magnetic resistance (CMR) material or a high temperature superconducting (HTSC) material. PCMO is used. Further, the film thickness of the perovskite material is preferably 50 nm to 500 nm. Perovskite materials can also be deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, organometallic deposition, sol-gel deposition, and organometallic chemical vapor deposition. accumulate.
  • CMR giant magnetic resistance
  • HTSC high temperature superconducting
  • a Pt film 10 and a TiN film 11 are formed on the PCMO film 9 as a conductive material for connecting the upper electrode 2 and the memory material body 3 by a sputtering method.
  • the thickness of the Pt film 10 is 50 nm
  • the thickness of the TiN film 11 is lOOnm.
  • the conductive material on the perovskite material is Pt and the conductive material under the upper electrode 2 is T iN film or Ti film.
  • the conductive material is formed to a thickness in the range of about 5 nm to about 500 nm.
  • the conductive material of this embodiment has a laminated structure of the Pt film 10 and the TiN film 11, a single layer film may be used, and Pt is preferable in that case. Furthermore, the conductive material may be a laminated film of Pt, Ti, and TiN.
  • the TiN film 7 and the Pt film 8 as the lower electrode material, the PCMO film 9 as the memory material body 3, and the Pt film 10 and the TiN film 11 as the conductive material are used by using the lower electrode mask pattern.
  • the lower electrode 1 is formed (second step). Specifically, as shown in FIG. 2 (b), a resist (not shown) patterned into an LZS (line and space) shape (stripe shape) based on the lower electrode mask pattern by a photolithography technique. ZN) is used as a mask to etch the TiN film 11 by dry etching and remove the resist.
  • LZS line and space
  • ZN is used as a mask to etch the TiN film 11 by dry etching and remove the resist.
  • the Pt film 10, PCMO film 9, Pt film 8 and TiN film 7 are simultaneously etched by a dry etching method to form the lower electrode 1.
  • the TiN film 11 is used as a mask, and the Pt film 10, PCMO film 9, Pt film 8 and TiN film 7 are continuously etched.
  • the lower electrode 1 may be formed by simultaneously etching the Pt film 10, the PCMO film 9, the Pt film 8, and the TiN film 7 together with the TiN film 11 by a dry etching method.
  • the PCMO film 9 serving as the memory material body 3 is processed in a self-aligned manner in a stripe shape having the same width as the lower electrode 1 (corresponding to the length of the upper electrode 2 in the extending direction).
  • an SiO film 12 is deposited as a first insulating material at 800 nm on the PCMO film 9 serving as the lower electrode 1 and the memory material body 3, the Pt film 10 and the TiN film 11 serving as the conductive materials by the CVD method.
  • the deposited insulating film is not limited to the SiO film.
  • any appropriate insulating film such as a imide film or a SiOF film may be used.
  • the insulating film is deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, organic metal deposition, spin-on deposition, or metal organic chemical vapor deposition. Do it.
  • the SiO film 12 is flattened by the CMP method to expose the surface of the TiN film 11 (fourth step).
  • the flattening method is not limited to the CMP method, and any appropriate flattening technique such as a spin-on method, a combination of a spinon method and an etchback method, or a combination thereof. It is also suitable to flatten using a combination.
  • the upper electrode 2 is formed on the TiN film 11 and the SiO film 12.
  • the upper electrode material is preferably conductive material such as aluminum, copper, TiN, titanium, gold, platinum, iridium, silver, etc. It is a material containing a functional material.
  • the TiN film 13 is preferably deposited to a thickness in the range of about 5 nm to about 800 ⁇ m.
  • the PCMO film 9 as the memory material body 3, the Pt film 10 and TiN film 11 as the conductive material, and the TiN film 13 as the upper electrode material are processed simultaneously or continuously using the upper electrode mask pattern.
  • the memory material body 3 and the upper electrode 2 are formed (sixth step). Specifically, as shown in FIG. 2 (c), LZS (which intersects with the lower electrode 1 based on the upper electrode mask pattern is formed on the region to be the upper electrode 2 of the TiN film 13 by a photolithography technique. Line-and-space) resist 14 is formed. Then, as shown in FIG.
  • the TiN film 13 and the TiN film 11 are etched by the dry etching method using the resist 14 as a mask to form the upper electrode 2.
  • the Pt film 10 and the PCMO film 9 are etched by the dry etching method using the TiN film 11 and the upper electrode 2 as a mask to form the memory material body 3 in a self-aligned manner.
  • the length of the upper electrode 2 in the extending direction is the same as the line width of the lower electrode 1
  • the length of the lower electrode 1 in the extending direction is the upper electrode 2. The same length as the line width.
  • the SiO film 15 is formed by the CVD method.
  • FIG. 1 is a plan layout view of a memory cell in the second embodiment of the device of the present invention (first embodiment). 4 (a), (b), (c), (d), FIG. 5 (e), and (f) show the manufacturing method in the order of steps. A-A 'cross-sectional view, BB' cross-sectional view, and CC-C 'cross-sectional view are shown.
  • a BPSG film 5 having a thickness of 1500 nm is formed on a silicon semiconductor substrate 4 on which a memory circuit for driving the device of the present invention is formed. Polishing to lOOOnm by flat polishing). Next, a contact plug 6 that connects the silicon semiconductor substrate 4 and the lower electrode 1 is formed.
  • a lower electrode material of the lower electrode 1 and a velovite material as an example of the memory material body 3 are sequentially deposited on the semiconductor substrate (first step). Specifically, first, in order to form the lower electrode 1, a TiN film 7 as a lower electrode material is deposited on the BPSG film 5 by 5 Onm by sputtering, and a Pt film 8 is deposited on the TiN film 7 by 150 nm by sputtering. accumulate.
  • the lower electrode material is made of a conductive oxide or other conductive material.
  • the conductive material is a material including YBa Cu 2 O (YBCO), which is a material that enables the epitaxial growth of the perovskite material formed on the top.
  • YBCO YBa Cu 2 O
  • the lower electrode 1 is formed to a thickness in the range of about 5 nm to about 50 Onm.
  • Pr C which is a perovskite material on the Pt film 8.
  • the material is a material whose resistance value changes in response to an electrical signal having a printing force tl, and is preferably a giant magnetic resistance (CMR) material or a high temperature superconducting (HTSC) material. PCMO is used. Further, the film thickness of the perovskite material is preferably 50 nm to 500 nm. Perovskite materials can also be deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, organometallic deposition, sol-gel deposition, and organometallic chemical vapor deposition. accumulate.
  • CMR giant magnetic resistance
  • HTSC high temperature superconducting
  • the TiN film 7 and the Pt film 8 as the lower electrode material and the PCMO film 9 as the memory material body 3 are processed using the lower electrode mask pattern to form the lower electrode 1 (second process) ).
  • the pattern is formed into an LZS (line and space) shape (stripe shape) based on the lower electrode mask pattern by photolithography.
  • the resist not shown
  • the PCMO film 9, Pt film 8 and TiN film 7 are simultaneously etched by the dry etching method to form the lower electrode 1.
  • the PCMO film 9 serving as the memory material body 3 is processed in a self-aligned manner in a stripe shape having the same width as the lower electrode 1 (corresponding to the length of the upper electrode 2 in the extending direction).
  • an SiO film 12 is deposited as a first insulating material by 600 nm on the PCMO film 9 to be the lower electrode 1 and the memory material body 3 by a CVD method (third process).
  • the deposited insulating film is
  • SiO film It is not limited to SiO film. Any suitable insulation such as SiN film, polyimide film, SiOF film, etc.
  • the insulating film may be deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, metal organic deposition, spin-on deposition, or metal organic chemical vapor deposition. Do.
  • the SiO film 12 is flattened by the CMP method to expose the surface of the PCMO film 9 (the fourth
  • the flattening method is not limited to the CMP method, and flattening can be performed using any appropriate flattening technique such as a spin-on method, a combination of a spinon method and an etchback method, or a combination thereof. Is also suitable.
  • the upper electrode 2 is formed on the PCMO film 9 and the SiO film 12.
  • Pt film 17 as upper electrode material to be deposited is deposited by sputtering method (5th step) o
  • the upper electrode material is preferably made of aluminum, copper, TiN, titanium, gold, platinum, iridium, silver, etc. It is a material containing a conductive material.
  • the Pt film 17 is preferably deposited to a thickness in the range of about 5 nm to about 500 nm.
  • the PCMO film 9 to be the memory material body 3 and the TiN film 13 as the upper electrode material are covered using the upper electrode mask pattern to form the memory material body 3 and the upper electrode 2 ( (6th process).
  • LZS crossing with the lower electrode 1 based on the upper electrode mask pattern is formed on the region to be the upper electrode 2 of the Pt film 17 by a photolithography technique.
  • Line-and-space resist 14 is formed.
  • the Pt film 17 and the PCMO film 9 are simultaneously etched by a dry etching method to form the memory material body 3 and the upper electrode 2.
  • the length of the upper electrode 2 in the extending direction is the same as the line width of the lower electrode 1, and the length of the lower electrode 1 in the extending direction is the upper electrode 2.
  • the SiO film 15 is formed by the CVD method.
  • the surface of the PCMO film 9 is exposed.
  • a dedicated insulating film embedding device or the like is not necessary, and the surface ratio is lower.
  • a semiconductor device can be manufactured at low cost.
  • the memory material body 3 is not limited to a perovskite material such as a PCMO film. That is, as with the perovskite material, even if an oxide of a transition metal element, which is a material whose electrical resistance characteristics change by application of a voltage pulse, is used as the memory material body 3, it can be manufactured with fewer photo steps and manufacturing. It is possible to achieve the object of the present invention to provide a semiconductor memory device having a memory cell area smaller than the minimum memory cell area defined by the minimum processing dimension in the process and a manufacturing method thereof.
  • a TiO (titanium oxide) film that is an oxide of titanium element instead of the PCMO film 9 as the memory material body 3 in the first embodiment.
  • FIG. 1 is a plan layout view of memory cells in the third embodiment of the device of the present invention (similar to the first and second embodiments), and FIGS. 6 (a), (b), ( c), (d), Fig. 7 (e), (f), (g), (h) show the manufacturing method in the order of steps.
  • A-A 'cross-sectional view in Fig. 1, B-B' A sectional view and a CC ′ sectional view are shown.
  • a BPSG film 5 having a thickness of 1500 nm is formed on a silicon semiconductor substrate 4 on which a memory circuit for driving the device of the present invention is formed. Polish to lOOOnm by mechanic mechanical polishing) to flatten the surface. Next, a contact plug 6 that connects the silicon semiconductor substrate 4 and the lower electrode 1 is formed.
  • a lower electrode material of the lower electrode 1 and an oxide of a transition metal element as an example of the memory material body 3 are sequentially formed on the semiconductor substrate (first step).
  • a 20 nm thick TiN film 21, a 200 nm thick AlCu film 22 and a lOOnm thick Ti23 film are respectively sputtered on the BPSG film 5 as lower electrode materials.
  • Sequentially deposited by the tulling method (TiZAl-CuZTiN laminated structure).
  • the method of oxidizing the outermost surface of the lower electrode material is not limited to thermal oxidation in an oxygen atmosphere, but uses other oxidation methods such as oxidation in oxygen plasma and ozone oxidation. May be.
  • a TiN film 25 is formed by a sputtering method.
  • the thickness of the TiN film 11 is lOOnm.
  • the lower electrode material is used for the TiN film 21, AlCu film 22 and Ti film 23 as the lower electrode material, the TiO film 24 as the memory material body 3, and the TiN film 25 as the conductive material using the lower electrode mask pattern.
  • the lower electrode 1 is formed (second step). Specifically, as shown in FIG. 6 (c), a resist (not shown) patterned into an LZS (line and space) shape (stripe shape) based on the lower electrode mask pattern by a photolithography technique. )) As a mask to dry the Ti N film 25, TiO film 24, Ti film 23, AlCu film 22 and TiN film 21 by dry etching.
  • the TiO film 24 used as the memory material body 3 is the same as the lower electrode 1.
  • an SiO film 12 is deposited as a first insulating material by 800 nm by CVD (third process).
  • the deposited insulating film is not limited to the SiO film.
  • any appropriate insulating film such as a SiOF film may be used.
  • the insulating film may be deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, metal organic deposition, spin-on deposition, or metal organic chemical vapor deposition. Do. [0077] Further, the SiO film 12 is flattened by CMP to expose the surface of the TiN film 25 (4th
  • the flattening method is not limited to the CMP method, and flattening can be performed using any appropriate flattening technique such as a spin-on method, a combination of a spinon method and an etchback method, or a combination thereof. Is also suitable.
  • the upper electrode 2 is formed on the TiN film 25 and the SiO film 12.
  • An upper electrode material film is deposited (fifth step).
  • a TiN film 26 with a thickness of 20 nm, an AlCu film 27 with a thickness of 200 nm, and a TiN28 film with a thickness of lOO nm were sequentially deposited by a sputtering method (TiNZAl—CuZTiN laminated structure).
  • the upper electrode material is preferably a material containing a conductive material such as aluminum, copper, TiN, titanium, gold, platinum, iridium, or silver.
  • TiN film 28ZA1-Cu film 27ZTiN film 26 as a material is processed simultaneously or continuously using the upper electrode mask pattern to form memory material body 3 and upper electrode 2 (sixth step).
  • the upper electrode mask is formed on the upper electrode 2 in the laminated film of the TiN film 28ZA1-Cu film 27ZTiN film 26, which is the upper electrode material, by photolithography.
  • an LZS (line & space) shaped resist 14 intersecting with the lower electrode 1 is formed. Then, as shown in FIG.
  • the TiN film 28, the Al—Cu film 27, the TiN film 26, and the TiN film 25 are etched by the dry etching method, and the upper electrode 2 Form. Further, as shown in FIG. 7 (f), the TiO film 24 is etched by a dry etching method using the TiN film 25 and the laminated film of the TiN film 28ZA1-Cu film 27ZTiN film 26 as the upper electrode 2 as a mask.
  • the TiO film 24 serving as the memory material body 3 is in the direction of stretching of the upper electrode 2.
  • the length is the same as the line width of the lower electrode 1, and the length in the extending direction of the lower electrode 1 is the same as the line width of the upper electrode 2.
  • the SiO film 15 is formed by the CVD method.
  • the formation of the TiO film 24 is not limited to the acid P
  • the film may be deposited directly on the lower electrode material by CVD or sputtering.
  • a TiO film is formed by applying a DC power of 1.5 KWZcm2 to the Ti target.
  • the lower electrode material surface need not be a material containing Ti element.
  • the lower electrode material surface need not be a material containing Ti element.
  • noble metals such as Pt, Ir, Ru, Os, Rh, Pd, Al, Cu, etc. These metal elements or alloys containing these metals can be arbitrarily selected.
  • the TiO film 24 as the memory material body 3 is formed on the lower electrode.
  • a memory material body When formed by oxidizing the material surface, a memory material body can be formed by a heat treatment process of acid and soot, which is a common process in semiconductor processes, and a special apparatus for the film formation is required. do not do.
  • titanium oxide is represented by TiO. This is the composition ratio of each element.
  • the yarn resistance ratio is such that the electric resistance characteristics change due to electric pulses, the application to the present invention as a memory material body is not hindered.
  • a TiO film is applied instead of the PCMO film 9 of the first embodiment.
  • a TiO film is used instead of the PCMO film 9 in the second embodiment.
  • the memory material body 3 is not limited to a perovskite material such as a PCMO film.
  • the applicant of the present application has found that the electrical resistance characteristics of a transition metal element oxynitride change by application of a voltage pulse, as in the case of perovskite materials (Japanese Patent Application: Japanese Patent Application No. 2005-228600). Issue). Even if the material is used as the memory material body 3, a semiconductor memory device having a memory cell area smaller than the minimum memory cell area defined by the minimum processing dimension in the manufacturing process with fewer photo processes and its manufacture The object of the present invention of providing a method can be achieved.
  • FIG. 1 is a plan layout view of memory cells in the fourth embodiment of the device of the present invention (similar to the first to third embodiments), and FIGS. 8 (a), (b), (c ), (D), and FIGS. 9 (e), (f), (g), and (h) show the manufacturing method in the order of steps, and are taken along the lines AA 'and B-B' in FIG. Figure and C-C 'sectional view are shown
  • a BPSG film 5 having a thickness of 1500 nm is formed on a silicon semiconductor substrate 4 on which a memory circuit or the like for driving the device of the present invention is formed. Polishing to lOOOnm by flat polishing). Next, a contact plug 6 that connects the silicon semiconductor substrate 4 and the lower electrode 1 is formed.
  • a lower electrode material of the lower electrode 1 and an oxynitride of a transition metal element as an example of the memory material body 3 are sequentially formed on the semiconductor substrate (first step). More specifically, first, in order to form the lower electrode 1, a TiN film 21 having a thickness of 20 nm, an AlCu film 22 having a thickness of 200 nm, and a TiN29 film having a thickness of lOO nm are formed on the BPSG film 5 as lower electrode materials. Each is deposited sequentially by sputtering (TiNZAl—CuZTiN laminated structure).
  • the lower electrode material is made of conductive nitride or other conductive material.
  • the memory material body 3 heat treatment is performed in an atmosphere containing oxygen at 250 to 450 ° C.
  • the surface of the TiN film 29, which is the uppermost layer of the lower electrode material film is thermally oxidized, and the TiON film 30 as an example of the memory material body 3 is thickened. It is formed with a thickness of 1 Onm.
  • the TiN film 21, AlCu film 22 and TiN film 29 as the lower electrode material and the TiON film 30 as the memory material body 3 are covered using the lower electrode mask pattern to form the lower electrode. 1 is formed (second step). More specifically, as shown in FIG. 8 (c), a resist (not shown) patterned into an LZS (line and space) shape (stripe shape) based on the lower electrode mask pattern by a photolithography technique. ), The TiON film 30, TiN film 29, A1 Cu film 22 and TiN film 21 are sequentially etched by dry etching. This The TiON film 30 serving as the memory material body 3 is processed in a self-aligned manner in a stripe shape having the same width as the lower electrode 1 (corresponding to the length of the upper electrode 2 in the extending direction).
  • an SiO film 12 is deposited as a first insulating material by 600 nm on the lower electrode 1 and the TiON film 30 to be the memory material body 3 by a CVD method (third process).
  • the deposited insulating film is
  • SiO film It is not limited to SiO film. Any suitable insulation such as SiN film, polyimide film, SiOF film, etc.
  • the insulating film may be deposited using any suitable deposition technique such as pulsed laser deposition, RF-sputtering, electron beam evaporation, thermal evaporation, metal organic deposition, spin-on deposition, or metal organic chemical vapor deposition. Do.
  • the SiO film 12 is flattened by a CMP method to expose the surface of the TiON film 30 (the fourth
  • the flattening method is not limited to the CMP method, and flattening can be performed using any appropriate flattening technique such as a spin-on method, a combination of a spinon method and an etchback method, or a combination thereof. Is also suitable.
  • the upper electrode 2 is formed on the TiON film 30 and the SiO film 12.
  • An upper electrode material film is deposited (fifth step).
  • a TiN film having a thickness of 20 nm, an AlCu film having a thickness of 200 nm, and a TiN film having a thickness of lOOnm were sequentially deposited by a sputtering method (TiNZAl—CuZTiN laminated structure).
  • the upper electrode material is preferably a material containing a conductive material such as aluminum, copper, TiN, titanium, gold, platinum, iridium, or silver.
  • the laminated film of the TiON film 30 serving as the memory material body 3 and the TiN film 28ZA1 — Cu film 27ZTiN film 26 as the upper electrode material was processed simultaneously or continuously using the upper electrode mask pattern,
  • the memory material body 3 and the upper electrode 2 are formed (sixth step).
  • the upper electrode is formed on the region to be the upper electrode 2 of the laminated film of the TiN film 28ZA 1—Cu film 27ZTiN film 26, which is the upper electrode material, by a photolithography technique.
  • an LZS (line and space) shaped resist 14 intersecting with the lower electrode 1 is formed. Then, as shown in FIG.
  • the TiN film 28, the Al—Cu film 27, the TiN film 26, and the TiON film 30 are sequentially etched by a dry etching method to obtain a memory material.
  • the TiON film 30 serving as the memory material body 3 has a length in the extending direction of the upper electrode 2 that is the same as the line width of the lower electrode 1.
  • the length in the extending direction of 1 is the same as the line width of the upper electrode 2.
  • the SiO film 15 is formed by the CVD method.
  • the TiON film 30 as the memory material body 3 is formed by oxidizing the conductive nitride that is the surface of the lower electrode.
  • the formation of the TiON film 30 is limited to oxidation.
  • it may be deposited directly on the lower electrode material by CVD or sputtering.
  • bias ECR—CVD using TiCl and N 2 O as source gases at a processing temperature of 400 ° C.
  • It can be formed by the method (Bias Electron Cyclotron Resonance Chemical Vapor Deposition). Also, for example, reaction with Ti as a target in N—O mixed gas.
  • the film may be formed by a reactive sputtering method, or there is a method of forming a sputtering film in Ar gas with a TiON sintered target.
  • the lower electrode material does not need to be made of conductive nitride.
  • the TiON film 30 as the memory material body 3 is formed by oxidizing the surface of the lower electrode as in the present embodiment, the oxidation process, which is a general process in a semiconductor process, is performed.
  • the memory material body can be formed by the heat treatment process, and no special apparatus is required for the film formation.
  • titanium nitride as the lower electrode material
  • titanium oxynitride which is the oxide of the memory material body
  • the force in which titanium oxynitride is expressed by TiON does not strictly limit the composition ratio of each element.
  • the titanium oxynitride according to the present invention is a titanium compound containing at least oxygen and nitrogen, and particularly if the yarn has a composition ratio in which the electric resistance changes depending on the electric norus, the book as a memory material body. It does not prevent application to the invention.
  • the present embodiment is an example in which a TiON film is applied instead of the PCMO film 9 of the second embodiment.
  • a TiON film is used instead of the PCMO film 9. Suitable Embodiments to be used are easily possible.
  • the force described in the example in which the conductive material as the lower electrode material of the lower electrode 1 is made of a material containing YB co, platinum, iridium, or the like.
  • at least one element selected from the internal forces of Sm and Dy and at least one element selected from Ta, Ti, Cu, Mn, Cr, Co, Fe, Ni, and Ga It may be an acid oxide or a Pr i Ca [Mn M] 0 series (where M is any selected from Cr, Co, Fe, Ni, Ga)
  • La AE MnO system (where AE is selected from Ca, Sr, Pb, Ba)
  • An oxide of a system represented by (0 ⁇ X ⁇ 1, 0 ⁇ Z ⁇ 1) may be used.
  • TiN and Pt are used as the upper electrode material.
  • the upper electrode material is not limited to this, and a platinum group metal noble metal, Medium force of Ag, Al, Cu, Ni, Ti, Ta Selected metal simple substance or its alloy, oxide conductor selected from Ir, Ru, Re, Os, SRO (SrRuO), LSCO ( (LaSr) C
  • YBCO YbBa Cu O
  • the device of the present invention is driven before depositing a memory material body such as a perovskite material, an oxide of a transition metal element, or an oxynitride of a transition metal element. It is also preferable to further include a step of forming a memory circuit for this purpose.
  • a memory circuit or the like for driving the device of the present invention is formed.
  • a memory circuit or the like is formed in the lower portion of the device of the present invention using the silicon semiconductor substrate 4, the memory circuit or the like that is strong may be formed in the peripheral portion not in the lower portion of the device of the present invention. I do not care.
  • the transition metal oxide as the memory material body is an acid titanium
  • the transition metal oxide is an acid titanium.
  • the memory material body is not limited to nickel, zinc, copper, niobium, manganese, iron, cobalt, nonadium, zirconium, and tungsten. Further, in this case, if the lower electrode material of the lower electrode is a material containing any of these elements, a memory material body can be formed by oxidizing it.
  • the transition metal oxynitride as the memory material body is titanium oxynitride
  • the transition metal oxynitride is limited to titanium oxynitride.
  • an oxynitride of an element selected from among nickel, vanadium, zirconium, tandasten, cobalt, and zinc may be used.
  • the lower electrode material force of the lower electrode is a conductive nitride containing any of these elements, a memory material body can be formed by oxidizing it.
  • the storage material body 3 is made of titanium oxide and titanium oxynitride, respectively.
  • the applicant of the present application shows a greater change in electrical resistance characteristics due to electrical pulses when the crystal grain size of the titanium oxide or titanium oxynitride that is the memory material body 3 is 30 nm or less. I found out (see Japanese Patent Application: Japanese Patent Application No. 2005-3 75852). Therefore, it is preferable to form the TiO film 24 or the TiON film 30 so that the crystal grain diameter is 30 nm or less in each of the first steps in the third and fourth embodiments.
  • a TiO film 24 having a crystal grain size of 30 nm or less is formed by DC magnetron sputtering.
  • the sputtering target is a metal Ti target
  • Ar is introduced at a flow rate of 5 sccm
  • O is introduced at 15 sccm
  • the pressure is 3-15.
  • the produced TiO film 24 shows anatase-type titanium oxide having a crystal grain size of 30 nm or less.
  • an amorphous type titanium oxide film is formed on the lower electrode material film.
  • an electric furnace or a lamp heating device is used after formation in an oxygen-nitrogen mixed gas atmosphere having an oxygen concentration of 5% to 100%, or in an oxygen-argon mixed gas atmosphere having an oxygen concentration of 5% to 100%. Apply heat treatment at 250 ° C to 500 ° C. This makes it possible to form an anatase-type titanium oxide film.
  • the method of forming the TiO film 24 is limited to the DC magnetron sputtering method.
  • the substrate is heated to 250 ° C to 500 ° C, and the raw material is TiCl or Ti (OCH) which is an organic metal raw material
  • the titanium oxide film formed at a low substrate temperature shows an amorphous type. Therefore, as in the case of the DC magnetron sputtering method described above, titanium oxide is formed. Later, an anatase-type titanium oxide film is formed by heat treatment at 250 ° C. to 500 ° C. in an oxygen atmosphere.
  • the force for connecting the silicon semiconductor substrate 4 and the lower electrode 1 via the contact plug 6 is not limited to such a configuration.
  • this connection may be made by an A1 wiring formed on the lower electrode 1.
  • the apparatus of the present invention can be formed by other modified examples of the process.
  • FIGS. Ll (a) to (d) show the manufacturing method in the order of steps, and show the AA ′, BB ′ and CC ′ sectional views of FIG. Yes.
  • the BPSG film 5 having a flat surface, the silicon semiconductor substrate 4 and the lower electrode 1 are connected.
  • Form plug 6 a TiN film 7 as a lower electrode material is deposited on the BPSG film 5 by 50 nm by sputtering, and a Pt film 8 is deposited on the TiN film 7 by 150 nm by sputtering.
  • a SiN film 31 is deposited on the Pt film 8 to a thickness of lOOnm.
  • the TiN film 7 and the Pt film 8 as the lower electrode material and the SiN film 31 are covered using the lower electrode mask pattern.
  • a resist (not shown) patterned into an LZS (line & space) shape (strip shape) based on the lower electrode mask pattern by a photolithography technique.
  • the SiN film 31, the Pt film 8 and the TiN film 7 are simultaneously etched by a dry etching method.
  • SiO film 12 is flattened by CMP method.
  • a PCMO film 9 to be the memory material body 3 is deposited by sputtering to a thickness of 250 nm. After that, the surface is flattened by CMP to expose the surface of the SiO film 12.
  • a semiconductor device and a manufacturing method thereof according to the present invention include a plurality of upper electrodes extending in the same direction and a plurality of lower electrodes extending in a direction orthogonal to the extending direction of the upper electrode, and the upper electrode and the lower electrode It can be used for a semiconductor memory device having a cross-point structure in which a memory material body for storing data is formed in a layer between the two.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Le dispositif de mémoire en semi-conducteur selon l’invention présente une aire de cellule mémoire inférieure à l’aire de cellule mémoire minimale définie par les dimensions de fabrication minimales du processus de fabrication et est fabriqué avec un nombre inférieur d'étapes photolithographiques. L'invention concerne également un procédé de fabrication de ce dispositif mémoire en semi-conducteur. Le dispositif mémoire en semi-conducteur comprend une pluralité d’électrodes supérieures (2) s’étendant dans la même direction et une pluralité d'électrodes inférieures (1) s'étendant dans la direction perpendiculaire à la direction d'extension des électrodes supérieures (2), et comporte une structure de points de connexion dans laquelle un élément en matériau de mémoire servant à enregistrer les données est fomré dans une couche entre l'électrode supérieure (2) et l’électrode inférieure (1). La longueur de l’élément en matériau de mémoire dans la direction d’extension de l’électrode supérieure (2) est déterminée par la largeur de la ligne de l’électrode inférieure (1) de manière auto-alignée ; la longueur de la direction d’extension de l’électrode inférieure (1) est déterminée par la largeur de la ligne de l’électrode supérieure (2) de manière auto-alignée.
PCT/JP2006/313393 2005-07-12 2006-07-05 Dispositif de mémoire en semi-conducteur et son procédé de fabrication WO2007007608A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096674A1 (fr) * 2007-02-09 2008-08-14 Sharp Kabushiki Kaisha Dispositif de stockage semi-conducteur non volatile et son procédé de réécriture
JP2009071304A (ja) * 2007-09-10 2009-04-02 Samsung Electronics Co Ltd 抵抗変化型メモリ素子及びその形成方法
JP2009130139A (ja) * 2007-11-22 2009-06-11 Toshiba Corp 不揮発性半導体記憶装置の製造方法
JP2010225813A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 不揮発性記憶装置およびその製造方法
JP2012174818A (ja) * 2011-02-21 2012-09-10 Hitachi Ltd 半導体記憶装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003068983A (ja) * 2001-06-28 2003-03-07 Sharp Corp 電気的にプログラム可能な抵抗特性を有する、クロストークが低いクロスポイントメモリ
JP2004006579A (ja) * 2002-04-18 2004-01-08 Sony Corp 記憶装置とその製造方法および使用方法、半導体装置とその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003068983A (ja) * 2001-06-28 2003-03-07 Sharp Corp 電気的にプログラム可能な抵抗特性を有する、クロストークが低いクロスポイントメモリ
JP2004006579A (ja) * 2002-04-18 2004-01-08 Sony Corp 記憶装置とその製造方法および使用方法、半導体装置とその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096674A1 (fr) * 2007-02-09 2008-08-14 Sharp Kabushiki Kaisha Dispositif de stockage semi-conducteur non volatile et son procédé de réécriture
US8139392B2 (en) 2007-02-09 2012-03-20 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device and writing method of the same
JP2009071304A (ja) * 2007-09-10 2009-04-02 Samsung Electronics Co Ltd 抵抗変化型メモリ素子及びその形成方法
JP2009130139A (ja) * 2007-11-22 2009-06-11 Toshiba Corp 不揮発性半導体記憶装置の製造方法
JP2010225813A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 不揮発性記憶装置およびその製造方法
JP2012174818A (ja) * 2011-02-21 2012-09-10 Hitachi Ltd 半導体記憶装置およびその製造方法

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