WO2007012290A1 - Procede de production de silicium sur isolant - Google Patents

Procede de production de silicium sur isolant Download PDF

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Publication number
WO2007012290A1
WO2007012290A1 PCT/CN2006/001901 CN2006001901W WO2007012290A1 WO 2007012290 A1 WO2007012290 A1 WO 2007012290A1 CN 2006001901 W CN2006001901 W CN 2006001901W WO 2007012290 A1 WO2007012290 A1 WO 2007012290A1
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Prior art keywords
silicon
layer
thickness
insulator according
ion implantation
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PCT/CN2006/001901
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English (en)
French (fr)
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Meng Chen
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Shanghai Simgui Technology Co., Ltd
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Application filed by Shanghai Simgui Technology Co., Ltd filed Critical Shanghai Simgui Technology Co., Ltd
Priority to EP06775242A priority Critical patent/EP1914799A4/en
Publication of WO2007012290A1 publication Critical patent/WO2007012290A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Definitions

  • the invention relates to a process for ion-implanting bonding and thinning to prepare silicon on an insulator. It is a manufacturing process for microelectronics and solid-state electronics, silicon-based integrated optoelectronic device materials. Background technique
  • the silicon-on-insulator (SOI) circuit has the advantages of high speed, low power and anti-irradiation. It has an important application background in aerospace, military electronics, portable communication, etc. It is considered to be the 21st century. Silicon integrated circuit technology has received much attention ( ⁇ P.Colige, Silicon on Insulator Technology, Material to VLSI, ulwer Academic Publication 1991) 0 With the development of automotive electronic integrated circuits, audio power amplifier integrated circuits, lighting, etc. The demand for power devices is becoming more and more extensive, and the good insulation performance of SOI substrates has attracted much attention in the field of power devices. (F. Udrea, D. Garner, . Sheng, A. Guatemala, HT Urn and WI Milne, SOI Power Devices, Electronics and Communication Engineering Journal, Feb. 2000, p27)
  • Oxygen injection isolation ie SIMOX technology and bonding thinning technology
  • SOI substrates are two of the current mainstream technologies for preparing SOI substrates.
  • the former forms a SOI structure by injecting a high-dose oxygen ion into a single crystal silicon wafer and annealing at a high temperature to form a buried insulating Si ⁇ 2 (BOX) layer.
  • BOX buried insulating Si ⁇ 2
  • the latter is to first bond a piece of thermally oxidized silicon wafer to a piece of light, and then thin the back surface to the desired thickness to form an SOI structure.
  • the SIMOX technology uses high-energy (20 ⁇ 300keV), large beam (10' 7 0 18 cm - 2 ) oxygen ion implantation, forms oxygen enriched regions at a certain depth in the silicon wafer, and then forms a buried layer after high temperature annealing. Si ⁇ 2 in silicon, the BOX layer.
  • the SOI wafer formed by this process is limited by the implantation energy and dose.
  • the thickness of the BOX and the top silicon can be adjusted to a very limited range and is not very lively.
  • the maximum thickness of the BOX is hard to exceed 400 nm, and the maximum thickness of the top silicon is only about 300 nm.
  • the SIMOX process utilizes high temperature annealing to promote the formation of oxygen in the interior of the silicon to form a BOX layer, which makes the insulating properties of the BOX not as good as the thermal oxidization of Si ⁇ 2 .
  • These shortcomings limit the application of SIMOX technology in thick buried layers (>400
  • the bonding thinning process involves bonding a silicon wafer having a thermal oxide layer on one surface to another wafer and thinning the back surface of the wafer to a desired thickness.
  • the S ⁇ l wafer produced by this process although the quality of the BOX can be better ensured, the thickness of the top silicon is difficult to obtain precise control.
  • ⁇ W. Neuner uses plasma-assisted chemical etching to thin the top layer of silicon to ⁇ ⁇ and the flatness to within ⁇ 0.1 ⁇ . (JW Neuner, AM Ledger, S. . Schilb, and DPMathur, Improved Uniformity in Bonded SOI wafers with Active Layers from 1 ⁇ o 30 ⁇ a ⁇ High Throu ⁇ hpu ⁇ s, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, P.169-170) However, it is more difficult to further reduce the thickness of the top layer by grinding or etching to achieve a smaller thickness and flatness. These shortcomings also limit the application of the bond thinning process in terms of high uniformity requirements
  • SOITEC Based on the traditional bonding thinning process, SOITEC introduced Unibond technology.
  • One of the key steps of this technology is to form a Bubble Layer by a hydrogen ion implantation process, which is automatically split in a subsequent annealing process, thereby using the cracking layer to more precisely control the pre-polishing SOI layer uniformity, finally achieving precise control top
  • the invention provides a production process for preparing an SOI wafer by ion implantation combined with bonding and thinning.
  • the advantage of the implantation process is that the top silicon is thin and the uniformity is well controlled, and the bonding thinning process has the advantage that the BOX thickness can be adjusted over a wide range and the insulation performance is good.
  • the invention combines the advantages of the two processes, enhances the strengths and avoids the shortcomings, and exerts the advantages of both, and can be used to prepare a high-quality SOI wafer whose thickness of the buried layer can be adjusted while ensuring the uniformity of the thickness of the top silicon.
  • the invention comprises the following steps: Firstly, the device piece is formed by an ion implantation process (if the top layer silicon of the final product is desired to be relatively thick, the ion implantation piece needs to be epitaxially or after the final process is completed, the top layer silicon is extended, still referred to as a device piece. ), bonding the device piece (or the device piece containing the oxide layer) and the support piece (or the oxidized support piece), and annealing and strengthening in an atmosphere containing oxygen or water vapor, and then etching to the device piece by grinding and etching
  • the injection layer, ie, the self-stop layer is finally etched away from the stop layer and the top layer of silicon is finely ground or oxidized to form the final SOI wafer.
  • the thickness of the final product BOX and top layer silicon is determined by the oxide layer thickness and the implant depth (or epitaxial thickness) of the device.
  • the method for preparing silicon on an insulator according to the present invention comprises the following steps:
  • Ion implantation a corresponding ion implantation process is used to inject a layer of ions into the semiconductor material
  • the appropriate process parameters are selected for the device piece or the supporting piece to perform appropriate insulating layering treatment;
  • the single-sided back-grinding device piece thins the device piece to a certain thickness
  • the semiconductor material is silicon, gallium arsenide, indium phosphide or Ge
  • the device piece is prepared by an ion implantation process.
  • the implanted ions may be selected from N ions, O ions, or other ions; the basic principle of selecting ions is that the ion implantation layer acts as a chemical corrosion barrier. Commonly used ions are oxygen ions.
  • the ion implantation energy is between 1 OKeV and 500 KeV, and the ion implantation dose is between 1 E15/cm 2 and 1 E19/cm 2 ;
  • the optimized ion implantation energy is between 70 KeV and 250 KeV, and the ion implantation dose is between 5E1 0/cm 2 and 2E18/CIT1 2 ; the implantation concentration is between 500 and 10000 A; the implantation temperature is 20-70 CTC; Single temperature or multi-step multi-temperature composite injection.
  • the ion implantation can be carried out by using a relatively mature SIM ⁇ X (Separa ⁇ ion-by-Oxygen Implantation) oxygen ion implanter using a SIMOX implantation process.
  • the optimized oxygen ion implantation energy is between 30KeV and 250KeV, and the ion implantation dose is between 5E10/cm 2 and 2E18/CID 2 ; the optimized oxygen ion implantation energy is between 70-250 KeV, and the ion implantation dose is Between 5E16/cm 2 and 7E17/cm 2 , the optimum injection depth is between 1000 and 5000 angstroms and the injection temperature is 20-550 ⁇ .
  • the device piece can be subjected to subsequent processing (including high-temperature annealing treatment), and the purpose of the treatment is to make the interface between the injection layer and the non-injection layer steep, so that the chemical corrosion is easy to stop at the interface.
  • subsequent processing including high-temperature annealing treatment
  • the temperature of the subsequent high-temperature treatment of the device piece is between 600 ° C and 1500 ° C, and the temperature rise and fall is 0. 5-10 ° C / min; the atmosphere is an oxygen-argon or oxygen-nitrogen mixed atmosphere, wherein the oxygen content It is between 0% and 100%.
  • the device piece may not be subjected to subsequent processing, but the ion implantation dose is large, and a barrier layer capable of blocking specific chemical corrosion is formed without subsequent high temperature treatment, that is, an etching barrier layer having a corrosion self-stop function is formed;
  • the device piece can be formed by directly removing the silicon dioxide of the surface layer after the high temperature annealing treatment of the injection sheet, or not removing the silicon dioxide formed by the high temperature annealing treatment, and the mature diluted HF solution in the semiconductor process can be used.
  • the silica that is not removed will eventually be part of the 310 2 buried layer of the most S0I wafer.
  • the subsequent high temperature treatment of the device piece is optimized between 1100 degrees Celsius and 1350 degrees Celsius, and the optimized oxygen content is between 0% and 60%.
  • the etching process may be chemical etching, plasma etching or any other etching method that can be stopped at the ion implantation layer.
  • the epitaxial layer of a certain thickness can be grown by epitaxial method according to the requirements of the final product for the thickness of the top layer silicon, or by removing the silicon dioxide of the surface layer, that is, the epitaxial layer is grown on the top silicon of the original ion implantation sheet.
  • the epitaxial process can employ conventional processes commonly employed in the semiconductor industry.
  • the epitaxy can be a homoepitaxial or a heteroepitaxial.
  • the epitaxial layer can be P-type or N-type, doped with boron or phosphorus, and other dopants.
  • the insulating layer or the oxidized insulating layer will be a buried layer of the final SOI wafer
  • the insulating layer may be silicon dioxide (Si ⁇ 2 ), silicon nitride (Si 3 N 4 ) or other insulating material, and the insulating treatment may be performed separately on the device piece or the support sheet, or both. At the same time.
  • the insulating layering treatment refers to a method of growing an insulating layer, such as an oxidation method of growing Si ⁇ 2 , or a method of nitriding Si 3 N 4 .
  • the commonly used insulating layer is Si ⁇ 2
  • the treated insulating layer is The buried layer of the final SOI wafer; the thickness of the oxidation treatment is between 0.15 ⁇ m; the sum of the thickness of the oxide layer of the device piece and the support sheet will be the thickness of the final SOI wafer.
  • the oxidation process for the silicon wafer may be carried out by a mature oxidation preparation process in an integrated circuit, such as a dry oxygen oxidation process or a dry oxygen-wet oxygen-dry oxygen process.
  • the oxidized silicon wafer can be selected from a device piece or a support sheet.
  • the commonly used insulating layer is Si0 2 .
  • the device piece and the support piece are bonded by a bonding process.
  • the bonding process can be carried out using EVG's EVG bonder or other company's bonder. Bonding is typically carried out at room temperature, and plasma assisted room temperature bonding can also be employed.
  • the annealing atmosphere during the annealing and strengthening may be an oxygen-containing atmosphere, and may be dry oxygen, wet oxygen or a mixed gas.
  • the annealing and strengthening temperature is 200 degrees Celsius or more and 1400 degrees Celsius or less, and the time is half an hour to 15 hours.
  • the optimized degradation temperature is 1000 250 degrees Celsius, and the atmosphere is wet oxygen for 2 hours to ⁇ hours.
  • the single-sided thinning can be performed by a plate grinder or other equipment capable of thinning the silicon wafer. Thinning to a certain thickness range l unn ⁇ 100um.
  • the etching method described must be such that the corrosion ratio of the material to be etched and the ion implantation layer is sufficiently large to achieve self-stopping at the ion implantation layer.
  • the etching solution for chemically etching silicon is potassium hydroxide (KOH) or tetramethylammonium hydroxide (THMA) or other chemical agent having a large selective etching ratio to the ion implantation layer and silicon.
  • KOH potassium hydroxide
  • THMA tetramethylammonium hydroxide
  • Dilute potassium hydroxide (KOH) or tetramethylammonium hydroxide (THMA) is generally selected for etching silicon.
  • the ratio of corrosive liquid is generally 1:1000 (chemical agent: deionized water), and it needs to be heated during corrosion.
  • the temperature is usually between 25 °C and 200 °C.
  • the optimized etching solution is generally in the range of 1:1 to 1:100 (chemical agent: deionized water); the optimum etching temperature is between 50 degrees Celsius and 150 degrees Celsius.
  • the method of removing the ion implantation layer may be an etching method, or may directly adopt a polishing method.
  • the HF solution can be used for chemical etching.
  • the concentration of the HF solution can be adjusted from 1:1 to 1:2000.
  • the optimized HF solution concentration ratio is 1:10 to 1:100.
  • Fine polishing of the top layer can be done by chemical mechanical polishing machine or oxidation to adjust the thickness of the top silicon of the final SOI wafer, while making the surface smoother.
  • the thickness of the chemical mechanical polishing is between 300-5000A, and the thickness of common chemical mechanical polishing is removed. Between 300-3000A; the thickness of the silicon layer treated with oxidation is between 300-10000A, usually between 300-5000A
  • the injection sheet produced by the injection process can obtain nanometer-scale top layer silicon, which can reach a minimum of 30 nm, and the thickness uniformity can be freely adjusted in a small range ( ⁇ 10 nm), which is a single bonding thinning process. Unreachable thickness and uniformity.
  • the SOI wafer produced by the single bond thinning method, the BOX layer is prepared by thermal oxidation, which allows the thickness to be adjusted over a relatively large range.
  • the present invention combines the advantages of the two processes, complements each other, and exerts their respective advantages to overcome their respective shortcomings.
  • the SOI wafer prepared by the invention is prepared by thermal oxidation method, has good insulation performance and uniform thickness (the thickness can be adjusted between 0 and 5.0 ⁇ ); and the top silicon is "transplanted" from the injection sheet or the epitaxial injection sheet.
  • the self-stopping effect of the injection layer of the injection sheet effectively ensures the thickness and uniformity of the top silicon before the final fine polishing (the thickness uniformity before polishing can reach ⁇ 10 nm), and the uniformity of the thickness of the final SOI layer.
  • the thickness uniformity before polishing can reach ⁇ 10 nm
  • Step 1 Injecting oxygen ions into the original polishing pad 10, the energy is 190 KeV, the dose is 3.0E17/cm2, the injection temperature is 300 degrees, and the injection layer is marked as 11;
  • Step 2 The injection sheet was annealed at a high temperature with a ratio of oxygen of 0.5%.
  • the annealing temperature is 1330 degrees Celsius, and the annealing atmosphere is argon containing oxygen;
  • Step 3 10 pieces of the etch stop layer were obtained, the thickness of the surface layer silicon was about 230 ⁇ 5 nm, the thickness of the buried layer was about 90 ⁇ 5 nm, and the thickness of the surface layer Si ⁇ 2 was 400 ⁇ 5 nm.
  • the injection layer 11 became the etch stop layer 12 (ie buried oxygen layer).
  • the surface layer of the labeled silicon is 13, and the surface layer Si ⁇ 2 is labeled 14;
  • Step 4 Oxidize the silicon wafer 20 with an oxide layer thickness of about 000 ⁇ 5 nm, labeled 21
  • Step 5 Combine the wafer 10 and 20 bonds and anneal them.
  • the annealing temperature is 1150 ° C, and the water vapor is oxidized for 3 hours;
  • Step 0 The reinforced 10 back side is thinned by a sander with a remaining thickness of approximately 15 microns, labeled 15.
  • Step 7 The thinned film is etched with KOH.
  • concentration of the etching solution is 1:20 by mass (deionized water: K ⁇ H), the temperature is 70 degrees Celsius, about 25 minutes, and 15 is removed.
  • Step 8 Place the removed 15 pieces in 1:10 HF for about 30 seconds, remove 12;
  • Step 9 After the implementation of 8, the chemical mechanical polishing machine throws about 50nm, the remaining SOI layer thickness is 10;
  • the final SOI wafer was obtained with the following parameters:
  • the thickness of the SOI layer 16 was 195.3 nm, and the uniformity was
  • Step 1 Injecting oxygen ions into the original polishing pad 10, the energy is 190 KeV, the dose is 2.5E17/cm2, the injection temperature is 300 degrees, and the injection layer is marked as 11;
  • Step 2 Anneal the injection sheet at high temperature.
  • the annealing temperature is 1330 degrees Celsius, the annealing atmosphere is oxygen-containing argon;
  • Step 3 10 pieces with corrosion stop layer are obtained, the surface layer silicon thickness is about 250 ⁇ 5 nm, the buried layer thickness is about 80 ⁇ 10 nm, and the surface layer Si ⁇ 2
  • the thickness of the implant layer 11 becomes the etch stop layer 12 (ie, the buried oxide layer).
  • the labeled surface layer silicon is 13, and the surface layer Si ⁇ 2 is labeled 14;
  • Step 4 10 sheets were cleaned and the surface layer Si 214 was removed, and then the epitaxial layer was deposited to have a thickness of 1.40 um and a mark of 31.
  • Step 5 The epitaxial 10 pieces are oxidized, the oxidation temperature is 1000 degrees, and the oxide layer thickness is 200 nm ⁇ 10 nm, labeled 17.
  • Step 0 The silicon wafer 20 is oxidized to a thickness of about 800 ⁇ 5 nm, labeled 21
  • Step 7 The silicon wafers 10 and 20 are combined and annealed to be reinforced.
  • the annealing temperature is 1150 ° C, and the water vapor is oxidized for 3 hours;
  • Step 8 The reinforced 10 back side is thinned by a plater with a remaining thickness of approximately 15 microns, labeled 15.
  • Step 9 The thinned film is etched with KOH.
  • concentration of the etching solution is 1:20 (deionized water: K ⁇ H), and the temperature is 70 degrees Celsius, about 25 minutes, removed. 15
  • Step 10 The sheet after removing 15 is rinsed in 1:10 HF for about 30 seconds, and 12 is removed;
  • Step 11 After the implementation of 8, the chemical mechanical polishing machine is thrown away by about 100 nm, and the remaining SOI layer is marked as 18
  • the final SOI wafer was obtained with the following parameters: SOI layer thickness 1.548 um, uniformity ⁇ 21.5 nm; buried layer thickness 1000 ⁇ 10 nm, 17 plus 21, total thickness 1000 ⁇ 10 nm.
  • Figure 4 shows the uniformity test data for the thickness of the SOI layer.

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Description

一种绝缘体上硅的制作方法 技术领域
本发明涉及一种离子注入结合键合减薄的工艺， 制备绝缘体上的硅。 属于微电子与固体 电子学、 硅基集成光电子器件材料的一种制造工艺。 背景技术
绝缘体上的硅即 SOI(Silicon-on-insulator)电路具有高速，低功率，抗辐照等优点，在航 空航天， 军工电子， 便携式通讯等方面具有重要的应用背景， 被认为是二十一世纪的硅集成 电路技术， 倍受人们重视 (丄 P.Colige, Silicon on Insulator Technology, Material to VLSI, ulwer Academic Publication 1991 ) 0 随着汽车电子集成电路、 声频功率放大集成电路、 照明等的发展， 对功率器件的需求越来越广泛， SOI 衬底良好的绝缘性能， 使其在功率器件 领域的应用前景尤其倍受关注。 (F. Udrea, D. Garner, . Sheng, A. Popescu, H.T. Urn and W.I. Milne, SOI Power Devices, Electronics and Communication Engineering Journal, Feb. 2000, p27)
注氧隔离即 SIMOX技术以及键合减薄技术是目前制备 SOI衬底主流技术中的两种。 前 者通过向单晶硅圆片中注入高剂量氧离子， 高温退火后形成隐埋绝缘 Si〇2(BOX)层， 从而形 成 SOI结构。 后者是先将一片热氧化后的硅片和一片光片键合， 再背面减薄到所需要的厚度 形成 SOI结构。
SIMOX技术采用的是高能量 （20 ~ 300keV)、 大束流 （10'7 018cm-2) 的氧离子注入, 在硅片中一定深度形成氧的富集区域， 再经过高温退火后形成掩埋在硅中的 Si〇2， 即 BOX 层。这一工艺形成的 SOI圆片， 受到注入能量和剂量的限制， BOX以及顶层硅的厚度可以调 节的范围十分有限， 很不炅活。 BOX最大厚度很难超过 400nm , 顶层硅的最大厚度也仅大 约为 300nm左右。并且 SIMOX工艺是利用高温退火，促进氧在硅的内部聚集成核形成 BOX 层， 这就使得 BOX的绝缘性能不如热氧化形成的 Si〇2。这些缺点限制了 SIMOX技术在厚埋 层(>400|"^)以及厚的顶层硅(>300nm)方面的应用。
键合减薄工艺是将一片表面带有热氧化层的硅片和另一片光片键合， 并将硅片背面减薄 至需要的厚度。这一工艺生产的 S〇l圆片，虽然 BOX的质量可以得到较好的保证，但是顶层 硅的厚度很难得到精确的控制。丄 W. Neuner采用等离子辅助化学腐蚀的办法， 可以将顶层 硅减薄到 Ι μηι ,平整度控制在 ±0.1 μηη的范围内。 (J.W. Neuner, A.M. Ledger, S. . Schilb, and D.P.Mathur, Improved Uniformity in Bonded SOI wafers with Active Layers from 1†o 30μιη a† High Throu†hpu†s, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, p.169-170) 但是要进一步通过研磨或腐蚀的办法减薄顶层硅，达到更小的厚度和 平整度， 难度就更大了。 这些缺点也限制了键合减薄工艺在均匀性要求高的方面的应用。
在传统键合减薄工艺的基础上， SOITEC公司引入 Unibond技术。 这种技术的关键步骤 之一是通过氢离子注入工艺形成气泡层 (Bubble Layer) , 该层在后续的退火工艺中自动裂开 (Split) , 从而利用裂开层较为精确的控制了拋光前的 SOI层均匀性， 最终实现了精确控制顶
确认本 层硅的厚度。 发明内容
本发明提出了一种离子注入结合键合减薄制备 SOI圆片的生产工艺。 注入工艺的优点在 于顶层硅薄而且均匀性控制很好， 而键合减薄工艺的优点是 BOX厚度可以在大范围内调节， 而且绝缘性能好。 本发明通过两种工艺的结合， 扬长避短， 发挥了二者的优势， 可以用来制 备埋层厚度可以调节， 同时又能保证顶层硅厚度均匀性的高质量的 SOI圆片。
本发明包括如下步骤： 首先利用离子注入工艺形成器件片 （如果希望最终产品的顶层硅 比较厚，则需对离子注入片进行外延或在最后工艺完成后对顶层硅实行外延，仍称为器件片）， 将器件片 （或含氧化层的器件片） 和支撑片 （或氧化支撑片） 键合， 并在含氧气或水蒸汽气 氛中退火加固， 再采用研磨加腐蚀的方法腐蚀至器件片的注入层， 即自停止层， 最后腐蚀去 除自停止层并对顶层硅进行精细研磨或氧化处理， 形成最终的 SOI 圆片。 最终产品的 BOX 和顶层硅的厚度分别由氧化层厚度和器件片的注入深度 （或外延厚度） 决定。
具体地说， 本发明所述的一种绝缘体上的硅的制备方法， 包括以下步骤：
(1 ) 离子注入： 选用相应的离子注入工艺在半导体材料中注入一层离子；
(2)将离子注入片进行后续高温处理， 形成后续腐蚀工艺时的自停止层；
(3)直接采用注入并后续处理后的片子作为器件片， 或外延该片作为器件片 （Device Wafer)；
(4)根据对埋层（绝缘层）厚度的要求，对器件片或支撑片选择适当的工艺参数进行适当 的绝缘层化处理；
(5)将上述器件片和支撑片进行键合
(6)对键合片进行退火加固处理；
(7)单面背面研磨器件片减薄器件片到一定厚度；
(8)采用腐蚀方法至器件片的离子注入层完全暴露；
(9) 除去离子注入层；
(10) 对剩余顶层硅精细拋光或氧化处理调节最终顶层硅的厚度。
所述的半导体材料为硅、 砷化镓， 磷化铟或 Ge中一种
所述的器件片是采用离子注入工艺制备的。所注入的离子可以选择 N离子、 O离子、或 其他离子； 选择离子的基本原则是该离子注入层可作为化学腐蚀阻挡层。 常用的离子为氧离 子。
所述的离子注入能量在 l OKeV到 500KeV间，离子注入剂量在 1 E15/cm2到 l E19/cm2 间；
所述的优化的离子注入能量在 70KeV到 250KeV间， 离子注入剂量在 5E1 0/ cm2到 2E18/ CIT12间； 注入的浓度在 500- 10000A之间； 注入的温度为 20- 70CTC ; 可采用单温度或 多步多温度的复合注入。
所述的离子注入可选用比较成熟的 SIM〇X(Separa†ion- by-Oxygen Implantation)氧 离子注入机， 采用 SIMOX注入工艺。 所述的 SIMOX工艺， 优化的氧离子注入能量在 30KeV到 250KeV间， 离子注入剂量在 5E10/cm2到 2E18/CID2间； 优化的氧离子注入能量在 70-250KeV之间， 离子注入剂量在 5E16/cm2到 7E17/cm2间， 优化的注入深度为 1000-5000埃之间， 注入温度 20-550Ό。
所述的器件片可经过后续处理（包括高温退火处理），处理的目的是使注入层与非注入层 界面比较陡峭， 使化学腐蚀易在界面出停止。
所述的对器件片的后续高溫处理温度在摄氏 600度到摄氏 1500度间，升降温速率均为 0. 5-10 °C/分钟； 气氛为氧氩或氧氮混合气氛， 其中氧的含量为 0%到 100%间。
所述的器件片也可不经过后续处理， 但必须离子注入剂量较大， 不经后续高温处理就形 成可以阻挡特定化学腐蚀的阻挡层， 也即形成具有腐蚀自停止功能的腐蚀阻挡层；
所述的器件片的形成可将注入片高温退火处理后直接清除去掉表层的二氧化硅， 或不去 掉； 去掉高温退火处理后形成的二氧化硅， 可使用半导体工艺中成熟的稀释的 HF溶液； 不去 掉的二氧化硅将最终最为 S0I圆片的 3102埋层的一部分。
所述的对器件片的后续高温处理，优化的温度在摄氏 1 100度到摄氏 1350度间，优化的 氧含量为 0%到 60%间。
所述的腐蚀工艺可以是化学腐蚀， 也可以是等离子刻蚀或其它任何可以在离子注入层停 止住的腐蚀方法。
可以根据对最终产品对顶层硅厚度的要求， 或先去掉表层的二氧化硅， 采用外延后的方 法， 生长确定厚度的外延层，， 即在原始离子注入片的顶层硅上生长外延层。外延工艺可采用 通常半导体工业中普遍采用的常规工艺。 外延可为同质外延， 也可为异质外延。 外延层可为 P型或 N型， 可掺硼或磷， 以及其他掺杂剂。
所述的绝缘化处理或氧化处理后的绝缘层将为最终 SOI圆片的埋层；
所述的绝缘层可为二氧化硅 (Si〇2) ,氮化硅 (Si3N4)或其它具有绝缘性的物质，绝缘化处理可在 器件片或支撑片上分开单独进行， 或两者同时进行。
所述的绝缘层化处理即是指生长绝缘层的方法， 如生长 Si〇2的氧化方法， 或者 Si3N4的 氮化方法， 常用的绝缘层为 Si〇2, 处理后的绝缘层为最终 SOI圆片的埋层； 氧化处理的厚度 在 0. 1-5μ间； 器件片和支撑片氧化层厚度的总和将为最终的 S0I圆片的厚度。
所述的对硅片的氧化工艺可采用集成电路中成熟的氧化制备工艺， 如干氧氧化工艺或干 氧-湿氧-干氧工艺。
所述的氧化的硅片可选择器件片或者支撑片。
所述的常用的绝缘层为 Si02.
采用键合工艺将器件片和支撑片键合。
所述的键合工艺可以采用 EVG公司的 EVG键合机， 也可以采用其他公司的键合机。 键 合一般在室温下进行， 也可采用等离子体辅助室温键合。
所述的退火加固时退火气氛可为含氧气氛， 可为干氧、 湿氧或混合气体。
所述的退火加固的温度为摄氏 200度以上摄氏 1400度以下， 时间为半小时至 15小时。 所述的优化的退化温度为摄氏 1000 250度， 气氛为湿氧， 时间为 2小时 ~ό小时。 所述的单面减薄可采用磨片机或其他能够减薄硅片的设备。 减薄到一定厚度范围为 l unn~100um。
所述的优化的减薄到的厚度为 3um〜30um
所述的的腐蚀方法必须使被腐蚀材料和离子注入层的腐蚀比足够大， 从而实现在离子注 入层的自停止。
所述的化学腐蚀硅的腐蚀液为氢氧化钾 （KOH) 或四甲基氢氧化铵 （THMA) 或其他对 离子注入层和硅具有较大的选择腐蚀比的化学剂。
腐蚀硅时一般选择稀释的氢氧化钾 （KOH) 或四甲基氢氧化铵 （THMA)。 腐蚀液的配比 —般在 1 :1000 (化学剂:去离子水)， 腐蚀时需加热， 一般温度在摄氏 25度到摄氏 200度间。
所述的优化的腐蚀液的配比一般在 1 : 1到 1： 100 (化学剂:去离子水)；优化的腐蚀温度在 摄氏 50度到摄氏 150度间。
所述的除去离子注入层可选用腐蚀方法， 也可直接采用抛光等方法
选择恰当的化学腐蚀剂来腐蚀掉离子注入层时，如果离子注入层为 Si02, 则化学腐蚀可采用 HF溶液。
所述的 HF溶液， 浓度范围可在 1 : 1至 1： 2000间调节。
所述的优化的 HF溶液浓度比例为 1 : 10至 1 : 100。
顶层精细抛光可选用化学机械抛光机或氧化来调节最终 SOI圆片顶层硅的厚度， 同时使 表面更光滑；一般化学机械拋光除去的厚度在 300- 5000A之间， 常用的化学机械拋光去除的 厚度在 300-3000A之间；采用氧化处理的硅层厚度在 300-10000A之间，常用的是 300- 5000A 之间
注入工艺生产的注入片， 可以得到纳米量级的顶层硅， 最小可达到 30nm， 而且厚度均 匀性可以在较小的范围 （± 10nm) 内自由调节， 这是采用单一的键合减薄等工艺达不到的 厚度和均匀性。而采用单一键合减薄的方法生产的 SOI圆片， BOX层是采用热氧化的办法制 备的， 这使得其厚度可以在比较大的范围内调节。
本发明将两种工艺的优势妙地结合在一起， 互相弥补， 发挥了各自的优点而克服了各自 的缺点。采用本发明制备的 SOI圆片， BOX采用热氧化方法制备， 绝缘性能良好，厚度均匀 可调 (厚度可在 0~5.0μηη间调整)；而顶层硅是从注入片或外延注入片上 "移植"过来的， 注 入片的注入层的自停止作用， 有效地保障了在最终精细拋光前顶层硅的厚度和均匀性 （拋光 前的厚度均匀性可达到 ± 10nm) , 而最终 SOI层厚度的均匀性在 ± 0.05μΐη以内。 附图说明
图 1、 依本发明提供的制备 SOI的第一种工艺流程
(a)离子注入
(b) 高温退火处理形成腐蚀自停止层
(c)形成器件片
(d)氧化支撑片
(e)键合器件片和支撑片
(f)氧化加固键合片 (g)单面背面研磨器件片减薄器件片到一定厚度
()采用腐蚀方法至器件片的离子注入层完全暴露
0)除去离子注入层
ω对剩余顶层硅精细抛光形成最终的 soi片
图 2、 依本发明提供的制备 SOI的第二种工艺流程
(a)离子注入
(b)高温退火处理形成腐蚀自停止层
(c)去掉高温退火在表面形成的氧化层
(d)外延器件片
(e)氧化支撑片
(f)氧化外延后的器件片
(g)键合器件片和支撑片
(h)氧化加固键合片
(i)单面背面研磨器件片减薄器件片到一定厚度
ω采用腐蚀方法至器件片的离子注入层完全暴露
(k)除去离子注入层
(1)对剩余顶层硅精细抛光形成最终的 SOI片
图 3、 实施例 1的 SOI层厚度和均匀性测试结果
图 4、 实施例 2的 SOI层厚度和均匀性测试结果 具体实施方式
下面的两个具体实施例有助于理解本发明的特征和优点， 但本发明的实施并不仅局限于 此实施例。
实施例 1
步骤 1: 在原始抛光片 10中注入氧离子， 能量为 190KeV,剂量为 3.0E17/cm2, 注入温度为 300度,注入层标记为 11;
步骤 2: 将注入片， 氧的比例为 0.5%在高温下退火。 退火温度为摄氏 1330度， 退火气氛为 含氧的氩气；
步骤 3: 得到的具有腐蚀停止层的 10片， 表层硅厚度约 230±5nm, 埋层厚度约 90±5nm， 表层 Si〇2的厚度为 400±5nm.注入层 11变成了腐蚀停止层 12 (即埋氧层） .标记表层硅 为 13， 表层 Si〇2标记为 14;
步骤 4: 将硅片 20氧化， 氧化层厚度约为 000±5nm， 标记为 21
步骤 5: 将硅片 10和 20键合并退火后加固。退火温度为摄氏 1150度， 水汽氧化， 时间为 3 个小时；
步骤 0: 将加固后的 10片背面用磨片机减薄， 剰余厚度约为 15微米， 标记为 15。
步骤 7: 将减薄后的片子用 KOH腐蚀， 腐蚀液浓度为质量比 1:20 (去离子水: K〇H)， 温度为 摄氏 70度， 约 25分钟， 去除掉 15 步骤 8: 将去除掉 15后的片子放放在 1 :10 HF中约漂洗 30秒钟， 去除掉 12;
步骤 9: 在实施 8后， 用化学机械抛光机抛掉约 50nm, 剩余的 SOI层厚度为 10;
基于以上实施后， 得到最终的 SOI圆片， 参数如下： SOI层 16的厚度 195.3nm， 均匀性为
±2.7nm; 埋层厚度为， 为 14加上 21, 总厚度为 1000± 10nm。 图 3给出了 SOI层厚度的 均匀性测试数据。 实施例 2、
步骤 1: 在原始抛光片 10中注入氧离子， 能量为 190KeV,剂量为 2.5E17/cm2， 注入温度为 300度,注入层标记为 11;
步骤 2: 将注入片在高温下退火。 退火温度为摄氏 1330度， 退火气氛为含氧的氩气； 步骤 3:得到的具有腐蚀停止层的 10片，表层硅厚度约 250±5nm,埋层厚度约 80± 10nm， 表层 Si〇2的厚度为 400±5nm. 注入层 11变成了腐蚀停止层 12 (即埋氧层） .标记表层硅 为 13, 表层 Si〇2标记为 14;
步骤 4: 将 10片清洗并去除表层 Si〇214,然后采用外延工艺， 外延层的厚度为 1.40um, 标 记为 31。
步骤 5:将外延后的 10片氧化，氧化温度为 1000度，氧化层厚度为 200nm±10nm,标记为 17.
步骤 0: 将硅片 20氧化， 氧化层厚度约为 800±5nm， 标记为 21
步骤 7:将硅片 10和 20键合并退火后加固。退火温度为摄氏 1150度，水汽氧化， 时间为 3 个小时；
步骤 8: 将加固后的 10片背面用磨片机减薄， 剩余厚度约为 15微米, 标记为 15。
步骤 9: 将减薄后的片子用 KOH腐蚀， 腐蚀液浓度为质量比 1:20 (去离子水: K〇H)， 温度为 摄氏 70度， 约 25分钟， 去除掉 15
步骤 10: 将去除掉 15后的片子放在 1:10HF中约漂洗 30秒钟， 去除掉 12;
步骤 11: 在实施 8后， 用化学机械拋光机抛掉约 lOOnm, 剩余的 SOI层标记为 18
基于以上实施后， 得到最终的 SOI圆片， 参数如下： SOI层厚度 1.548um， 均匀性为 ±21.5nm; 埋层厚度为 1000±10nm, 为 17加上 21， 总厚度为 1000±10nm。 图 4给出 了 SOI层厚度的均匀性测试数据。

Claims

权利要求
Is一种绝缘体上硅的制作方法，特征在于首先利用离子注入工艺形成器件片或对离子注入片 进行外延或在最后工艺完成后对顶层硅实行外延后形成器件片， 然后将器件片或氧化后的器 件片和支撑片或氧化支撑片键合， 并退火加固， 再采用研磨加腐蚀的方法腐蚀至器件片的注 入层， 腐蚀去除自停止层， 并对顶层硅进行精细研磨或氧化处理， 形成最终的 SOI圆片； 最 终产品的埋层绝缘层和顶层硅的厚度分别由氧化层厚度和器件片的注入深度或外延厚度决 定。
2、 按权利要求 1所述的绝缘体上硅的制作方法， 其特征在于具体包括以下步骤：
(1 ) 离子注入： 在半导体材料中注入一层离子;所述的半导体材料为硅、砷化镓， 磷化铟 或 Ge中一种；
(2) 将离子注入片进行后续高温处理， 形成后续腐蚀工艺时的自停止层；
(3) 直接采用注入并后续处理后的片子作为器件片或外延该片作为器件片；
(4) 根据对埋层绝缘层厚度的要求， 对器件片或支撑片进行高温退火、 腐蚀或外延生 长方法进行绝缘层化处理； 其中， 高温处理 600-1500°C , 气氛为氧氩或氧氮混合 气体； 腐蚀包括化学腐蚀或等离子刻蚀；；
(5) 将上述器件片和支撑片进行键合
(6) 对键合片进行退火加固处理； 退火加固温度 500-1400°C , 时间 0.5-15h; 气氛为干 氧、 湿氧或含氧的混合气体；
(7) 单面背面研磨器件片减薄器件片到 1-100μ ;
(8) 采用腐蚀方法至器件片的离子注入层完全暴露；
(9) 采用腐蚀或抛光方法除去离子注入层；
(10) 对剩余顶层硅采用化学机械抛光机精细抛光或氧化处理。
3、 按权利要求 1或 2所述的绝缘体上硅的制作方法， 其特征在于离子注入能量在 lOKeV到 500KeV间， 离子注入剂量在 lE15/cm2到 lE19/cm2间， 注入的深度在 500-10000 '之间， 注 入温度为 20-700°C之间。
4、 按权利要求 1或 2所述的绝缘体上硅的制作方法， 其特征在于离子注入能量在 70KeV到 250KeV间， 离子注入剂量在 5E16/cm2到 2E18/cm2间。
5、 按权利要求 1或 2所述的绝缘体上硅的制作方法， 其特征在于氧离子注入采用 SIMOX工 艺。
6、 按权利要求 3所述 的绝缘体上硅的制作方法， 其特征在于离子注入剂量在 5E16/cm2到 7E17/cm2间； 注入深度为 1000-5000埃之间； 注入温度为 20-550°C之间。
7、按权利要求 2所述的绝缘体上硅的制作方法，其特征在于所述的对器件片的后续处理温度 在 600°C度到 1500°C间， 气氛为氧氩或氧氮混合气氛， 其中氧的含量为 0-100%间。 8、 按权利要求 7所述的绝缘体上硅的制作方法，， 其特征在于所述的对器件片的后续高温处 理温度在 1100- 1350°C， 氧含量为 0%到 60%间。
9、按权利要求 2所述的绝缘体上硅的制作方法，其特征在于根据对最终产品对顶层硅厚度的 要求或先去掉表层的二氧化硅的方法， 生长确定厚度的外延层， 外延工艺为半导体工业中普 遍采用的常规工艺， 外延为同质外延； 外延层为 P型或 N型， 掺杂硼、 磷或其他惨杂剂。
10、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于， 在后续高温处理过程中， 升 温从室温到 1350度的升温速率为从 10度 /分钟到 0.5度 /分钟， 气氛为氧氩或氧氮混合气氛， 其中氧的含量为 0%到 100%间； 降温从 1350度到室温， 降温速率为从 10度 /分钟到 0.5度 / 分钟， 气氛为氧氩或氧氮混合气氛， 其中氧的含量为 0%到 100%间。
IK 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于注入后的后续高温退火过程既 可采用单步单升降温速率或多步多升降温速率的复合步骤和复合升降温来实现；
12、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于步骤 （1 ) 和 （2) 完成后， 离 子注入导致的腐蚀停止层的厚度为 200A到 5000A之间， 表面二氧化硅的厚度为 1000A到 15000A之间， 表层硅的厚度在 200A到 4000A之间；
13、按权利要求 2或 12所述的绝缘体上硅的制作方法，其特征在于步骤 ( 1 )和（2) 完成后， 离子注入导致的腐蚀停止层的厚度为 500A到 1500A之间， 表面的二氧化硅厚度在 1500A到 ιοοοοΑ之间；
14、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于器件片的形成可将注入片高温 退火处理后直接清洗去掉表层的二氧化硅，或不去掉；去掉高温退火处理后形成的二氧化硅， 采用半导体工艺中成熟的稀释的 HF溶液来去掉； 不去掉的二氧化硅将作为最终 SOI圆片的 51〇2埋层的一部分。
15、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于所述的绝缘化处理或氧化处理 是形成最终 SOI圆片的绝缘层， 绝缘层可为二氧化硅， 氮化硅或其它具有绝缘性的物质， 绝 缘化处理即是指生长绝缘层的方法， 如生长 Si〇2的氧化方法， 或者 Si3N4的氮化方法。
16、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于所述的绝缘化处理是在器件片 或支撑片上单独进行， 或在器件片和支撑片上同时进行。
17、按权利要求 15所述的绝缘体上硅的制作方法，其特征在于对硅片的氧化工艺是采用集成 电路中的干氧氧化工艺或干氧-湿氧-干氧工艺制备工艺。
18、 按权利要求 15所述的绝缘体上硅的制作方法， 其特征在于氧化处理的厚度在 0.1微米到 5微米之间。
19、按权利要求 2或 15所述的绝缘体上硅的制作方法，其特征在于器件片和支撑片氧化层厚 度的总和为最终的 SOI圆片的厚度。
20、 按权利要求 1或 2所述的绝缘体上硅的制作方法， 其特征在于退火加固的温度为 200°C 度到 1400°C间， 退火加固时退火气氛为含氧气氛、 干氧、 湿氧或混合气体； 时间为半小时至 15小时。 21 s按权利要求 20所述的绝缘体上硅的制作方法， 其特征在于优化的加固温度为 1000~1250 °C， 气氛为湿氧， 时间为 2小时 ~6小时。
22按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于采用磨片机或其他能够减薄硅片 的设备， 单面减薄， 减薄到的厚度范围为 lum~100um。
23、 按权利要求 22 所述的绝缘体上硅的制作方法， 其特征在于所述的减薄到的厚度为 3um~30umo
24、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于化学腐蚀硅的化学腐蚀液为氢 氧化钾、 四甲基氢氧化铵或其他对离子注入层和硅具有较大的选择腐蚀比的化学剂。
25、按权利要求 24所述的绝缘体上硅的制作方法，其特征在于稀释的氢氧化钾或四甲基氢氧 化铵的腐蚀液的配比是化学剂与去离子水之比在 1:1000 , 腐蚀的温度在 25-200°C间。
26、按权利要求 25所述的绝缘体上硅的制作方法，其特征在于腐蚀液的化学剂与去离子水之 比在 1:1到 1 : 100 ； 腐蚀温度在 50-150°C间。
27、按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于步骤 （9) 涉及的除去离子注入 层可选用腐蚀方法或直接采用拋光方法。
28、 按权利要求 2或 27所述的绝缘体上硅的制作方法， 其特征在于离子注入层为 Si02， 则 化学腐蚀采用 HF溶液； 浓度范围在 1:1至 1： 2000间调节。
29、 按权利要求 28所述的绝缘体上硅的制作方法， 其特征在于 HF溶液的浓度范围为 1 :10 至 1:100。
30、 按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于步骤 （10) 中所述的化学机械 抛光除去的厚度在 300埃至 50000埃之间， 以保证最后 SOI层厚度的均匀性。
31、 按权利要求 30 所述的绝缘体上硅的制作方法， 其特征在于化学机械抛光去除的厚度在 300至 3000埃之间。
32、按权利要求 2所述的绝缘体上硅的制作方法， 其特征在于步骤 (10) 中所述的氧化处理， 去除的硅层厚度在 300埃至 10000埃之间。
33、按权利要求 32所述的绝缘体上硅的制作方法，其特征在于采用氧化处理，去除的硅层厚 度在 300埃到 5000埃之间。
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