WO2007010646A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2007010646A1
WO2007010646A1 PCT/JP2006/305703 JP2006305703W WO2007010646A1 WO 2007010646 A1 WO2007010646 A1 WO 2007010646A1 JP 2006305703 W JP2006305703 W JP 2006305703W WO 2007010646 A1 WO2007010646 A1 WO 2007010646A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor element
base region
semiconductor
region
electrode
Prior art date
Application number
PCT/JP2006/305703
Other languages
English (en)
French (fr)
Inventor
Katsuyuki Torii
Original Assignee
Sanken Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Priority to US11/995,360 priority Critical patent/US8143645B2/en
Priority to CN200680025644XA priority patent/CN101223644B/zh
Priority to EP06729670A priority patent/EP1909329B1/en
Publication of WO2007010646A1 publication Critical patent/WO2007010646A1/ja

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Definitions

  • the present invention relates to a semiconductor device including a plurality of stacked semiconductor elements.
  • a stacked multi structure in which switching elements constituting a bridge circuit are stacked is applied to a semiconductor device.
  • a semiconductor device to which a stacked multi structure is applied is known, for example, from Patent Document 1 below.
  • an H-type bridge circuit using a power semiconductor element can be formed with an increased degree of integration while reducing the area occupied by the support plate.
  • MOSFET MOS field effect transistor
  • IGBTs insulated gate type bipolar transistors
  • a MOSFET is formed on a drain region (51) having an N-type conductivity type and on an upper surface (51a) having a P-type conductivity type and a drain region (51).
  • the IGBT is formed on the upper surface (61a) of the collector region (61) having the P-type conductivity type and the N-type conductivity type and the collector region (61).
  • the IGBT has a P-type conductivity type second base region (63), an N-type conductivity type first base region (62), and a P-type conductivity type.
  • a diode (69) is formed between the collector region (61) and the first base region (62) having the N-type conductivity, and diodes (69) having opposite polarities are connected in series. For this reason, it has been difficult to effectively use this diode as a protective built-in diode.
  • an H-bridge circuit or the like in which a load having an inductive component is connected to the output terminal, the back electromotive force generated by the inductive component of the load is easily applied to the IGBT. For this reason, it is necessary to connect a diode to each IGBT in parallel, and to reverse the reverse current (surge current) generated by the counter electromotive force via the diode.
  • Patent Document 2 a force sword region having the opposite conductivity type is formed on the center side of the collector region, and an anode region having a P-type conductivity type is formed above the force sword region.
  • an IGBT with a built-in diode According to the IGBT of Patent Document 2, an external diode can be omitted, and a stacked multi-structure semiconductor device in which IGBTs are stacked can be formed.
  • Patent Document 1 International Publication No. 2005Z018001
  • Patent Document 2 JP-A-9 191110
  • an object of the present invention is to provide a stacked multi-structure semiconductor device that is made smaller than before and is easy to produce by stacking IGBTs with built-in diodes. It is another object of the present invention to provide a semiconductor device that prevents heat generated by current from concentrating on the center side of the semiconductor substrate.
  • the semiconductor device of the present invention includes a first semiconductor element (1) and a second semiconductor element (2) stacked and fixed on the first semiconductor element (1).
  • Each of the first semiconductor element (1) and the second semiconductor element (2) includes: 1. a collector region (15) having a first conductivity type (P), opposite to the first conductivity type (P); A first base region (16) having the second conductivity type (N) and formed on the upper surface (15a) of the collector region (15), and having the first conductivity type (P) and the first base region A second base region (17) formed adjacent to (16), an emitter region (18) having the second conductivity type (N) and formed adjacent to the second base region (17)
  • a semiconductor substrate (31) comprising: 2.
  • a gate electrode (25) formed on an upper surface (17a) of the second base region (17) via an insulator (9); and 3. a second base region (17) and the emitter electrode (22) formed on the upper surface (17a, 18a) of the emitter region (18), and 4. the collector electrode (23) formed on the lower surface (15b) of the collector region (15) Is provided.
  • the first base region (16) has a peripheral portion (26) adjacent to the side surface (31c) of the semiconductor substrate (31), and the first semiconductor element (1) and the second semiconductor element (2) Includes a peripheral base region (27) having a first conductivity type (P) and forming a diode (21) adjacent to the peripheral portion (26) of the first base region (16), and the first base Diode electrode (24) formed on the upper surface (26a) of the peripheral part (26) of the region (16), and the diode electrodes (1) of the first semiconductor element (1) and the second semiconductor element (2) ( 24) and the collector electrode (23) are electrically connected to each other.
  • a peripheral base region (27) having a first conductivity type (P) and forming a diode (21) adjacent to the peripheral portion (26) of the first base region (16), and the first base Diode electrode (24) formed on the upper surface (26a) of the peripheral part (26) of the region (16), and the diode electrodes (1) of the first semiconductor element (1) and the second semiconductor element (2) ( 24) and the collector electrode (23) are electrical
  • the first semiconductor element (1) and the second semiconductor element (2) are formed by the back electromotive force caused by the inductive component of the connected load.
  • Emitter electrode (22) of device (2) Force Reverse electrode (surge current) induced in the reverse direction to collector electrode (23) is generated, but peripheral base region having first conductivity type (P) (27) And a peripheral portion (26) of the first base region (16) having the second conductivity type (N) to form a diode (21) and form a diode on the upper surface (26a) of the peripheral portion (26).
  • the reverse current is transferred to the peripheral base region (27), the peripheral portion (26) of the first base region (16), and It can flow to the collector electrode (23) through the diode electrode (24). Therefore, a semiconductor device that does not require an external diode to be connected to the semiconductor device can be formed in a small size.
  • FIG. 1 is a partially enlarged sectional view showing an embodiment of a semiconductor device according to the present invention.
  • the semiconductor device of the present embodiment includes a metal support plate (5) and a support plate (5) made of metal such as copper or aluminum having heat dissipation properties.
  • the semiconductor element stack (7) and the third IGBT (3) as the third semiconductor element and the fourth semiconductor element as the fourth semiconductor element are sequentially stacked and fixed on the support plate (5).
  • the H-type bridge circuit (10) shown in Fig. 4 is constructed.
  • a plurality of external leads (33) arranged around are connected by wires (lead fine wires) (29).
  • a load (6) which is a cold cathode fluorescent discharge tube, which is driven more, is connected.
  • the semiconductor device making up the H-type bridge circuit (10) is covered and integrated with the resin encapsulant (34), but the external lead (33) is led out to the resin encapsulant (34). Is done.
  • a load (6) is connected to a part of the external lead (33).
  • One of the IGBT (3) and the fourth IGBT (4) constitutes the no-side switch of the H-type bridge circuit (10)
  • the first semiconductor element stack (7) constitutes the first semiconductor element stack (7).
  • the other of the IGBT (l) and the second IGBT (2) and the other of the third IGBT (3) and the fourth IGBT (4) constituting the second semiconductor element stack (8) are H-shaped. Bridge times Configure the low side switch of the road (10).
  • the second IGBT (2) and the fourth IGBT (4) on the low side are placed on the first IGBT (l) and the third IGBT (3) on the high side.
  • the first and second semiconductor element stacks (7, 8) are configured to be attached, and the control is provided between the first semiconductor element stack (7) and the second semiconductor element stack (8).
  • the element (13) is fixed on a single support plate (5) by an adhesive (32) made of solder, brazing material or silver paste.
  • the second IGBT (2) and the fourth IGBT (4) are, in plan view, the upper surfaces (la, 3a) of the first IGBT (l) and the third IGBT (3) and The upper surface (2a, 4a) and the lower surface (2b, 4b) have a smaller area than the lower surface (lb, 3b). As shown in FIG.
  • each of the first IGBT (l) to the fourth IGBT (4) includes a semiconductor substrate (31) having a silicon single crystal isotropic force as a semiconductor substrate, and each semiconductor substrate (31) A collector region (15) having a P-type conductivity type as a first conductivity type, and an N-type conductivity type as a second conductivity type opposite to the P-type conductivity type and an upper surface of the collector region (15) ( A first base region (16) formed in 15a) and a second base region having a P-type conductivity and formed on the upper surface (16a) side adjacent to the first base region (16) (17) and an emitter region (18) having an N-type conductivity and formed on the upper surface (17a) side adjacent to the second base region (17).
  • the first IGBT (l) to the fourth IGBT (4) are formed on the upper surface (17a) of the second base region (17) via a gate insulating film (9) as an insulator.
  • Gate electrode (control electrode) (25) formed on the upper surface (17a, 18a) of the second base region (17) and the emitter region (18) (upper surface electrode) (22), And a collector electrode (bottom electrode) (23) formed on the lower surface (15b) of the collector region (15).
  • a known channel region is formed.
  • the second base region (17) is arranged in parallel in a lattice shape or a stripe shape in the first base region (16) with respect to the planar direction of the semiconductor substrate (31).
  • the emitter region (18) is disposed so as to oppose each other along the edge of the second base region (17).
  • the gate electrode (25) is formed in a stripe shape between the second base regions (17) so as to straddle the adjacent second base regions (17).
  • a cell (30) which is the minimum unit of the active region of the semiconductor element is formed.
  • the second base region (17) is shaped like an island within the first base region (16). You may make it.
  • a gate bus line electrically connected to the gate electrode (25) is formed on the upper surface (31a) of the semiconductor substrate (31) along the peripheral surface of the semiconductor substrate (31).
  • the gate bus line is formed of a conductive metal such as aluminum, covers an extended portion of the gate electrode (25) formed in a stripe shape, and is electrically connected to the gate electrode (25).
  • the conductive adhesive (32) electrically connects the emitter electrode (22) of the first IGBT (l) and the collector electrode (23) of the second IGBT (2), so that the first The emitter electrode (22) of the third IGBT (3) and the collector electrode (23) of the fourth IGBT (4) are electrically connected.
  • the gate insulating film (9) is made of, for example, silicon dioxide, and a gate electrode (25) made of, for example, polysilicon is formed on the upper surface of the gate insulating film (9).
  • an interlayer insulating film (19) having, for example, silicon dioxide or silicon force, which electrically insulates the gate electrode (25) and the emitter electrode (22) is formed around the gate electrode (25).
  • the emitter electrode (22) and the collector electrode (23) are formed of, for example, aluminum or a laminate in which aluminum and nickel are laminated.
  • the first base region (16) of each IGBT (1, 2, 3, 4) has a peripheral portion (26) adjacent to the side surface (31c) of the semiconductor substrate (31). And a side surface (31c) of the semiconductor substrate (31) by a peripheral base region (27) having a P-type conductivity formed adjacent to the peripheral portion (26) of the first base region (16).
  • a diode (21) is formed in the vicinity of.
  • the second base region (17) and the emitter region (18) are formed on the element center side with two side surface (3 lc) forces forming one corner of the semiconductor substrate (31) being separated from each other.
  • each IGBT (1, 2, 3, 4) shown in FIG. 1 includes an annular peripheral portion (26) formed on the side surface (31c) side of the semiconductor substrate (31) and the peripheral portion (26).
  • a diode (21) is formed in the peripheral part (26), and a cell (30) is formed in the central part.
  • the peripheral base region (27) can be formed together with the second base region (17) by diffusing impurities such as boron into the upper surface (31a) of the semiconductor substrate (31). Therefore, the peripheral base region (27) can be formed by the same manufacturing process as the existing one without increasing the manufacturing cost.
  • the force that forms the emitter region (18) in the peripheral base region (27) on the side facing the second base region (17) includes the emitter region in the peripheral base region (27). (18) may not be formed [0022]
  • a diode electrode (24) formed on the upper surface (26a) of the peripheral portion (26) of the first base region (16) is provided.
  • the gate electrode (25) and the emitter electrode (22) are formed by separating the two side surface (31c) forces of the semiconductor substrate (31), whereas the diode electrode (24) is a semiconductor. It is formed adjacent to the two side surfaces (31c) of the substrate (31).
  • a gap (20) is formed between the diode electrode (24) and the emitter electrode (22), and the diode electrode (24) and the emitter electrode (22) are electrically separated.
  • an insulating film (not shown) consisting of silicon dioxide and silicon force is formed between the diode electrode (24) and the emitter electrode (22). May be.
  • the insulating film can be formed together with the interlayer insulating film (19) during the step of forming the interlayer insulating film (19).
  • the diode electrode (24) is made of, for example, the same aluminum or silicon-containing aluminum having high adhesion to the aluminum forming the wire (28).
  • the diode electrode (24) has a flat upper surface (24a), and a support plate (5) or external lead (33) whose upper surface is similarly formed flat by a well-known wire bonding method. Connected by wire (28).
  • the process of connecting the diode electrode (24) and the external lead (33) with the wire (28) is performed by the top electrode of the first IGBT (l) to the fourth IGBT (4) and the control element (13). Since the same process as the process of connecting the upper electrode or the external lead (33) to the wire (29) can be performed, the manufacturing cost does not increase and the semiconductor device can be manufactured by the same manufacturing process as the existing one.
  • the diode electrode (24) and the collector electrode (23) of the first IGBT (l) to the fourth IGBT (4) are electrically connected to each other, as shown in FIG.
  • a diode is connected in parallel between the emitter and collector of the IGBT (1,2,3,4).
  • the first IGBT (l) and the third IGBT (3) that make up the non-side switch connect the external lead (33) connected to the positive terminal and the diode electrode (24) with a wire (28).
  • the diode electrode (24) and the collector electrode (23) are electrically connected through another external lead (33) connected to the positive terminal and the support plate (5).
  • the second IGBT (2) and the fourth IGBT (4) that make up the low-side switch are connected at the connection point (A, ⁇ ).
  • the pole (24) and the collector electrode (23) are electrically connected.
  • the first IGBT (l) to the fourth IGBT (4) include a load (6) connected to the H-type bridge circuit (10).
  • the back electromotive force due to the inductive component generates a reverse current (surge current) that is induced in the reverse direction to the emitter electrode (22) force collector electrode (23) of each IGBT (1,2,3,4).
  • a diode (21) is formed by the peripheral base region (27) having the P-type conductivity type and the peripheral portion (26) of the first base region (16) having the N-type conductivity type.
  • the semiconductor device constituting the H-type bridge circuit (10) that does not require the connection of an external diode to the semiconductor device can be formed in a small size.
  • the H-type bridge circuit (10) When the H-type bridge circuit (10) is operated, the first IGBT (l) and the fourth IGBT (4), and the second IGBT (2) and the third IGBT are controlled by the control element (13). By switching the IGBT (3) on and off alternately and switching the current, the reverse current (I) is alternately connected between the connection points (A) and (A).
  • Is turned on, the second IGBT (2) and the third IGBT (3) are turned off, and a one-way current (I) flows through the load (6), and then the first IGBT (l) and the second IGBT 4 IGBT (4) is switched off,
  • the unidirectional current (I) is the first
  • the current (I) in the other direction flows through the IGBT (1), the fourth IGBT (4) and the support plate (5).
  • the side (31c) force of the conductive substrate (31) is also released to the outside.
  • the H-type bridge circuit (10) shown in the figure when the first IGBT (l) and the fourth IGBT (4) are turned on and the second IGBT (2) and the third IGBT (3) are turned off. A current flows through the center of the semiconductor substrate (31) constituting the first IGBT (l) and the fourth IGBT (4).
  • the second IGBT (2) and the third IGBT (3) are turned on and the first IGBT (l) and the fourth IGBT (4) are turned off, the first IGBT (l ) And the fourth I GBT (4) is applied with a reverse voltage.
  • the surge current based on this reverse voltage is the force that flows by bypassing the diode (21) built in the semiconductor substrate (31) constituting the first IGBT (l) and the fourth IGBT (4). As described above, it flows close to the side surface (31c) of the semiconductor substrate (31).
  • the peripheral base region (27) is formed in the corner portion of the semiconductor substrate (31), but may be formed in the vicinity of the side surface (31c) separated from the corner portion.
  • the present invention relates to a semiconductor device comprising a semiconductor device formed by stacking a plurality of semiconductor elements, an H-bridge circuit (full-bridge circuit) used in a cold cathode fluorescent tube driving device, and the like. It can be applied well to the device.
  • H-bridge circuit full-bridge circuit

Abstract

　外付けダイオードを接続せずに半導体装置を小型化すると共に、電流により生じる熱が半導体基体の中央側に集中することを防止する。順次に積層された第１のＩＧＢＴ(1)及び第２のＩＧＢＴ(2)の第１のベース領域(16)は、各半導体基体(31)の側面(31c)に近接する周辺部(26)を有する。各ＩＧＢＴ(1,2)は、Ｎ型の第１のベース領域(16)の周辺部(26)に隣接してダイオード(21)を形成するＰ型の周辺ベース領域(27)と、第１のベース領域(16)の周辺部(26)の上面(26a)に形成されたダイオード電極(24)とを備え、各ＩＧＢＴ(1,2)のダイオード電極(24)とコレクタ電極(23)とを電気的に接続する。半導体装置のオン時には、側面(31c)から離間した半導体基体(31)の中央側に電流が流れるが、半導体装置のオフ時に逆方向電流が発生したとき、逆方向電流が半導体基体(31)の側面(31c)に近接して流れる。

Description

明 細 書
半導体装置
技術分野
[0001] 積層した複数の半導体素子を備える半導体装置に関する。
背景技術
[0002] 近年の電子部品の小型化に対応する一手段として、ブリッジ回路を構成するスイツ チング素子を積層したスタックドマルチ構造が半導体装置に適用されて 、る。スタック ドマルチ構造を適用した半導体装置は、例えば下記特許文献 1により公知である。特 許文献 1に示す半導体装置によれば、パワー半導体素子を用いた H型ブリッジ回路 を支持板の占有面積を減少しつつ集積度を向上して形成できる。し力しながら、積層 するパワー半導体素子に MOSFET(MOS型電界効果トランジスタ）を用いると、チ ップサイズが大きくなり、小型化が達成できない。そのため、チップサイズを小さく形 成できる IGBT (絶縁ゲート型ノイポーラトランジスタ）が用いられていた。しかしなが ら、 IGBTを使用すると、同時に外付けのダイオードも H型ブリッジ回路に組み込まな ければならず、結果的に小型化が達成できな力つた。また、外付けのダイオードによ り製品コストが増カロした。
[0003] 一般的に MOSFETは、例えば図 5に示すように、 N型導電型を有するドレイン領 域 (51)、 P型導電型を有し且つドレイン領域 (51)の上面 (51a)に形成されたベース領域 (52)、 N型導電型を有し且つベース領域 (52)の上面 (52a)に形成されたソース領域 (53) を備える半導体基板 (50)と、ゲート絶縁膜 (54)を介してソース領域 (53)の上面 (53a)に 形成されたゲート電極 (55)と、ベース領域 (52)及びソース領域 (53)の上面 (52a,53a)に 形成されたソース電極 (56)と、ドレイン領域 (51)の下面 (51b)に形成されたドレイン電極 (57)とを備える。よって、 P型導電型を有するベース領域 (52)と N型導電型を有するド レイン領域 (51)との間にダイオード (58)が形成され、これを保護用の内蔵ダイオードと して禾 lj用でさる。
[0004] これに対し、 IGBTは、図 6に示すように、 P型導電型を有するコレクタ領域 (61)、 N 型導電型を有し且つコレクタ領域 (61)の上面 (61a)に形成された第 1のベース領域 (62 )、P型導電型を有し且つ第 1のベース領域 (62)の上面 (62a)に形成された第 2のべ一 ス領域 (63)、 N型導電型を有し且つ第 2のベース領域 (63)の上面 (63a)に形成された ェミッタ領域 (64)を備える半導体基板 (60)と、ゲート絶縁膜 (65)を介して第 2のベース 領域 (63)の上面 (63a)に形成されたゲート電極 (66)と、第 2のベース領域 (63)及びエミ ッタ領域 (64)の上面 (63a,64a)に形成されたェミッタ電極 (67)と、コレクタ領域 (61)の下 面 (61b)に形成されたコレクタ電極 (68)とを備える。よって、 IGBTでは、図 6に示すよう に、 P型導電型を有する第 2のベース領域 (63)と N型導電型を有する第 1のベース領 域 (62)と、 P型導電型を有するコレクタ領域 (61)と N型導電型を有する第 1のベース領 域 (62)との間にそれぞれダイオード (69)が形成され、逆極性のダイオード (69)が直列 接続される。このため、このダイオードを保護用の内蔵ダイオードとして有効利用する ことが困難であった。出力端子に誘導成分を有する負荷を接続した Hブリッジ回路等 では、 IGBTに負荷の誘導成分により発生した逆起電力が印加され易い。このため、 各 IGBTにダイオードを並列に接続して、逆起電力により発生した逆方向電流 (サー ジ電流）をダイオードを介してバイノスさせる必要がある。
[0005] 下記特許文献 2は、コレクタ領域の中央側にこれと反対導電型の力ソード領域を形 成すると共に、力ソード領域の上方に P型導電型を有するアノード領域を形成し、こ れによりダイオードを内蔵した IGBTを開示する。特許文献 2の IGBTによれば、外付 けダイオードを省略して、 IGBTを積層したスタックドマルチ構造の半導体装置を形 成することができる。
[0006] 特許文献 1：国際公開第 2005Z018001号公報
特許文献 2：特開平 9 191110号公報
発明の開示
発明が解決しょうとする課題
[0007] し力しながら、特許文献 2の IGBTでは、平面方向に対して半導体基板の同位置に アノード領域と力ソード領域とを重ねて形成しなければならないため、両半導体領域 の位置決めが難しぐ生産性の点で問題があった。また、 IGBTのオン時には、半導 体基板の中央側のセル領域に電流が流れるが、半導体装置のオフ時に逆方向電流 が発生したときにも、この逆方向電流が半導体基板の中央側を流れるため、電流に より発生する熱が半導体基板の中央側に集中して、半導体基板の電気的特性が劣 ィ匕するおそれがあった。
よって、本発明は、ダイオードを内蔵した IGBTを積層して、従来より小型化され、 且つ生産も容易なスタックドマルチ構造の半導体装置を提供することを目的とする。 また、電流により発生する熱が半導体基板の中央側に集中することを防止した半導 体装置を提供することを目的とする。
課題を解決するための手段
[0008] 本発明の半導体装置は、第 1の半導体素子 (1)と、第 1の半導体素子 (1)上に積層さ れて固着された第 2の半導体素子 (2)とを備える。第 1の半導体素子 (1)及び第 2の半 導体素子 (2)の各々は、 1.第 1導電型 (P)を有するコレクタ領域 (15)、第 1導電型 (P)と は反対の第 2導電型 (N)を有し且つコレクタ領域 (15)の上面 (15a)に形成された第 1の ベース領域 (16)、第 1導電型 (P)を有し且つ第 1のベース領域 (16)に隣接して形成され た第 2のベース領域 (17)、第 2導電型 (N)を有し且つ第 2のベース領域 (17)に隣接して 形成されたェミッタ領域 (18)を備える半導体基体 (31)と、 2.絶縁体 (9)を介して第 2の ベース領域 (17)の上面 (17a)に形成されたゲート電極 (25)と、 3.第 2のベース領域 (17) 及びェミッタ領域 (18)の上面 (17a,18a)に形成されたェミッタ電極 (22)と、 4.コレクタ領 域 (15)の下面 (15b)に形成されたコレクタ電極 (23)とを備える。第 1のベース領域 (16)は 、半導体基体 (31)の側面 (31c)に近接する周辺部 (26)を有し、第 1の半導体素子 (1)及 び第 2の半導体素子 (2)は、第 1導電型 (P)を有し且つ第 1のベース領域 (16)の周辺部 (26)に隣接してダイオード (21)を形成する周辺ベース領域 (27)と、第 1のベース領域 (1 6)の周辺部 (26)の上面 (26a)に形成されたダイオード電極 (24)とを備え、第 1の半導体 素子 (1)及び第 2の半導体素子 (2)のダイオード電極 (24)とコレクタ電極 (23)とをそれぞ れ電気的に接続する。
[0009] 第 1の半導体素子 (1)及び第 2の半導体素子 (2)は、接続される負荷の誘導成分によ る逆起電力により、第 1の半導体素子 (1)及び第 2の半導体素子 (2)のェミッタ電極 (22) 力 コレクタ電極 (23)へ逆方向に誘起される逆方向電流 (サージ電流）が発生するが 、第 1導電型 (P)を有する周辺ベース領域 (27)と第 2導電型 (N)を有する第 1のベース 領域 (16)の周辺部 (26)とによりダイオード (21)を形成し、周辺部 (26)の上面 (26a)に形 成されたダイオード電極 (24)とコレクタ電極 (23)とを電気的に接続することによって、 逆方向電流を周辺ベース領域 (27)、第 1のベース領域 (16)の周辺部 (26)及びダイォ ード電極 (24)を通じてコレクタ電極 (23)に流すことができる。よって、半導体装置に外 付けのダイオードを接続する必要がなぐ半導体装置を小型に形成することができる 。半導体装置のオン時には、側面 (31c)から離間した半導体基体 (31)の中央側に電 流が流れるが、半導体装置のオフ時に逆方向電流が発生したとき、逆方向電流が半 導体基体 (31)の側面 (31c)に近接して流れるため、電流により発生する熱が半導体基 体 (31)の中央側に集中して、半導体基体 (31)の電気的特性が劣化することを防止で きる。また、半導体基体 (31)の側面 (31c)に近接してダイオード (21)が形成されるため、 ダイオード (21)に流れる逆方向電流により発生する熱は、半導体基体 (31)の側面 (31c )から良好に外部に放出される。
発明の効果
[0010] 本発明によれば、より小型化され且つ信頼性の高 、スタックドマルチ構造の半導体 装置を提供することができる。
図面の簡単な説明
[0011] [図 1]本発明による半導体装置の一実施の形態を示す部分拡大断面図
[図 2]図 1の全体図
[図 3]図 2の平面図
[図 4]図 3の回路図
[図 5]—般的な MOSFETの断面図
[図 6]—般的な IGBTの断面図
符号の説明
[0012] (1)· ·第 1の半導体素子 (第 1の IGBT)、 （2) · ·第 2の半導体素子 (第 2の IGBT)、
(3) · ·第 3の半導体素子 (第 3の IGBT)、 （4) · ·第 4の半導体素子 (第 4の IGBT)、 (5)· ·支持板、 （7)· ·第 1の半導体素子積層体、 （8)· ·第 2の半導体素子積層体、 (9)· ·絶縁体 (ゲート絶縁膜)、 （10)· ·Η型ブリッジ回路、 （13) · ·制御素子、 （15)· •コレクタ領域、 （15a)' ·上面、 （15b) ' ·下面、 （16) · ·第 1のベース領域、 （16a) ' · 上面、 （17)· ·第 2のベース領域、 （17a)' ·上面、 （18)· ·ェミッタ領域、 （18a)' '上 面、 （21)· 'ダイオード、 （22)· ·ェミッタ電極、 （23)· ·コレクタ電極、 （24)· ·ダイォー ド電極、 （25) · ·ゲート電極、 （26) · ·周辺部、 （26a)' ·上面、 （27)· ·周辺ベース領 域、 （31)· ·半導体基体 (半導体基板)、 （31c ，側面、
発明を実施するための最良の形態
[0013] 以下、 IGBTにより H型ブリッジ回路を構成した本発明による半導体装置の一実施 の形態を図 1〜図 4について説明する。
[0014] 本実施の形態の半導体装置は、図 1〜図 3に示すように、放熱性を有する銅又はァ ルミ-ゥム等の金属製の支持板 (5)と支持板 (5)の上に順次積層されて固着された第 1 の半導体素子としての第 1の IGBT (絶縁ゲート型バイポーラトランジスタ)（1)及び第 2 の半導体素子としての第 2の IGBT(2)を有する第 1の半導体素子積層体 (7)と、支持 板 (5)の上に順次積層されて固着された第 3の半導体素子としての第 3の IGBT(3)及 び第 4の半導体素子としての第 4の IGBT(4)を有する第 2の半導体素子積層体 (8)と、 第 1の IGBT(l)力も第 4の IGBT(4)までのスイッチング動作を制御する制御素子 (13)と を備え、図 4に示す H型ブリッジ回路 (10)を構成する。
[0015] 第 1の IGBT(l)〜第 4の IGBT(4)の上面電極（ェミッタ電極及びゲート電極）と、制 御素子 (13)の上面電極 (制御電極)又は支持板 (5)の周囲に配置された複数の外部リ ード (33)とは、ワイヤ（リード細線) (29)により接続される。第 1の IGBT(l)のェミッタ電極 (22)と第 2の IGBT(2)のコレクタ電極 (23)との接続点 (A )と、第 3の IGBT(3)のェミッタ
1
電極 (22)と第 4の IGBT(4)のコレクタ電極 (23)との接続点 (A )との間には、交流電流に
2
より駆動される例えば冷陰極蛍光放電管である負荷 (6)が接続される。 H型ブリッジ回 路 (10)を構成する半導体装置は榭脂封止体 (34)により被覆されて一体化されるが、 外部リード (33)は榭脂封止体 (34)力 外部に導出される。この外部リード (33)の一部に 負荷 (6)が接続される。
[0016] 第 1の半導体素子積層体 (7)を構成する第 1の IGBT(l)及び第 2の IGBT(2)の一方 並びに第 2の半導体素子積層体 (8)を構成する第 3の IGBT(3)及び第 4の IGBT(4)の 一方は、 H型ブリッジ回路 (10)のノ、ィサイド側スィッチを構成し、第 1の半導体素子積 層体 (7)を構成する第 1の IGBT(l)及び第 2の IGBT(2)の他方並びに第 2の半導体素 子積層体 (8)を構成する第 3の IGBT(3)及び第 4の IGBT(4)の他方は、 H型ブリッジ回 路 (10)のローサイド側スィッチを構成する。本実施の形態では、ハイサイド側の第 1の IGBT(l)と第 3の IGBT(3)との上に、ローサイド側の第 2の IGBT(2)と第 4の IGBT(4) カ涸着されて第 1及び第 2の半導体素子積層体 (7,8)が構成され、第 1の半導体素子 積層体 (7)と第 2の半導体素子積層体 (8)との間に設けられる制御素子 (13)と共に、半 田、ろう材又は銀ペーストから成る接着剤 (32)により単一の支持板 (5)上に固着される
[0017] 第 2の IGBT(2)及び第 4の IGBT(4)は、平面的に見て、第 1の IGBT(l)及び第 3の I GBT(3)の上面 (la,3a)及び下面 (lb,3b)と比較して小さい面積の上面 (2a,4a)及び下面 (2b,4b)を有する。第 1の IGBT(l)〜第 4の IGBT(4)は、図 1に示すように、半導体基 体としてのシリコン単結晶等力も成る半導体基板 (31)を備え、各半導体基板 (31)は、 第 1導電型としての P型導電型を有するコレクタ領域 (15)と、 P型導電型とは反対の第 2導電型としての N型導電型を有し且つコレクタ領域 (15)の上面 (15a)に形成された第 1のベース領域 (16)と、 P型導電型を有し且つ第 1のベース領域 (16)に隣接して上面（ 16a)側に形成された第 2のベース領域 (17)と、 N型導電型を有し且つ第 2のベース領 域 (17)に隣接して上面 (17a)側に形成されたェミッタ領域 (18)とを備える。
[0018] また、第 1の IGBT(l)〜第 4の IGBT(4)は、絶縁体としてのゲート絶縁膜 (9)を介して 第 2のベース領域 (17)の上面 (17a)に形成されたゲート電極 (制御電極) (25)と、第 2の ベース領域 (17)及びェミッタ領域 (18)の上面 (17a,18a)に形成されたェミッタ電極（上 面電極）（22)と、コレクタ領域 (15)の下面 (15b)に形成されたコレクタ電極 (底面電極） (2 3)とをそれぞれ備える。ェミッタ領域 (18)と第 1のベース領域 (16)との間に挟まれた第 2 のベース領域 (17)の上にゲート絶縁膜 (9)を介して形成されるゲート電極 (25)により、 周知のチャネル領域が形成される。
[0019] 第 2のベース領域 (17)は、半導体基板 (31)の平面方向に対して、第 1のベース領域 ( 16)内に格子状又はストライプ状に並列して配置される。また、ェミッタ領域 (18)は、第 2のベース領域 (17)の縁部に沿って互いに対向するように配置される。更に、ゲート 電極 (25)は、隣り合う第 2のベース領域 (17)に跨るように第 2のベース領域 (17)の間に ストライプ状に形成される。これにより、半導体素子の活性領域の最小単位であるセ ル (30)が形成される。第 2のベース領域 (17)は、第 1のベース領域 (16)内に島状に形 成してもよい。図示しないが、半導体基板 (31)の上面 (31a)には、ゲート電極 (25)と電 気的に接続するゲートバスラインが半導体基板 (31)の周面に沿って形成される。ゲー トバスラインは、アルミニウム等の導電性金属により形成され、ストライプ状に形成され たゲート電極 (25)の延長部分を被覆して、ゲート電極 (25)と電気的に接続される。
[0020] 導電性の接着剤 (32)により、第 1の IGBT(l)のェミッタ電極 (22)と第 2の IGBT(2)のコ レクタ電極 (23)とが電気的に接続され、第 3の IGBT(3)のェミッタ電極 (22)と第 4の IG BT(4)のコレクタ電極 (23)とが電気的に接続される。ゲート絶縁膜 (9)は、例えば二酸 化シリコンにより形成され、ゲート絶縁膜 (9)の上面に例えばポリシリコン力 成るゲー ト電極 (25)が形成される。また、ゲート電極 (25)の周囲には、ゲート電極 (25)とェミッタ 電極 (22)とを電気的に絶縁する例えば二酸ィ匕シリコン力も成る層間絶縁膜 (19)が形 成される。ェミッタ電極 (22)及びコレクタ電極 (23)は、例えばアルミニウム又はアルミ- ゥムとニッケルとを積層した積層体により形成される。
[0021] 図 1に示すように、各 IGBT(1,2,3,4)の第 1のベース領域 (16)は、半導体基板 (31)の 側面 (31c)に近接する周辺部 (26)を有し、第 1のベース領域 (16)の周辺部 (26)に隣接 して形成された P型導電型を有する周辺ベース領域 (27)により、半導体基板 (31)の側 面 (31c)に近接してダイオード (21)が形成される。図示する半導体装置では、第 2のべ ース領域 (17)及びェミッタ領域 (18)が半導体基板 (31)の一角を形成する 2つの側面 (3 lc)力も離間して素子中央側に形成されるのに対し、第 1のベース領域 (16)の周辺部（ 26)及び周辺ベース領域 (27)が半導体基板 (31)の 2つの側面 (31 c)に隣接して形成さ れる。即ち、図 1に示す各 IGBT(1,2,3,4)は、半導体基板 (31)の側面 (31c)側に形成さ れた環状の周辺部 (26)と、この周辺部 (26)に囲まれて素子中央側に配置された中央 部とを有し、周辺部 (26)にダイオード (21)が形成され、中央部にセル (30)が形成される 。周辺ベース領域 (27)は、半導体基板 (31)の上面 (31a)にホウ素等の不純物を拡散し て、第 2のベース領域 (17)と共に形成することができる。よって、製造コストを増加せず 、既存と同一の製造工程により周辺ベース領域 (27)を形成できる。本実施の形態で は、第 2のベース領域 (17)に対向する側の周辺ベース領域 (27)内にェミッタ領域 (18) を形成している力 周辺ベース領域 (27)内にはェミッタ領域 (18)を形成しなくてもよい [0022] 第 1のベース領域 (16)の周辺部 (26)の上面 (26a)に形成されたダイオード電極 (24)を 備える。図示する半導体装置では、ゲート電極 (25)及びェミッタ電極 (22)が半導体基 板 (31)の 2つの側面 (31c)力も離間して形成されるのに対し、ダイオード電極 (24)が半 導体基板 (31)の 2つの側面 (31c)に隣接して形成される。ダイオード電極 (24)とェミッタ 電極 (22)との間には、間隙 (20)が形成され、ダイオード電極 (24)とェミッタ電極 (22)とを 電気的に分離する。ダイオード電極 (24)とェミッタ電極 (22)との絶縁性を向上するため に、ダイオード電極 (24)とェミッタ電極 (22)との間に二酸ィ匕シリコン力 成る図示しない 絶縁膜を形成してもよい。絶縁膜は、層間絶縁膜 (19)を形成する工程時に、層間絶 縁膜 (19)と共に形成できる。ダイオード電極 (24)は、例えばワイヤ (28)を形成するアル ミニゥムとの接着性の高い同じアルミニウム又はシリコン含有アルミニウムにより形成さ れる。また、ダイオード電極 (24)は、平坦に形成された上面 (24a)を有し、周知のワイヤ ボンディング法により、同様に上面が平坦に形成された支持板 (5)又は外部リード (33) とワイヤ (28)により結線される。ダイオード電極 (24)と外部リード (33)とをワイヤ (28)によ り結線する工程は、第 1の IGBT(l)〜第 4の IGBT(4)の上面電極と制御素子 (13)の上 面電極又は外部リード (33)とをワイヤ (29)により結線する工程と同一工程により行うこと ができるため、製造コストが増加せず、既存と同一の製造工程により半導体装置を製 造できる。
[0023] 第 1の IGBT(l)〜第 4の IGBT(4)のダイオード電極 (24)とコレクタ電極 (23)とは、それ ぞれ電気的に接続され、図 4に示すように、各 IGBT(1,2,3,4)のェミッタとコレクタとの 間にはダイオードが並列接続される。ノ、ィサイド側スィッチを構成する第 1の IGBT(l) 及び第 3の IGBT(3)は、正側端子に接続された外部リード (33)とダイオード電極 (24)と をワイヤ (28)で接続することにより、正側端子に接続された別の外部リード (33)及び支 持板 (5)を通じてダイオード電極 (24)とコレクタ電極 (23)とが電気的に接続される。ロー サイド側スィッチを構成する第 2の IGBT(2)及び第 4の IGBT(4)は、接続点 (A ,Α )〖こ
1 2 接続された外部リード (33)とダイオード電極 (24)とをワイヤ (28)で接続することにより、 接続点 (A ,Α )に接続された別の外部リード (33)及びワイヤ (29)を通じてダイオード電
1 2
極 (24)とコレクタ電極 (23)とが電気的に接続される。
[0024] 第 1の IGBT(l)〜第 4の IGBT(4)には、 H型ブリッジ回路 (10)に接続される負荷 (6) の誘導成分による逆起電力により、各 IGBT(1,2,3,4)のェミッタ電極 (22)力 コレクタ 電極 (23)へ逆方向に誘起される逆方向電流 (サージ電流）が発生するが、 P型導電 型を有する周辺ベース領域 (27)と N型導電型を有する第 1のベース領域 (16)の周辺 部 (26)とによりダイオード (21)を形成し、周辺部 (26)の上面 (26a)に形成されたダイォー ド電極 (24)とコレクタ電極 (23)とを電気的に接続することによって、逆方向電流を周辺 ベース領域 (27)、第 1のベース領域 (16)の周辺部 (26)及びダイオード電極 (24)を通じ てコレクタ電極 (23)に流すことができる。よって、半導体装置に外付けのダイオードを 接続する必要がなぐ H型ブリッジ回路 (10)を構成する半導体装置を小型に形成する ことができる。
[0025] H型ブリッジ回路 (10)を作動する際に、制御素子 (13)により、第 1の IGBT(l)及び第 4の IGBT(4)と、第 2の IGBT(2)及び第 3の IGBT(3)とを交互にオン.オフ動作させて 、スイッチング作動させることにより、接続点 (A )と (A )との間に交互に逆方向の電流 (I
1 2 1
,1 )を流して、負荷 (6)を作動させることができる。第 1の IGBT(l)及び第 4の IGBT(4)
2
がオンのとき、第 2の IGBT(2)及び第 3の IGBT(3)がオフとなり、負荷 (6)に一方向の 電流 (I )が流れ、その後、第 1の IGBT(l)及び第 4の IGBT(4)がオフに切り換えられ、
1
第 2の IGBT(2)及び第 3の IGBT(3)とがオンに切り換えられると、負荷 (6)に他方向の 電流 (I )が流れて、負荷 (6)が交流電流により作動される。一方向の電流 (I )は、第 1の
2 1
IGBT(1)、第 4の IGBT(4)及び支持板 (5)に流れ、他方向の電流 (I )は、第 2の IGBT(
2
2)、第 3の IGBT(3)及び支持板 (5)に流れる。
[0026] このように、第 1の IGBT(l)から第 4の IGBT(4)までのスイッチング動作を行な!/、、直 流電圧源を使用し、接続点 (A )と (A )との間に接続された冷陰極蛍光放電管を点灯
1 2
させることができる。半導体装置のオン時には、側面 (31c)から離間した半導体基板 (3 1)の中央側に電流が流れるが、半導体装置のオフ時に逆方向電流が発生したときは 逆方向電流が半導体基板 (31)の側面 (31c)に近接して流れる。このため、オン電流の 流れる電流通路とサージ電流の流れる電流通路とを分離することができ、電流により 発生する熱が半導体基板 (31)の中央側に集中して、半導体基板 (31)の電気的特性 が劣化することを防止できる。また、半導体基板 (31)の側面 (31c)に近接してダイォー ド (21)が形成されるため、ダイオード (21)に流れる逆方向電流により発生する熱は、半 導体基板 (31)の側面 (31c)力も良好に外部に放出される。図示する H型ブリッジ回路（ 10)では、第 1の IGBT(l)及び第 4の IGBT(4)がオンされて第 2の IGBT(2)及び第 3の IGBT(3)がオフされた際、第 1の IGBT(l)及び第 4の IGBT(4)を構成する半導体基板 (31)の中央側に電流が流れる。次に、第 2の IGBT(2)及び第 3の IGBT(3)がオンされ て、第 1の IGBT(l)及び第 4の IGBT(4)がオフされた際、第 1の IGBT(l)及び第 4の I GBT(4)に逆方向電圧が印加される。この逆方向電圧に基づくサージ電流は第 1の I GBT(l)及び第 4の IGBT(4)を構成する半導体基板 (31)に内蔵されたダイオード (21) をバイパスして流れる力 この電流は上述のように半導体基板 (31)の側面 (31c)に近 接して流れる。
[0027] 本発明の実施の形態は、前記実施の形態に限定されず、種々の変更が可能であ る。例えば、図 1に示す半導体装置では、周辺ベース領域 (27)を半導体基板 (31)の 角部に形成したが、角部カゝら離間した側面 (31c)近傍に形成してもよい。
産業上の利用可能性
[0028] 本発明は、複数の半導体素子を積重して形成された半導体装置、冷陰極蛍光放 電管の駆動装置に使用される Hブリッジ回路 (フルブリッジ回路)等を構成する半導 体装置に良好に適用できる。

Claims

請求の範囲
[1] 第 1の半導体素子と、該第 1の半導体素子上に積層された第 2の半導体素子とを備 え、
前記第 1の半導体素子及び第 2の半導体素子の各々は、
第 1導電型を有するコレクタ領域、第 1導電型とは反対の第 2導電型を有し且つ前 記コレクタ領域の上面に形成された第 1のベース領域、第 1導電型を有し且つ前記 第 1のベース領域に隣接して形成された第 2のベース領域、第 2導電型を有し且つ 前記第 2のベース領域に隣接して形成されたェミッタ領域とを備える半導体基体と、 絶縁体を介して前記第 2のベース領域の上面に形成されたゲート電極と、 前記第 2のベース領域及びェミッタ領域の上面に形成されたェミッタ電極と、 前記コレクタ領域の下面に形成されたコレクタ電極とを備えた半導体装置において 前記第 1のベース領域は、前記半導体基体の側面に近接する周辺部を有し、 前記第 1の半導体素子及び第 2の半導体素子は、第 1導電型を有し且つ前記第 1 のベース領域の周辺部に隣接してダイオードを形成する周辺ベース領域と、前記第 1のベース領域の周辺部の上面に形成されたダイオード電極とを備え、
前記第 1の半導体素子及び第 2の半導体素子の前記ダイオード電極と前記コレクタ 電極とをそれぞれ電気的に接続したことを特徴とする半導体装置。
[2] 前記第 1の半導体素子のェミッタ電極と、前記第 2の半導体素子のコレクタ電極と は、それぞれ電気的に接続され、
前記第 1の半導体素子と前記第 2の半導体素子とは、交互にスイッチング動作され る請求項 1に記載の半導体装置。
[3] 放熱性を有する支持板と、該支持板上に順次積層されて固着された第 1の半導体 素子及び第 2の半導体素子を有する第 1の半導体素子積層体と、前記支持板上に 順次積層されて固着された第 3の半導体素子及び第 4の半導体素子を有する第 2の 半導体素子積層体と、前記第 1の半導体素子から前記第 4の半導体素子までのスィ ツチング動作を制御する制御素子とを備え、
前記第 1の半導体素子〜第 4の半導体素子は、 第 1導電型を有するコレクタ領域、第 1導電型とは反対の第 2導電型を有し且つ前 記コレクタ領域の上面に形成された第 1のベース領域、第 1導電型を有し且つ前記 第 1のベース領域に隣接して形成された第 2のベース領域、第 2導電型を有し且つ 前記第 2のベース領域に隣接して形成されたェミッタ領域を備える半導体基体と、 絶縁体を介して前記第 2のベース領域の上面に形成されたゲート電極と、 前記第 2のベース領域及びェミッタ領域の上面に形成されたェミッタ電極と、 前記コレクタ領域の下面に形成されたコレクタ電極とを備えた半導体装置において 前記第 1のベース領域は、前記半導体基体の側面に近接する周辺部を有し、 前記第 1の半導体素子〜第 4の半導体素子は、第 1導電型を有し且つ前記第 1の ベース領域の周辺部に隣接してダイオードを形成する周辺ベース領域と、前記第 1 のベース領域の周辺部の上面に形成されたダイオード電極とを備え、
前記第 1の半導体素子〜第 4の半導体素子の前記ダイオード電極と前記コレクタ電 極とをそれぞれ電気的に接続したことを特徴とする半導体装置。
[4] 前記第 1の半導体素子のェミッタ電極と、前記第 2の半導体素子のコレクタ電極と は、電気的に接続され、
前記第 3の半導体素子のェミッタ電極と、前記第 4の半導体素子のコレクタ電極と は、電気的に接続され、
前記第 1の半導体素子及び第 4の半導体素子と前記第 2の半導体素子及び第 3の 半導体素子とは、交互にスイッチング動作される請求項 3に記載の半導体装置。
[5] 前記第 1の半導体素子積層体の第 1の半導体素子及び第 2の半導体素子と、前記 第 2の半導体素子積層体の第 3の半導体素子及び第 4の半導体素子とは、 H型プリ ッジ回路を構成し、
前記第 1の半導体素子積層体を構成する前記第 1の半導体素子及び第 2の半導 体素子の一方並びに前記第 2の半導体素子積層体を構成する前記第 3の半導体素 子及び第 4の半導体素子の一方は、前記 H型ブリッジ回路のハイサイド側スィッチを 構成し、
前記第 1の半導体素子積層体を構成する前記第 1の半導体素子及び第 2の半導 体素子の他方並びに前記第 2の半導体素子積層体を構成する前記第 3の半導体素 子及び第 4の半導体素子の他方は、前記 H型ブリッジ回路のローサイド側スィッチを 構成する請求項 3に記載の半導体装置。
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EP1909329A4 (en) 2008-09-17
EP1909329B1 (en) 2011-11-02
CN101223644A (zh) 2008-07-16
KR100983959B1 (ko) 2010-09-27
KR20080033973A (ko) 2008-04-17
JP2007027432A (ja) 2007-02-01
EP1909329A1 (en) 2008-04-09
CN101223644B (zh) 2010-05-19
US8143645B2 (en) 2012-03-27
US20090140289A1 (en) 2009-06-04

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