WO2006095715A1 - 試験装置、試験方法、電子デバイスの生産方法、試験シミュレータ、及び試験シミュレーション方法 - Google Patents
試験装置、試験方法、電子デバイスの生産方法、試験シミュレータ、及び試験シミュレーション方法 Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 808
- 238000000034 method Methods 0.000 title claims description 47
- 238000004088 simulation Methods 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000010998 test method Methods 0.000 title claims description 14
- 238000001514 detection method Methods 0.000 claims abstract description 122
- 230000008859 change Effects 0.000 claims abstract description 49
- 230000002950 deficient Effects 0.000 claims abstract description 35
- 230000004044 response Effects 0.000 claims description 15
- 230000003252 repetitive effect Effects 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000007493 shaping process Methods 0.000 description 23
- 238000012545 processing Methods 0.000 description 21
- 230000002596 correlated effect Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 230000000875 corresponding effect Effects 0.000 description 12
- 238000007689 inspection Methods 0.000 description 10
- 238000011990 functional testing Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000004891 communication Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31928—Formatter
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
Definitions
- Test apparatus test method, electronic device production method, test simulator, and test simulation method
- the present invention relates to a potential difference between a pair of signals forming a differential signal output from an inspection object.
- the present invention relates to a potential comparator for deriving a magnitude relationship between predetermined threshold potentials.
- This application is related to the following Japanese application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
- inspection apparatuses for inspecting characteristics and the like of electronic circuits are known! Specifically, such an inspection apparatus compares an electrical signal output from an electronic circuit to be inspected with a predetermined threshold voltage by a potential comparator, and determines the quality of the electronic circuit based on the comparison result. It has a function. Therefore, the reliability of the inspection performed by the inspection device largely depends on the comparison accuracy of the potential comparator that performs the potential comparison, and the potential comparator that constitutes the inspection device is very important from the viewpoint of the reliability of the inspection. Become.
- the differential transmission method is a technique for transferring a signal using two transmission lines. Specifically, the differential transmission method is based on a potential difference between two electric signals transmitted via the two transmission lines. Or, a low judgment is made. In response to the increase in the number of electronic circuits using the differential transmission method, even in the field of inspection devices that perform characteristics inspection of electronic circuits, etc., an inspection device equipped with a potential comparator compatible with the differential transmission method Realization of this is requested.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2002-215712
- the conventional test apparatus and test simulator have the ability to simulate an electronic device or a device simulator that simulates the electronic device, even when multiple output signals are output. is doing. Therefore, even when the timing at which each output signal changes is correlated among the plurality of output signals, it is possible to test the electronic device based on the correlation and identify the quality. There wasn't.
- an object of the present invention is to provide a test apparatus, a test method, an electronic device production method, a test simulator, and a test simulation method that can solve the above-described problems.
- This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- a test signal is given to an electronic device, and a plurality of output signals that are output according to the test signal are expected.
- a test apparatus for testing whether an electronic device performs an expected operation by comparing with a value, a reference timing detection means for detecting that one output signal has changed, and one output signal The setting means for presetting the minimum time until the change of one other output signal after the change, and the timing when the minimum time has passed since the reference timing detection means detected a change in one output signal.
- the capturing means for capturing the value of another output signal and the value of the other output signal captured by the capturing means are taken by the other output signal after the minimum time has elapsed.
- Chikaratsu comprises identifying means for identifying an electronic device to be defective.
- the capture means includes a strobe generation means for generating a strobe signal at a timing when a minimum time has elapsed since the reference timing detection means has detected a change in one output signal, and another strobe signal.
- a comparator that captures the values of two output signals.
- the test apparatus further includes expected value holding means for holding in advance, as an expected value, a value that should be taken by another one of the output signals when the value of one output signal changes and the minimum force time has elapsed. Also good.
- the minimum time is the setup time of one output signal for other electronic devices operating upon receipt of the output signal from the electronic device, or It ’s okay!
- a test signal is given to the electronic device, and a plurality of output signals output from the electronic device according to the test signal are respectively compared with expected values
- a test method for testing whether or not an electronic device performs an expected operation and a reference timing detection step for detecting that one output signal has changed, and after one output signal has changed.
- the capture step that captures the value of one output signal and the value force of another output signal that is captured in the capture step!
- an identification step for identifying the electronic device as defective when the number is not matched with the value to be taken.
- a method of producing an electronic device that selectively produces electronic devices that perform an expected operation wherein a reference timing detection step for detecting that one output signal has changed, and after one output signal has changed,
- the setting step for presetting the minimum time until another output signal changes, and the timing at which the minimum time has passed since the change of one output signal was detected in the reference timing detection step The step of capturing the value of one output signal of the other, and the value force of the other output signal captured in the capturing step after the minimum time has passed.
- a test signal is given to a device simulator that simulates the operation of an electronic device, and a plurality of output signals from which a device simulator power is also output according to the test signal are provided.
- a test signal is given to the electronic device, and a plurality of output signals output from the electronic device according to the test signal are respectively compared with expected values
- the setting means that presets the minimum time until one output signal changes, and the time from when the reference timing detection means detects a change in one output signal until the other output signal changes
- a test signal is given to the electronic device, and a plurality of output signals output from the electronic device according to the test signal are respectively compared with expected values, A test method for testing whether or not an electronic device performs an expected operation, and a reference timing detection step for detecting that one output signal has changed, and after one output signal has changed.
- a test signal is given to the electronic device, and a plurality of output signals output from the electronic device according to the test signal are respectively compared with expected values
- a method of producing an electronic device that selectively produces electronic devices that perform the expected operation, and a reference timing for detecting that one output signal has changed.
- a detection step, a setting step for presetting a minimum time from when one output signal changes until another one changes, and a change of one output signal during the reference timing detection step Elapsed time detection step that detects the elapsed time from when a signal is detected until another output signal changes, and identification that identifies an electronic device as a defective product when the elapsed time is shorter than the previous minimum time Steps.
- a test signal is given to a device simulator that simulates the operation of an electronic device, and a plurality of output signals that also output a device simulator power according to the test signal are provided.
- a test simulator for testing whether or not an electronic device performs an expected operation by comparing with each expected value, a reference timing detection means for detecting that one output signal has changed, A setting unit that presets a minimum time from when an output signal changes until another one output signal changes, and a reference timing detection unit that detects a change in one output signal and then another one Elapsed time detection means for detecting the elapsed time until the output signal changes, and when the elapsed time is shorter than the minimum time in the previous period, the electronic device is regarded as defective. Identifying and an identification means.
- a plurality of test signals are given to the electronic device, and a plurality of output signals output from the electronic device in response to the plurality of test signals are provided.
- Test signal detection means for detecting the value of another test signal at the time when the time has elapsed, and the value of the other test signal detected by the detection means. When not match the pre-stored value as a value to be taken by one of the test signal, and a notification means for Do can be correctly tested electronic devices, and determines to notify.
- a plurality of test signals are given to a device simulator that simulates the operation of an electronic device, and a device is responsive to the plurality of test signals.
- a test simulator that tests whether or not an electronic device can be tested correctly by comparing multiple output signals output from the chair simulator with expected values.
- reference timing acquisition means for acquiring the time to be performed, setting means for presetting a minimum time from when one test signal changes until another test signal changes, and reference timing acquisition means
- the test signal detection means for detecting the value of another test signal at the timing when the minimum time has elapsed from the time when one test signal changes, and the other test signal detected by the detection means When the minimum time elapses, another electronic test signal does not match the value stored in advance as the value to be taken. Do can Ku and child test, it is determined that and a notifying means for notifying to that effect.
- a plurality of test signals are given to a device simulator for simulating the operation of an electronic device, and a plurality of signals output from the device simulator according to the plurality of test signals.
- This is a test simulation method that tests whether or not an electronic device can be correctly tested by comparing the output signal of each with the expected value, and a reference timing for obtaining the time at which one test signal changes.
- the acquisition step, the setting step for presetting the minimum time from when one test signal changes until the other test signal changes, and the reference timing acquisition step A test signal detection scan that detects the value of one other test signal at the timing when the minimum time has elapsed from the time when one test signal changes.
- the test simulation method further includes a storage step of storing the modified test signal pattern after the notification in the notification step. After the storage step, the reference timing acquisition step and the test signal detection are performed again. Steps may be performed.
- a plurality of test signals are given to a device simulator that simulates the operation of an electronic device, and device simulation is performed according to the plurality of test signals. By comparing each output signal with the expected value, it is tested whether the electronic device can be tested correctly, and the test signal pattern used for the test is used.
- a method of producing an electronic device that tests an actual electronic device to select and produce an electronic device that performs an expected operation, and obtains a reference timing acquisition step for obtaining a time at which one test signal changes; From the setting step that presets the minimum time from when one test signal changes to the time when another test signal changes, and from the time when one test signal changes acquired in the reference timing acquisition step
- the test signal detection step detects the value of another test signal at the timing when the minimum time has elapsed, and the detection is performed in the detection step. If the value of one other test signal does not match the pre-stored value that the other test signal should take after the minimum time has elapsed, the electronic device is correctly tested.
- the reference timing acquisition step and the test signal detection step are repeatedly performed, and the value of the other test signal detected in the detection step is the value that the other test signal should take after the minimum time has elapsed.
- a plurality of test signals are given to the electronic device, and a plurality of output signals output from the device simulator according to the plurality of test signals are respectively compared with expected values.
- a test apparatus for testing whether or not an electronic device can be correctly tested and a reference timing acquisition means for acquiring a time when one test signal changes, and after one test signal changes, The other test signal changes from the setting means that presets the minimum time until another test signal changes, and the time when one test signal changes obtained by the reference timing acquisition means.
- Elapsed time detection means to detect the elapsed time until, and the elapsed time is the minimum in the previous period
- a notification means for notifying that the electronic device cannot be correctly tested when the time is shorter.
- a plurality of test signals are given to a device simulator that simulates the operation of an electronic device, and a plurality of signals output from the device simulator according to the plurality of test signals are provided.
- This is a test simulator that tests whether or not the power of each device can be correctly tested by comparing each output signal with the expected value, and the reference timing for obtaining the time when one test signal changes
- Elapsed time detection means that detects the elapsed time from when the time changes to when another test signal changes, and the elapsed time from the previous minimum time
- the Itoki, and a notifying means for Do can be correctly tested electronic devices, and determines to notify
- a plurality of test signals are given to a device simulator that simulates the operation of an electronic device, and a plurality of signals output from the device simulator according to the plurality of test signals are provided.
- This is a test simulation method that tests whether or not an electronic device can be correctly tested by comparing the output signal of each with the expected value, and a reference timing for obtaining the time at which one test signal changes.
- the acquisition step, the setting step for presetting the minimum time from when one test signal changes until the other test signal changes, and the reference timing acquisition step An elapsed time detecting step for detecting an elapsed time from the time when one test signal changes to the time when the other one test signal changes, A notification step for notifying that the electronic device cannot be correctly tested when the overtime is shorter than the minimum time in the previous period.
- the test simulation method further includes a storage step of storing the modified test signal pattern after the notification is performed in the notification step, and the reference timing acquisition step and the elapsed time detection step are performed again after the storage step. May be
- a device that simulates the operation of the electronic device is used.
- the electronic device By applying multiple test signals to the device simulator and comparing the multiple output signals output to the device simulator in response to the multiple test signals with expected values, the electronic device can be tested correctly.
- the process from the time when one test signal changes, acquired in the reference timing acquisition step, to the time when one other test signal changes An elapse time detection step for detecting a time interval, and a notification step and a notification step for notifying that the electronic device cannot be correctly tested when the elapsed time is shorter than the minimum time in the previous period and notifying the fact.
- the value of the other test signal detected in the step is used to modify the electronic device using the modified test signal pattern when the other test signal matches the value to be taken after the minimum time has elapsed.
- the actual test step of testing the actual product and the value of the output signal obtained from the electronic device module by the actual test step match the expected value, And a identification identifying the electronic device as a good product.
- the present invention by testing the correlation of the timing at which each output signal changes among a plurality of output signals output from the electronic device, The quality can be identified with higher accuracy.
- FIG. 1 is a block diagram showing an example of a functional configuration of the test system 10 according to the first embodiment of the present invention.
- the test system 10 includes a test control device 12, a test device 14, and a DUT (Device Under Test) 16.
- the test system 10 tests the DUT 16 that is an electronic device by using the test apparatus 14.
- the test control device 12 controls the test device 14 to cause the test device 14 to execute the test of the DUT 16.
- the test equipment 14 gives a test signal to the DU T16 and compares the output signals output from the DUT 16 in response to the test signal with the expected values to determine whether or not the DUT 16 performs the expected operation.
- the DUT 16 generates a plurality of output signals according to the test signal given from the test apparatus 14, and outputs each of the plurality of output signals using each of the plurality of pins provided in the DUT 16.
- the test apparatus 14 performs processing for comparing each of a plurality of output signals output from the DUT 16 with expected values, as in a functional test using a conventional test apparatus.
- testing the DUT16 independently for each output signal testing the correlation of the timing at which each output signal changes among multiple output signals can be made more effective. The purpose is to identify with high accuracy
- the plurality of output signals whose timings to change described in this example correlate with, for example, the DUT 16 outputs a signal designating an address to another electronic device such as a DRAM.
- a row address strobe (RAS) signal indicating the timing of inputting the address signal and the address value indicated by the address signal as a row address
- a column address indicating the timing of inputting the address value indicated by the address signal as a column address
- CAS strobe
- the test apparatus 14 includes a pattern generation unit 100, a timing generation unit 110, a waveform shaping unit 120, a driver 130, a reference timing detection unit 140, a setting unit 150, an acquisition unit 160, an expected value holding unit 170, and Identification means 180 is provided.
- the pattern generation means 100 Based on the control of the test control device 12, the pattern generation means 100 generates a test signal pattern to be applied to the DUT 16 and outputs the generated test signal pattern to the waveform shaping means 120. Also, pattern generation The means 100 generates information indicating the expected value of the output signal output by the DUT 16 when the test signal corresponding to the generated test signal pattern is given, and outputs the generated information to the expected value holding means 170. To do.
- the information indicating the expected value is, for example, the correlation between the timing at which each output signal changes between one output signal and the other output signal among the plurality of output signals output by the DUT16.
- the timing generation unit 110 Based on the control of the test control device 12, the timing generation unit 110 generates a timing at which a test signal should be given to the DUT 16, and information indicating the timing is generated by the waveform shaping unit 120, the reference timing detection unit 140, and the expected value. Output to holding means 170.
- the waveform shaping means 120 is based on the pattern of the test signal to be given to the DUT 16 received from the pattern generation means 100 and the information received from the timing generation means 110 and indicating the timing to give the test signal to the DUT 16. Then, shape the waveform of the test signal to be given to the DUT 16 and output it to the driver 130.
- the driver 130 provides the DUT 16 with a test signal that also receives the waveform shaping means 120 force.
- the test apparatus 14 may have a plurality of pin cards corresponding to each of the plurality of pins provided in the DUT 16, and each of the drivers 130 provided for each pin force mode is used. Different test signals may be applied to each of the plurality of pins. Then, the DUT 16 generates a plurality of output signals according to the given test signal, and outputs the generated output signals to the reference timing detection means 140 and the capture means 160.
- the reference timing detection means 140 detects that one of the output signals output from the DUT 16 has changed. For example, the reference timing detection unit 140 generates a plurality of strobe signals, captures the value of the one output signal in accordance with each of the plurality of strobe signals, and the captured value is the previously acquired value power. It may be detected that the one output signal has changed depending on whether or not the force has changed. Then, the reference timing detection unit 140 outputs information indicating the timing at which the one output signal has changed to the capturing unit 160. The setting unit 150 outputs each output signal between one output signal and the other output signal among the plurality of output signals output from the DUT 16.
- the minimum time from when the one output signal changes until the other output signal changes is based on, for example, the control of the test control device 12.
- the setting means 150 outputs information indicating the set minimum time to the capturing means 160.
- the capturing means 160 includes a strobe generating means 162 and a comparator 164.
- the reference time detecting means 140 detects a change in one output signal, and then the minimum time set by the setting means 150 is set. The value of the other output signal is captured at the timing when elapses.
- the strobe generation unit 162 generates a strobe signal at a timing when a set minimum time has elapsed after the reference timing detection unit 140 detects a change in one output signal, and the generated strobe signal is compared with the comparator 164. Output to.
- the strobe generating means 162 may be integrated with the timing generating means 110.
- the comparator 164 takes in the value of the other output signal output from the DUT 16 based on the strobe signal generated by the strobe generator 162. Specifically, the comparator 164 compares the value of the other output signal with the reference voltage at the timing indicated by the generated strobe signal.
- the logical value that is the comparison result may be used as the value of the other output signal. Then, the comparator 164 outputs the value of the other output signal to the identification unit 180.
- the expected value holding means 170 is An expected value of the output signal to be output corresponding to the signal is generated, and the generated expected value is held in advance.
- the expected value holding means 170 has a timing at which each output signal changes between one output signal and the other output signal among a plurality of output signals output from the DUT 16. If there is a correlation, the value to be taken by the other output signal at the timing when the minimum time set by the setting means 150 has elapsed after the value of the one output signal has changed is the expected value. Hold in advance.
- the identifying unit 180 identifies the quality of the DUT 16 by comparing the output signal captured by the capturing unit 160 with the expected value held by the expected value holding unit 170. Specifically, the identification means 180 is another output captured by the capture means 160. When the value of the signal does not match the expected value stored in the expected value holding means 170 as the value to be taken by another output signal after the set minimum time has elapsed, DUT16 is set. Identify as defective. Then, the identification unit 180 outputs the quality determination result for the DUT 16 to the test control device 12 and presents it to the user or the like.
- the test apparatus 14 has been described as identifying the quality of the DUT 16 based on the correlation of the timing of changes among a plurality of output signals. Similar to the functional test using the conventional test equipment, the quality of the DUT 16 is identified by comparing each of the multiple output signals with the expected value stored in the expected value holding means 170 at a predetermined timing. You can do it.
- the test apparatus 14 when the timings at which the output signals change are correlated among the plurality of output signals output from the electronic device.
- the electronic device can be tested based on the correlation.
- each output signal is preliminarily set even if the value of each output signal at a predetermined timing matches the expected value.
- the specified correlation is not satisfied, that is, the value of the other output signal at the timing when the preset minimum time has elapsed since the change of one output signal is different from the expected value.
- the electronic device can be identified as a defective product.
- the timing at which each output signal changes is uniform even if the value of each output signal at a predetermined timing does not match the expected value. If each output signal satisfies the predetermined correlation, the electronic device can be identified as a non-defective product.
- an electronic device can be tested with higher accuracy and more flexibility than a conventional test apparatus that performs only a functional test.
- the value of the other output signal is determined according to the strobe signal generated at the timing when the minimum time has elapsed from the timing at which one of the output signals has changed. By taking in, the correlation in each output signal can be reliably tested. Furthermore, according to the test device 14, one of the other captured Even if a variety of test signal patterns are used by holding the value to be taken by the output signal in advance as an expected value and comparing it with another captured output signal, the pattern of the test signal Testing can be performed based on the expected value for each.
- FIG. 2 shows an example of an output signal of the DUT 16 according to the first embodiment of the present invention.
- output signal A is one of the output signals described in FIG.
- the output signal B is another output signal described in FIG.
- the output signal A and the output signal B are correlated with the timing at which they change.
- output signal B does not change until a preset minimum time has elapsed after output signal A changes.
- the timing at which the output signal A changes is the timing T1
- the timing when the minimum time set by the setting means 150 has elapsed from the timing T1 is the timing T2.
- the expected value held by the expected value holding means 170 that is, the value that the output signal B should take at the timing T2 is L logic. Therefore, when the output signal B indicates the H logic at the timing T2, the identification unit 180 identifies the DUT 16 as a defective product.
- the minimum time is the set-up time of one output signal, that is, the output signal A, or another one output to another electronic device that operates by receiving an output signal from the electronic device that is the DUT16. It can be either the hold time of the signal, ie output signal B.
- the DUT 16 outputs an address signal and a RAS signal indicating a timing for inputting the address value indicated by the address signal as a row address to DRAM which is another electronic device. . That is, the test apparatus 14 tests the function of the DUT 16 that outputs the address signal and the RAS signal.
- the minimum time may be the setup time of the output signal A for other electronic devices.
- the minimum time may be the hold time of output signal B for another electronic device.
- FIG. 3 is a flowchart showing an example of a processing flow in the electronic device test method using the test apparatus 14 according to the first embodiment of the present invention.
- the setting means 150 presets the minimum time from when one output signal changes among the plurality of output signals output by the DUT 16 until the other output signal changes (S1000).
- the reference timing detection means 140 takes in the one output signal among the plurality of output signals output according to the test signal by the DUT 16 (S1010).
- the reference timing detection means 140 determines whether or not the value of the one output signal that has been acquired is a force that has also changed the previously acquired value force (S1020).
- the reference timing detection means 140 When the value of the one output signal has not changed (S 1020: No), the reference timing detection means 140 returns the process to S 1010 and executes the capture of the one output signal again. On the other hand, when the value of the one output signal has changed (S1020: Yes), the reference timing detection means 140 detects the changed timing as the reference timing (S1030).
- the strobe generating means 162 generates a strobe signal at the timing when the set minimum time has elapsed from the detected reference timing (S1040).
- the comparator 164 captures the other output signal among the plurality of output signals output from the DUT 160 at the timing indicated by the generated strobe signal (S1050).
- the identification unit 180 determines whether or not the value of the one other output signal that has been taken in matches the expected value held in the expected value holding unit 170 (S1060). When the value of the other output signal matches the expected value (S1060: Yes), the identification unit 180 identifies the electronic device that is the DUT 16 as a good product (S1070). On the other hand, when the value of the other one output signal does not match the expected value (S1060: No), the identification unit 180 identifies the electronic device that is the DUT 16 as a defective product (S1080).
- the correlation By testing the electronic device based on the above, it is possible to test with higher accuracy and more flexibility whether or not the electronic device performs the expected operation. In addition, by testing electronic devices according to the process flow shown in this figure Electronic devices that perform the expected operations can be selected with higher accuracy and more flexibility.
- FIG. 4 is a block diagram showing an example of a functional configuration of the test simulation system 20 according to the second embodiment of the present invention.
- the test simulation system 20 includes a test simulator control means 22, a test simulator 24, and a device simulator 26.
- the test simulator 24 simulates the operation of the test apparatus 14 according to the first embodiment of the present invention described with reference to FIGS. 1 to 3 by software. Specifically, the test simulator 24 provides a test signal to the device simulator 26 that simulates the operation of the electronic device, and also outputs a plurality of output signals output from the device simulator 26 according to the test signal. To see if the electronic device performs the expected operation.
- the test simulator 24 includes a pattern generating means 100, a timing generating means 110, a wave forming means 120, a driver 130, a reference timing detecting means 140, a setting means 150, an acquisition means 160, an expected value holding means 170, and Identification means 180 is provided.
- the members of the test simulator 24 shown in this figure have substantially the same functions as the members having the same reference numerals of the test apparatus 14 shown in FIG. To do.
- each member included in the test simulator 24 operates by simulating the corresponding function of each member included in the test apparatus 14 by software.
- the test simulator 24 is a device that receives the control of the test simulator control means 22 instead of the test control device 12 and that simulates the electronic device by software instead of the actual DUT 16 of the electronic device. Test the electronic device by testing simulator 26.
- FIG. 5 is a block diagram showing an example of the configuration of the test system 30 according to the third embodiment of the present invention.
- the test system 30 includes a test control device 32, a test device 34, and a DUT 36.
- the test system 30 tests the DUT 36, which is an electronic device, using the test apparatus 34.
- the test control device 32 controls the test device 34 to cause the test device 34 to execute the test of the DUT 36.
- the test apparatus 34 provides the test signal to the DUT 36 and compares the output signals output from the DUT 36 in response to the test signal with the expected values to determine whether the DUT 36 performs the expected operation. Test for no.
- the DUT 36 generates a plurality of output signals according to the test signal given from the test apparatus 34, and outputs each of the plurality of output signals using each of the plurality of pins provided in the DUT 36.
- the test apparatus 34 performs processing for comparing each of a plurality of output signals output from the DUT 36 with expected values, as in a functional test using a conventional test apparatus. By testing the DUT 36 independently for each output signal, the correlation between the timings at which the output signals change among the multiple output signals can be tested. The purpose is to identify with high accuracy
- the test apparatus 34 includes a pattern generating means 300, a timing generating means 310, a waveform shaping means 320, a driver 330, a reference timing detecting means 340, an elapsed time detecting means 350, a comparator 360, a setting means 370, an expected value. Holding means 380 and identification means 390 are provided.
- the pattern generation means 300 generates a test signal pattern to be given to the DUT 36 based on the control of the test control device 32, and outputs the generated test signal pattern to the waveform shaping means 320.
- the pattern generation means 300 generates information indicating the expected value of the output signal output by the DUT 36 when the test signal corresponding to the generated test signal pattern is given, and expects the generated information.
- the timing generation means 310 Based on the control of the test control device 32, the timing generation means 310 generates a timing to give a test signal to the DUT 36, and information indicating the timing is used as the waveform shaping means 320, the reference timing detection means 340, and the expected value. Output to holding means 380.
- the waveform shaping means 320 receives the test signal pattern received from the pattern generation means 300 and to be applied to the DUT 36, and the test signal received from the timing generation means 310 to the DUT 36. Based on the information indicating the timing at which the test signal is to be applied, the waveform of the test signal to be applied to the DUT 36 is formed and output to the driver 330.
- the driver 330 provides the DUT 36 with a test signal that also receives the waveform shaping means 320 force.
- the test apparatus 34 may have a plurality of pin cards corresponding to each of the plurality of pins provided in the DUT 36, and each of the drivers 330 provided for each pin force mode is used. Different test signals may be applied to each of the plurality of pins.
- the DUT 36 generates a plurality of output signals according to the given test signal, and outputs the generated output signals to the reference timing detection means 340, the elapsed time detection means 350, and the comparator 360.
- the reference timing detection means 340 detects that one of the plurality of output signals output from the DUT 36 has changed. For example, the reference timing detection unit 340 generates a plurality of strobe signals, captures the value of the one output signal in accordance with each of the plurality of strobe signals, and the captured value is the previously acquired value power. It may be detected that the one output signal has changed depending on whether or not the force has changed. Then, the reference timing detection unit 340 outputs information indicating the timing at which the one output signal has changed to the elapsed time detection unit 350.
- the elapsed time detection means 350 correlates the timing at which each output signal changes between one output signal and the other output signal among the plurality of output signals output from the DUT 36.
- the reference timing detection means 340 detects an elapsed time from when the change of the one output signal is detected until the other output signal is changed.
- the elapsed time detection unit 350 generates a plurality of strobe signals when the reference timing detection unit 340 detects a change in the one output signal, and generates another strobe signal according to each of the plurality of strobe signals. Capture the value of one output signal
- the elapsed time detecting means 350 calculates the elapsed time from when the reference timing detecting means 340 detects the change of the one output signal until the value of the other one output signal changes. Detect as. Then, the elapsed time detection means 350 outputs information indicating the detected elapsed time to the identification means 390.
- the comparator 360 compares each of the output signals output from the DUT 36 with a reference voltage, and determines a logical value indicating the comparison result. Output.
- the setting means 370 includes a case where, among a plurality of output signals output from the DUT 36, a timing at which each output signal changes is correlated between one output signal and the other output signal. In addition, a minimum time from when the one output signal changes until the other output signal changes is set in advance based on, for example, control of the test control device 32. Then, the setting means 370 outputs information indicating the set minimum time to the identification means 390. Based on the information indicating the expected value received from the pattern generating means 300 and the timing at which the test signal received from the timing generating means 310 should be given to the DUT 36, the expected value holding means 380 The expected value of the output signal to be output correspondingly is generated, and the generated expected value is stored in advance.
- the identification means 390 Based on the elapsed time received from the elapsed time detection means 350 and the comparison result received from the comparator 360, the identification means 390 identifies pass / fail of the electronic device that is the DUT 36. Specifically, the identification unit 390 identifies the DUT 36 as a defective product when the elapsed time received from the elapsed time detection unit 350 is shorter than the minimum time received from the setting unit 370. The identification unit 390 also disables the DUT 36 when the logical value indicating the comparison result between the output signal and the reference voltage received from the comparator 360 does not match the expected value held in the expected value holding unit 380. It may be identified as a good product. Then, the identification means 390 outputs the result of quality determination for the DUT 36 to the test control device 32 and presents it to the user or the like.
- the test apparatus 34 when the timings at which the output signals change are correlated among the plurality of output signals output from the electronic device.
- the electronic device can be tested based on the correlation.
- each output signal is preliminarily set even if the value of each output signal at a predetermined timing matches the expected value. If the specified correlation is not satisfied, i.e., the time from when one output signal changes until the other output signal changes is shorter than the preset minimum time, the electronic device Can be identified as defective.
- each output signal at a predetermined timing is determined.
- the minimum time set by the setting means 370 is the setup time of one output signal for another electronic device that operates by receiving an output signal from the electronic device that is the DUT 36, or one other time It may be one of the output signal hold times.
- FIG. 6 is a flowchart showing an example of a process flow in the electronic device test method using the test apparatus 34 according to the third embodiment of the present invention.
- the setting means 370 presets the minimum time from when one output signal changes among the plurality of output signals output by the DUT 36 until the other output signal changes (S 1100).
- the reference timing detection means 340 takes in the one output signal among the plurality of output signals output according to the test signal by the DUT 36 (S1110).
- the reference timing detection means 340 determines whether or not the value of the one output signal that has been acquired is a force that has also changed the previously acquired value force (S 1120).
- the reference timing detection means 340 If the value of the one output signal has not changed (S1120: No), the reference timing detection means 340 returns the process to S1110 and executes the capture of the one output signal again. On the other hand, when the value of the one output signal has changed (S1120: Yes), the reference timing detection means 340 detects the changed timing as the reference timing (S1130).
- the elapsed time detecting means 350 takes in the other output signal among the plurality of output signals output according to the test signal by the DUT 36 (S1140).
- the elapsed time detecting means 350 determines whether or not the value of the other one of the acquired output signals has changed the previously acquired value force (S 1150).
- the elapsed time detecting means 350 returns the process to S1140, and again takes in the other one output signal.
- the elapsed time detection means 350 uses the reference timing.
- the elapsed time from the timing to the timing when the value of the other one output signal changes is detected (S1160). Subsequently, the identification unit 390 determines whether or not the detected elapsed time is shorter than the set minimum time (S1170). When the elapsed time is not shorter than the minimum time (S1170: No), the identification unit 390 identifies the electronic device that is the DUT 36 as a good product (S1180). On the other hand, when the elapsed time is shorter than the minimum time (S1170: Yes), the identification unit 390 identifies the electronic device that is the DUT 36 as a defective product (S1190).
- the correlation By testing the electronic device based on the above, it is possible to test with higher accuracy and more flexibility whether or not the electronic device performs the expected operation. In addition, by testing an electronic device according to the processing flow shown in this figure, an electronic device that performs an expected operation can be selected and produced with higher accuracy and more flexibility.
- FIG. 7 is a block diagram showing an example of a functional configuration of a test simulation system 40 according to the fourth embodiment of the present invention.
- the test simulation system 40 includes a test simulator control means 42, a test simulator 44, and a device simulator 46.
- the test simulator 44 simulates the operation of the test apparatus 34 according to the third embodiment of the present invention described with reference to FIGS. 5 and 6 by software. Specifically, the test simulator 44 provides a test signal to the device simulator 46 that simulates the operation of the electronic device, and outputs a plurality of output signals output from the device simulator 46 in response to the test signal, respectively. To see if the electronic device performs the expected operation.
- the test simulator 44 includes a pattern generating means 300, a timing generating means 310, a wave forming means 320, a driver 330, a reference timing detecting means 340, an elapsed time detecting means 350, a comparator 360, a setting means 370, an expected value holding means. 380 and identification means 390.
- the members of the test simulator 44 shown in this figure have substantially the same functions as the members having the same reference numerals of the test apparatus 34 shown in FIG. To do. However, each of the members that the test simulator 44 has is Each function of the corresponding member of the test apparatus 34 is operated by simulating by software.
- the test simulator 44 is controlled by the test simulator control means 42 instead of the test control device 32, and is a device that simulates the electronic device by software instead of the DUT 36 which is the actual electronic device. The electronic device is tested by testing simulator 46.
- the timings at which the output signals change among the plurality of output signals output from the device simulator that simulates the electronic device are correlated.
- the electronic device can be tested based on the correlation. This makes it possible to perform a simulation test of an electronic device with higher accuracy and more flexibility than a test simulator that simulates a conventional test apparatus that performs only functional tests.
- FIG. 8 is a block diagram showing an example of a functional configuration of a test simulation system 50 according to the fifth embodiment of the present invention.
- the test simulation system 50 includes a test simulator control means 52, a test simulator 54, and a device simulator 56.
- the test simulator 54 simulates the operation of a test apparatus for testing an electronic device by software. Specifically, the test simulator 54 provides a plurality of test signals to a device simulator 56 that simulates the operation of the electronic device, and also outputs a plurality of output signals output from the device simulator 56 in response to the plurality of test signals. By comparing each with the expected value, the ability to correctly test the electronic device is tested. That is, the test simulator 54 tests a test signal used when testing an electronic device, that is, a test program.
- the device simulator 56 simulates the operation of an electronic device provided with a plurality of pins by software, and each of a plurality of test signals corresponding to each of the plurality of pins given from the test simulator 54. In response to this, a plurality of output signals are output.
- the test simulator 54 tests the correlation between timings at which the test signals change among a plurality of test signals given to the device simulator 56, thereby obtaining the device simulator 56. Simulates electronic data The purpose of this test is to test whether Neus is capable of being tested correctly using the multiple test signals with higher V accuracy.
- the plurality of test signals whose timings of change described in this example are correlated with, for example, a signal designating an address as a test signal to the device simulator 56 that simulates DRAM
- the RAS signal indicating the timing of inputting the address value indicated by the address signal as a row address
- the CAS signal indicating the timing of inputting the address value indicated by the address signal as a column address.
- the test simulator 54 includes a pattern generation unit 500, a timing generation unit 505, a wave forming unit 510, a reference timing acquisition unit 515, a setting unit 520, a test signal detection unit 525, a notification unit 530, a driver 535, a comparator 540, Expected value holding means 545 and identification means 550 are provided.
- the pattern generation means 500 generates a test signal pattern to be given to the device simulator 56 based on the control of the test simulator control means 52, and outputs the generated test signal pattern to the waveform shaping means 510.
- the pattern generation means 500 may generate a plurality of test signals corresponding to each of a plurality of pins provided in the electronic device simulated by the device simulator 56.
- the pattern generation means 500 generates information indicating the expected value of the output signal output from the device simulator 56 when the test signal corresponding to the generated test signal pattern is given, and the generated information is displayed. Output to expected value holding means 545.
- the timing generation means 505 Based on the control of the test simulator control means 52, the timing generation means 505 generates a timing at which a test signal should be given to the device simulator 56, and information indicating the timing is obtained by the waveform shaping means 510 and the reference timing acquisition. Output to means 515 and expected value holding means 545.
- the waveform shaping means 510 receives the pattern of the test signal to be given to the device simulator 56 received from the pattern generation means 500 and the information received from the timing generation means 505 indicating the timing to give the test signal to the device simulator 56. Based on this, waveforms of a plurality of test signals to be given to the device simulator 56 are formed and output to the reference timing acquisition means 515 and the test signal detection means 525.
- the reference timing acquisition unit 515 includes a plurality of test signals received from the waveform shaping unit 510. The time when one test signal changes among the plurality of test signals is obtained based on the number. For example, the reference timing acquisition unit 515 repeatedly captures the value of the one test signal at a predetermined time interval, and the one test signal depends on whether or not the captured value has changed the previously acquired value force. Is detected, and the detected time is acquired. Then, the reference timing acquisition unit 515 outputs information indicating the acquired time to the test signal detection unit 525.
- the setting means 520 has a timing at which each test signal changes between one test signal and the other test signal among the plurality of test signals output by the waveform shaping means 510. When there is a correlation, a minimum time from when the one test signal is changed to when the other test signal is changed is set in advance based on, for example, control of the test simulator control means 52. Then, the setting means 520 outputs information indicating the set minimum time to the test signal detection means 525.
- the test signal detection unit 525 receives a test signal to be given to the device simulator 56 from the waveform shaping unit 510. Then, the test signal detection means 525 receives another one at the timing when the minimum time set by the setting means 520 has elapsed from the time when one test signal acquired by the reference timing acquisition means 515 changes. Detect the value of the test signal. Then, the test signal detection unit 525 outputs the value of the detected test signal to the notification unit 530. Further, the test signal detecting means 525 outputs each of the test signals received from the waveform shaping means 510 to the driver 535.
- the notification means 530 is simulated by the device simulator 56 by using the current test signal based on the value of the other test signal detected by the test signal detection means 525. Determine whether the tested electronic device can be tested correctly. Specifically, the notification means 530 is used when the timing at which each test signal changes is correlated between one test signal and the other test signal among the plurality of test signals. The value of the other one test signal detected by the test signal detecting means 525 is determined in advance as a value to be taken by the other one test signal after the minimum time has elapsed since the change of the one test signal. If the force does not match the stored value, the current test signal will not test the electronic device correctly. The test simulator control means 52 is notified to that effect.
- the value stored in advance as a value to be taken by another one of the test signals is, for example, generated by the pattern generation unit 500 based on the control of the test simulator control means 52, and the notification unit 530. It may be a value stored in advance.
- the driver 535 gives a plurality of test signals received from the test signal detection means 525 to the device simulator 56. Then, the device simulator 56 generates an output signal according to the given plurality of test signals, and outputs the generated output signal to the comparator 540.
- the comparator 540 compares the output signal received from the device simulator 56 with a reference voltage, and outputs a logical value as a comparison result to the identification unit 550. When the device simulator 56 outputs the output signal as a logical value instead of an analog value, the comparator 540 outputs the received logical value as it is to the identification unit 550 without performing the comparison process described above. Good.
- the expected value holding means 545 is based on the information indicating the expected value received from the pattern generating means 500 and the timing at which the test signal received from the timing generating means 505 should be given to the device simulator 56. 56 generates an expected value of the output signal output corresponding to the test signal, and holds the generated expected value in advance.
- the identification unit 550 Based on the comparison result received from the comparator 540, the identification unit 550 identifies whether the electronic device simulated by the device simulator 56 or the quality of the test program. Specifically, identification means 550 determines that the logical value indicating the comparison result between the output signal and the reference voltage received from comparator 540 does not match the expected value held in expected value holding means 545. Identify electronic devices or test programs as defective. Then, the identification unit 550 outputs the result of quality discrimination for the electronic device or the test program to the test simulator control unit 52 and presents it to the user or the like.
- the timing at which each test signal changes is correlated among the plurality of test signals applied to the device simulator 56 that simulates the electronic device. In this case, whether or not the electronic device can be correctly tested using the test signal can be tested based on the correlation. As a result, the value of each test signal at a predetermined timing Even if the values match the values to be taken, the respective test signals do not satisfy the predetermined correlation, i.e., the minimum time set in advance after one test signal changes. If the value of one other test signal at the time when the time elapses is different from the value to be taken, it can be determined that these test signals cannot correctly test the electronic device.
- test simulator 54 whether or not the test of the electronic device can be correctly performed can be tested with higher accuracy and more flexibility than the test simulator that performs the conventional simulation test. Is possible.
- the test apparatus includes a pattern generation unit 500, a timing generation unit 505, a waveform shaping unit 510, a reference timing acquisition unit 515, a setting unit 520, a test signal detection unit 525, a notification unit 530, a driver 535, and a comparator 540.
- the expected value holding means 545 and the identification means 550 may be provided.
- each of the members of the test apparatus has substantially the same function as each of the members having the same reference numerals that the test simulator 54 shown in the figure has.
- the test apparatus gives a plurality of test signals to an actual electronic device, and outputs a plurality of output signals output from the electronic device in response to the plurality of test signals. Compare with the value to test whether the electronic device performs the expected operation. Further, the test apparatus may test the electronic device based on the control of the test control apparatus instead of the test simulator control means 52. Then, the test apparatus performs processing similar to the processing described as the processing of the test simulator 54 in this figure, thereby changing the timing at which each test signal changes among a plurality of test signals applied to the electronic device. Can be tested based on the correlation of the ability to correctly test the electronic device using the test signal.
- FIG. 9 shows an example of a test signal used in the test simulator 54 according to the fifth embodiment of the present invention.
- test signal A is one of the test signals described in FIG.
- Test signal B is another test signal described in FIG.
- test signal A and test signal B correlate with the timing at which they change.
- test signal B does not change until a preset minimum time has elapsed after test signal A changes.
- the timing at which the test signal A changes is timing T1
- the timing when the minimum time set by the setting means 520 has elapsed from timing T1 is timing T2.
- the value that test signal B should take at timing T2 is L logic. Therefore, when the test signal B indicates the H logic at the timing T2, the notification unit 530 cannot correctly test the electronic device simulated by the device simulator 56 using the test signal shown in the figure.
- the minimum time may be either one test signal, that is, the setup time of the test signal A, or another one test signal, that is, the hold time of the test signal B.
- the test simulator 54 power device simulator 56 that simulates DRAM, an address signal and a RAS signal indicating the timing of inputting the address value indicated by the address signal as a row address are used as test signals.
- the minimum time may be the setup time of the test signal A.
- the test signal A is a RAS signal and the test signal B is an address signal
- the minimum time may be a hold time of the test signal B for the electronic device simulated by the device simulator 56.
- FIG. 10 uses a test simulation system 50 according to the fifth embodiment of the present invention.
- 5 is a flowchart showing an example of a processing flow in an electronic device test simulation method and a production method.
- the setting means 520 sets the minimum time from when one test signal changes among the plurality of test signals until the other one test signal changes (S1200).
- the reference timing acquisition means 515 detects the value of the one test signal among the plurality of test signals (S1205).
- the reference timing acquisition means 515 determines whether or not the detected value of the one test signal is a force that also changes the previously detected value force (S 1210). If the value of the one test signal has changed!
- the reference timing acquisition means 515 returns the processing to S1205 and detects the value of the one test signal again. .
- the reference timing acquisition means 515 acquires the changed time (S1215).
- the test signal detection means 525 detects the value of the other one test signal at the timing when the set minimum time has elapsed from the time when the value of the one test signal has changed. (S1220). Subsequently, the notification means 530 determines whether or not the detected value of the other test signal matches the value to be taken (S 1225). When it is determined that the value of the other one test signal does not match the value to be taken (S 1225: No), the notification means 530 uses the electronic signal simulated by the device simulator 56 for these test signals. It is determined that the device cannot be tested correctly and a notification to that effect is sent (S 1230).
- the test simulator control means 52 causes the user to correct the test signal by notifying the user of the notification content received from the notification means 530, and stores the corrected test signal pattern. (S1235). Then, the test simulation system 50 returns the process to S1205, and again acquires the time at which one test signal has changed in the reference timing acquisition unit 515, and another one test signal in the test signal detection unit 525. The process of detecting the value of is repeated.
- the actual test equipment replaces the test simulator 54 with these test signals.
- the test apparatus gives a test signal to the actual electronic device so that the value of the output signal obtained by the electronic device power is the value of the test signal. It is determined whether or not the force generated according to the pattern matches the expected value of the output signal (S 1245).
- the test apparatus identifies the electronic device as a non-defective product (S1250).
- the test apparatus identifies the electronic device as a defective product (S1255).
- test simulation method according to the flow of processing from SI 200 to SI 235 in this figure, when the timings at which the test signals change are correlated among multiple test signals, By verifying the test signal based on the correlation, it is possible to determine whether the electronic device can be tested correctly using the test signal. Even if it is determined that the electronic device cannot be correctly tested, the user can test the electronic device correctly by repeatedly correcting the pattern of the test signal and re-verifying the pattern. The pattern of the test signal that can be generated can be generated with high accuracy.
- by conducting a simulation test and an actual test of an electronic device according to the processing flow shown in this figure it is possible to select whether or not the electronic device is a non-defective product with higher accuracy and more flexibility. Electronic devices can be produced.
- FIG. 11 is a block diagram showing an example of a functional configuration of a test simulation system 60 according to the sixth embodiment of the present invention.
- the test simulation system 60 includes a test simulator control means 62, a test simulator 64, and a device simulator 66.
- Test simulator 64 includes pattern generation means 500, timing generation means 505, waveform shaping means 510, reference timing acquisition means 515, setting means 620, elapsed time detection means 625, notification means 630, driver 535, comparator 540, expectation Value holding means 545 and identification means 550 are provided.
- members having the same reference numerals as those of the test simulator 54 shown in FIG. 8 have substantially the same functions as the corresponding members of the test simulator 54.
- the explanation is omitted except for the differences.
- the test simulator 64 receives the control of the test simulator control means 62 instead of the test simulator control means 52 and tests the device simulator 66 instead of the device simulator 56.
- the setting means 620 has a timing at which each test signal changes between one test signal and another test signal among the plurality of test signals output by the waveform shaping means 510. When there is a correlation, a minimum time from when the one test signal is changed to when the other test signal is changed is set in advance based on, for example, control of the test simulator control means 62. Then, the setting unit 620 outputs information indicating the set minimum time to the notification unit 630.
- the elapsed time detecting means 625 receives a test signal to be given to the device simulator 66 from the waveform shaping means 510. Then, the elapsed time detection means 625 detects the elapsed time from the time when one test signal changes, acquired by the reference timing acquisition means 515, until the other test signal changes. For example, the elapsed time detecting means 625 repeatedly fetches the value of the other one test signal at a predetermined time interval from the time when the one test signal changes, and the fetched value was fetched last time. Value Force Depending on whether or not the force has changed, it is detected that the other test signal has changed.
- the elapsed time detecting means 625 detects the elapsed time from the time when the one test signal changes until the other one test signal changes as the elapsed time. Then, the elapsed time detection unit 625 outputs information indicating the detected elapsed time to the notification unit 630.
- the notification means 630 uses the test simulator 64 force current test signal to correctly identify the electronic device being simulated by the device simulator 66. Determine whether you can test. Specifically, when the elapsed time is shorter than the minimum time received from the setting unit 620, the notification unit 630 determines that the electronic device cannot be correctly tested with the current test signal, and tests that fact. Notify the simulator control means 62.
- the timings at which the test signals change are correlated among the plurality of test signals applied to the device simulator 66 that simulates the electronic device. In this case, whether or not the electronic device can be correctly tested by using the test signal can be tested based on the correlation. As a result, each test at a predetermined timing Even if the value of the signal is consistent with the value to be taken, each test signal does not satisfy the predetermined correlation, i.e. one test signal has changed and the other If the elapsed time until one test signal changes is shorter than the preset minimum time, it can be determined that the electronic device cannot be correctly tested with these test signals! / .
- test simulator 64 it is possible to test whether or not the ability to correctly test an electronic device is higher and more flexible than a test simulator that performs a conventional simulation test. can do.
- the minimum time set by the setting means 620 may be a difference between the setup time of one test signal or the hold time of another test signal! /.
- the force described for the test simulator 64 that simulates the operation of the test apparatus for testing the electronic device by software using FIG. 11 instead of the actual test apparatus force.
- the same processing as in the simulator 64 may be performed.
- the test apparatus includes pattern generation means 500, timing generation means 505, waveform shaping means 510, reference timing acquisition means 515, setting means 620, elapsed time detection means 625, notification means 630, driver 535, A comparator 540, expected value holding means 545, and identification means 550 may be provided.
- each of the members included in the test apparatus has substantially the same function as each of the members having the same reference numerals included in the test simulator 64 shown in the figure.
- the test apparatus gives a plurality of test signals to an actual electronic device, and outputs a plurality of output signals output from the electronic device according to the plurality of test signals, respectively. Test whether the electronic device performs the expected operation by comparing with the expected value.
- the test apparatus may test the electronic device based on the control of the test control apparatus instead of the test simulator control means 62. Then, the test apparatus performs the same processing as the processing described as the processing of the test simulator 64 in this figure, thereby If the timing at which each test signal changes is correlated among multiple test signals given to the child device, whether or not the electronic device can be correctly tested using the test signal You can test based on the correlation!
- FIG. 12 is a flowchart showing an example of a processing flow in a test simulation method and a production method for an electronic device using a test simulation system 60 according to the sixth embodiment of the present invention.
- the setting means 620 sets the minimum time from when one test signal changes among the plurality of test signals until the other output signal changes (S 1300).
- the reference timing acquisition unit 515 detects the value of the one test signal among the plurality of test signals (S1305).
- the reference timing acquisition means 515 determines whether or not the detected value of the one test signal is a force that also changes the previously detected value force (S 1310). If the value of the one test signal has changed!
- the reference timing acquisition means 515 returns the process to S1305 and detects the value of the one test signal again. .
- the reference timing acquisition means 515 acquires the changed time (S1315).
- the elapsed time detecting means 625 detects the value of another test signal among the plurality of test signals (S1320).
- the elapsed time detecting means 625 determines whether or not the value of the detected other one of the test signals is a force that also changes the previously detected value force (S1325).
- the elapsed time detecting means 625 returns the process to S1320 and again sets the value of the other one test signal. To detect.
- the elapsed time detection means 625 changes the value of the other test signal after the value of the one test signal changes.
- the elapsed time until the value of is changed is detected (S1330).
- the notification unit 630 determines whether or not the detected elapsed time is shorter than a preset minimum time (S 1335). If it is determined that the elapsed time is shorter than the minimum time (S1335: Yes), the notification means 530 determines that the electronic device simulated by the device simulator 66 cannot be correctly tested with these test signals. Then, this is notified (S1340). Subsequently, the test simulator control means 62 causes the user to correct the test signal by, for example, presenting the notification content received from the notification means 630 to the user, so that the test signal is corrected. Stored (SI 345). Then, the test simulation system 60 returns the process to S1305, and again acquires the time at which one test signal has changed in the reference timing acquisition means 515, and the elapsed time detection process in the elapsed time detection means 625. Repeatedly.
- the test apparatus uses these test signal patterns to generate a device simulator.
- the actual electronic device simulated by 66 is tested (S 1350).
- the test apparatus gives the test signal to the actual electronic device so that the value of the output signal obtained by the electronic device force is generated according to the pattern of the test signal. (S1355).
- the test apparatus identifies the electronic device as a non-defective product (S1360).
- the test apparatus identifies the electronic device as a defective product (S1365).
- test simulation method when the timing at which each test signal changes is correlated among a plurality of test signals, By verifying the test signal based on the correlation, it is possible to determine whether the electronic device can be tested correctly using the test signal. Even when it is determined that the electronic device cannot be correctly tested, the user can correctly test the electronic device by repeatedly correcting the pattern of the test signal and re-verifying the pattern. The pattern of the test signal that can be generated can be generated with high accuracy.
- by conducting a simulation test and an actual test of an electronic device according to the processing flow shown in this figure it is possible to select whether or not the electronic device is a non-defective product with higher accuracy and more flexibility. Electronic devices can be produced.
- FIG. 13 is a block diagram showing an example of the hardware configuration of the computer 1500 according to the embodiment of the present invention.
- a computer 1500 according to an embodiment of the present invention includes a CPU peripheral unit having a CPU 1505, a RAM 1520, a graphic controller 1575, and a display device 1580 connected to each other by a host controller 1582, and an input / output controller.
- the host controller 1582 connects the RAM 1520 to the CPU 1505 and the graphic controller 1575 that access the RAM 1520 at a high transfer rate.
- the CPU 1505 operates based on the programs stored in the ROM 1510 and the RAM 1520 and controls each part.
- the graphic 'controller 1575 acquires image data generated on the frame buffer provided by the CPU 1505 and the like in the RAM 1520 and displays it on the display device 1580.
- the graphic controller 1575 may include a frame notifier for storing image data generated by the CPU 1505 or the like.
- the input / output controller 1584 connects the host controller 1582 to the communication interface 1530, the hard disk drive 1540, and the CD-ROM drive 1560, which are relatively high-speed input / output devices.
- the communication interface 1530 communicates with other devices via a network.
- the hard disk drive 1540 stores programs and data used by the CPU 1505 in the computer 1500.
- CD-ROM drive 1560 reads CD-ROM 15 95 programs or data and provides them to hard disk drive 1540 via RAM 1520.
- the input / output controller 1584 is connected to the ROM 1510 and the flexible disk drive 1550 and the relatively low-speed input / output device of the input / output chip 1570.
- the ROM 1510 stores a boot program executed when the computer 1500 is started up, a program depending on the hardware of the computer 1500, and the like.
- the flexible disk drive 1550 reads a program or data from the flexible disk 1590 and provides it to the hard disk drive 1540 via the RA M1520.
- the input / output chip 1570 connects various input / output devices via a flexible disk 'drive 1550' and, for example, a parallel 'port, a serial' port, a keyboard 'port, a mouse' port, and the like.
- the test simulation program provided to the hard disk drive 1540 via the RAM 1520 is a description of a flexible disk 1590, a CD-ROM 1595, or an IC card. It is stored on the recording medium and provided by the user.
- the test simulation program is read from the recording medium, installed in the hard disk drive 1540 in the computer 1500 via the RAM 1520, and executed by the CPU 1505.
- the test simulation program installed and executed on the computer 1500 works on the CPU 1505 and the like to make the computer 1500 function as the test simulator (24, 44, 54, 64) described with reference to FIGS.
- the programs described above may be stored in an external storage medium.
- storage media flexible disk 1590, CD-ROM 1595, optical recording media such as DVD and PD, magneto-optical recording media such as MD, tape media, semiconductor memory such as IC cards, etc.
- a storage device such as a node disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 1500 via the network.
- FIG. 1 is a block diagram showing an example of a functional configuration of a test system 10 according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing an example of an output signal of the DUT 16 according to the first embodiment of the present invention.
- FIG. 3 is a flowchart showing an example of a process flow in the electronic device test method using the test apparatus 14 according to the first embodiment of the present invention.
- FIG. 4 is a block diagram showing an example of a functional configuration of a test simulation system 20 according to a second embodiment of the present invention.
- FIG. 5 is a block diagram showing an example of a configuration of a test system 30 according to a third embodiment of the present invention.
- FIG. 6 shows a method for testing an electronic device using a test apparatus 34 according to the third embodiment of the present invention. It is a flowchart which shows an example of the flow of a process in.
- FIG. 7 is a block diagram showing an example of a functional configuration of a test simulation system 40 according to a fourth embodiment of the present invention.
- FIG. 8 is a block diagram showing an example of a functional configuration of a test simulation system 50 according to a fifth embodiment of the present invention.
- FIG. 9 is a diagram showing an example of a test signal used in a test simulator 54 according to the fifth embodiment of the present invention.
- FIG. 10 is a flowchart showing an example of a processing flow in an electronic device test simulation method and a production method using a test simulation system 50 according to a fifth embodiment of the present invention.
- FIG. 11 is a block diagram showing an example of a functional configuration of a test simulation system 60 according to a sixth embodiment of the present invention.
- FIG. 12 is a flowchart showing an example of a processing flow in an electronic device test simulation method and a production method using a test simulation system 60 according to a sixth embodiment of the present invention.
- FIG. 13 is a block diagram showing an example of a hardware configuration of a computer 1500 according to the embodiment of the present invention. Explanation of symbols
- test system 10 test system, 12 test control device, 14 test device, 16 DUT, 20 test simulation system, 22 test simulator control means, 24 test simulator, 26 device simulator, 30 test system, 32 test control device, 34 test device , 36 DU T, 40 test simulation system, 42 test simulator control means, 44 test simulator, 46 device simulator, 50 test simulation system, 52 test simulator control means, 54 test simulator, 56 device simulator, 60 test simulator Chillon system, 62 test simulator control means, 64 test simulator, 66 device simulator, 100 pattern generation means, 110 timing generation means, 120 wave forming means, 130 driver, 140 reference timing detection means, 150 setting means, 160 acquisition means , 16 2 Strobe generation means, 164 comparator, 170 expected value holding means, 180 discriminating means, 300 pattern generating means, 310 timing generating means, 320 wave forming means, 330 driver, 340 reference timing detecting means, 350 elapsed time detecting means, 360 comparator, 370 setting means, 380 expected value holding means, 390 identification Means, 500 pattern generation means, 505 timing generation means, 510 wave
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06728703A EP1870725B1 (en) | 2005-03-07 | 2006-03-07 | Test device, test method, electronic device manufacturing method, test simulator, and test simulation method |
DE602006016417T DE602006016417D1 (de) | 2005-03-07 | 2006-03-07 | Prüfeinrichtung, prüfverfahren, herstellungsverfahren für elektronische bauelemente, prüfsimulator und prüfsimulationsverfahren |
CN2006800071710A CN101133340B (zh) | 2005-03-07 | 2006-03-07 | 测试装置、测试方法、电子元件的生产方法、测试模拟器以及测试模拟方法 |
US11/395,094 US7532994B2 (en) | 2005-03-07 | 2006-03-31 | Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method |
Applications Claiming Priority (2)
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JP2005062044A JP4820560B2 (ja) | 2005-03-07 | 2005-03-07 | 試験装置、試験方法、電子デバイスの生産方法、試験シミュレータ、及び試験シミュレーション方法 |
JP2005-062044 | 2005-03-07 |
Related Child Applications (1)
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US11/395,094 Continuation US7532994B2 (en) | 2005-03-07 | 2006-03-31 | Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method |
Publications (1)
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WO2006095715A1 true WO2006095715A1 (ja) | 2006-09-14 |
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PCT/JP2006/304334 WO2006095715A1 (ja) | 2005-03-07 | 2006-03-07 | 試験装置、試験方法、電子デバイスの生産方法、試験シミュレータ、及び試験シミュレーション方法 |
Country Status (8)
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US (1) | US7532994B2 (ja) |
EP (1) | EP1870725B1 (ja) |
JP (1) | JP4820560B2 (ja) |
KR (1) | KR20070116245A (ja) |
CN (1) | CN101133340B (ja) |
DE (1) | DE602006016417D1 (ja) |
TW (1) | TWI401448B (ja) |
WO (1) | WO2006095715A1 (ja) |
Families Citing this family (9)
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JP2007017179A (ja) * | 2005-07-05 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体集積回路の検証方法および検査方法 |
US8067943B2 (en) * | 2009-03-24 | 2011-11-29 | Advantest Corporation | Test apparatus, calibration method, program, and recording medium |
US20130120010A1 (en) * | 2011-11-10 | 2013-05-16 | Qualcomm Incorporated | Power Measurement System for Battery Powered Microelectronic Chipsets |
KR101483519B1 (ko) | 2012-05-15 | 2015-01-16 | 삼성전자 주식회사 | 밀폐형 왕복동 압축기 |
KR101618822B1 (ko) * | 2014-10-29 | 2016-05-18 | (주)이노티오 | 스캔 테스트 시간 최소화 방법 및 그 장치 |
JP6688665B2 (ja) * | 2016-04-11 | 2020-04-28 | 横河電機株式会社 | 機器保全装置、機器保全方法、機器保全プログラム及び記録媒体 |
JP2017218975A (ja) * | 2016-06-08 | 2017-12-14 | 三菱電機株式会社 | 劣化診断装置 |
JP6832654B2 (ja) * | 2016-09-09 | 2021-02-24 | 東京エレクトロン株式会社 | 検査システムの調整方法およびそれに用いる補助エレメント |
TWI665565B (zh) * | 2018-04-03 | 2019-07-11 | 孕龍科技股份有限公司 | Signal pairing analysis method |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633879A (en) | 1996-01-19 | 1997-05-27 | Texas Instruments Incorporated | Method for integrated circuit design and test |
JP2000009809A (ja) * | 1998-06-26 | 2000-01-14 | Advantest Corp | 誤設定検出機能を具備したic試験装置 |
JP2000147062A (ja) * | 1998-11-10 | 2000-05-26 | Matsushita Electric Ind Co Ltd | 半導体検査装置および半導体検査方法 |
JP2001051025A (ja) * | 1999-08-12 | 2001-02-23 | Advantest Corp | 半導体試験用プログラムデバッグ装置 |
JP2002025294A (ja) * | 2000-07-06 | 2002-01-25 | Advantest Corp | 半導体デバイス試験方法・半導体デバイス試験装置 |
JP2002042498A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 半導体記憶装置、補助装置および試験装置 |
US6532561B1 (en) | 1999-09-25 | 2003-03-11 | Advantest Corp. | Event based semiconductor test system |
JP2003161767A (ja) * | 2001-11-27 | 2003-06-06 | Ando Electric Co Ltd | 半導体試験装置 |
JP2004125574A (ja) * | 2002-10-01 | 2004-04-22 | Advantest Corp | 試験装置、及び試験方法 |
JP2004272312A (ja) | 2003-03-05 | 2004-09-30 | Fuji Electric Device Technology Co Ltd | テスト装置及びテスト方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2952131B2 (ja) * | 1993-05-11 | 1999-09-20 | シャープ株式会社 | 半導体集積回路の試験装置 |
JP2001255357A (ja) * | 2000-01-07 | 2001-09-21 | Advantest Corp | テストパターン妥当性検証方法及びその装置 |
US7089517B2 (en) * | 2000-09-29 | 2006-08-08 | Advantest Corp. | Method for design validation of complex IC |
US7437261B2 (en) * | 2003-02-14 | 2008-10-14 | Advantest Corporation | Method and apparatus for testing integrated circuits |
JP4558405B2 (ja) * | 2004-08-17 | 2010-10-06 | 株式会社アドバンテスト | 試験エミュレータ、エミュレーションプログラム、及び半導体デバイス製造方法 |
-
2005
- 2005-03-07 JP JP2005062044A patent/JP4820560B2/ja not_active Expired - Fee Related
-
2006
- 2006-03-07 CN CN2006800071710A patent/CN101133340B/zh not_active Expired - Fee Related
- 2006-03-07 EP EP06728703A patent/EP1870725B1/en not_active Expired - Fee Related
- 2006-03-07 TW TW095107592A patent/TWI401448B/zh not_active IP Right Cessation
- 2006-03-07 DE DE602006016417T patent/DE602006016417D1/de active Active
- 2006-03-07 KR KR1020077022668A patent/KR20070116245A/ko not_active Application Discontinuation
- 2006-03-07 WO PCT/JP2006/304334 patent/WO2006095715A1/ja active Application Filing
- 2006-03-31 US US11/395,094 patent/US7532994B2/en not_active Expired - Fee Related
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633879A (en) | 1996-01-19 | 1997-05-27 | Texas Instruments Incorporated | Method for integrated circuit design and test |
JP2000009809A (ja) * | 1998-06-26 | 2000-01-14 | Advantest Corp | 誤設定検出機能を具備したic試験装置 |
US6226230B1 (en) | 1998-06-26 | 2001-05-01 | Advantest Corporation | Timing signal generating apparatus and method |
JP2000147062A (ja) * | 1998-11-10 | 2000-05-26 | Matsushita Electric Ind Co Ltd | 半導体検査装置および半導体検査方法 |
JP2001051025A (ja) * | 1999-08-12 | 2001-02-23 | Advantest Corp | 半導体試験用プログラムデバッグ装置 |
US6532561B1 (en) | 1999-09-25 | 2003-03-11 | Advantest Corp. | Event based semiconductor test system |
JP2002025294A (ja) * | 2000-07-06 | 2002-01-25 | Advantest Corp | 半導体デバイス試験方法・半導体デバイス試験装置 |
JP2002042498A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 半導体記憶装置、補助装置および試験装置 |
JP2003161767A (ja) * | 2001-11-27 | 2003-06-06 | Ando Electric Co Ltd | 半導体試験装置 |
JP2004125574A (ja) * | 2002-10-01 | 2004-04-22 | Advantest Corp | 試験装置、及び試験方法 |
JP2004272312A (ja) | 2003-03-05 | 2004-09-30 | Fuji Electric Device Technology Co Ltd | テスト装置及びテスト方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1870725A4 |
Also Published As
Publication number | Publication date |
---|---|
EP1870725B1 (en) | 2010-08-25 |
EP1870725A1 (en) | 2007-12-26 |
US20060247882A1 (en) | 2006-11-02 |
TWI401448B (zh) | 2013-07-11 |
EP1870725A4 (en) | 2009-01-07 |
CN101133340B (zh) | 2011-02-23 |
CN101133340A (zh) | 2008-02-27 |
JP2006242878A (ja) | 2006-09-14 |
DE602006016417D1 (de) | 2010-10-07 |
US7532994B2 (en) | 2009-05-12 |
KR20070116245A (ko) | 2007-12-07 |
TW200636272A (en) | 2006-10-16 |
JP4820560B2 (ja) | 2011-11-24 |
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