WO2006089272A2 - Selective deposition of embedded transient protection for printed circuit boards - Google Patents

Selective deposition of embedded transient protection for printed circuit boards Download PDF

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Publication number
WO2006089272A2
WO2006089272A2 PCT/US2006/005984 US2006005984W WO2006089272A2 WO 2006089272 A2 WO2006089272 A2 WO 2006089272A2 US 2006005984 W US2006005984 W US 2006005984W WO 2006089272 A2 WO2006089272 A2 WO 2006089272A2
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WO
WIPO (PCT)
Prior art keywords
transient protection
recited
printed circuit
circuit board
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/005984
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English (en)
French (fr)
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WO2006089272A3 (en
Inventor
George Dudnikov
Franz Gisin
Gregory Schroeder
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Sanmina Corp
Original Assignee
Sanmina SCI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanmina SCI Corp filed Critical Sanmina SCI Corp
Priority to JP2007553397A priority Critical patent/JP2008533699A/ja
Priority to CN200680004951.XA priority patent/CN101595769B/zh
Publication of WO2006089272A2 publication Critical patent/WO2006089272A2/en
Anticipated expiration legal-status Critical
Publication of WO2006089272A3 publication Critical patent/WO2006089272A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H05K1/0259—Electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/073—High voltage adaptations
    • H05K2201/0738—Use of voltage responsive materials, e.g. voltage switchable dielectric or varistor materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts

Definitions

  • PCBs Printed circuit boards, backplanes, midplanes, printed wiring boards, flex circuits, rigid flex-circuits, multi-chip modules (MCM), interposers and the like are herein referred to collectively as "PCBs”.
  • a via structure typically provides a conductive path between conductive layers in the z- axis direction (orthogonal to the x-y plane of a PCB).
  • Via holes are formed by a variety of techniques including but not limited to laser drilling, mechanical drilling, and techniques based on photo definition. Via holes are subsequently partially or wholly filled or coated with a conductive material, usually metal.
  • Such via structures may be blind, buried, through-hole and may or may not include pads on the conductive layers, as is well known to those skilled in the art of PCB design.
  • Sensitive components on a printed circuit board can be damaged by transient occurrences of electrostatic discharges (ESD).
  • ESD electrostatic discharges
  • An ESD is characterized by a rapid rise in the order of tens of kilovolts in a few picoseconds, for example.
  • Other transient phenomena with lower peak voltage levels and slower rise-times can also cause damage to the printed circuit board.
  • a sudden rise in voltage can be caused by a poorly grounded soldering iron, or a power switching relay, or a lightning strike on telecommunication lines that are connected to the printed circuit board.
  • FIG. IA is a schematic that illustrates a printed circuit board 102 protected by conductive guard rings 104.
  • Printed circuit board (PCB) 102 has a length L and a width W.
  • conductive guard rings 104 are added to the periphery of each outer layer of PCB 102 and one or more discrete transient protection devices can be attached to PCB 102.
  • the guard rings 104 are attached to the chassis ground at the location where I/O connectors 106 are mounted to PCB 102. Typically, when a person picks up a PCB, the person will initially touch the periphery of the PCB. By positioning guard rings 104 along the periphery of PCB 102, guard rings 104 re-direct undesired transient currents to chassis ground. Thus, detrimental currents are not allowed to flow to transient sensitive components on PCB 102. However, guard rings fail to protect interior surfaces 112 of PCB 102. Another form of transient protection is the use of discrete transient protection devices.
  • Discrete transient protection devices such as discrete transient protection devices 108 can be attached to PCB 102 at the location where signal and/or power lines enter PCB 102, such as connector 106.
  • discrete transient protection devices consume valuable real estate on the PCB.
  • U.S. Patent No. 6,657,532 discloses discrete over-voltage protection components made of a thin layer of neat dielectric polymer or glass positioned between a ground plane and an electric conductor.
  • U.S. Patent No. 6,657,532 also discloses discrete over-voltage protection components having multi-layers of variable voltage material.
  • Another non-limiting example of a discrete transient protection device is a resettable polymeric-positive-temperature- coefficient (PPTC) device. Like fuses, PPTC devices help protect circuitry from overcurrent damage. However, discrete PPTC devices consume valuable real estate on the PCB.
  • PPTC resettable polymeric-positive-temperature- coefficient
  • transient protection include on-chip transient protection devices 110, such as zener diodes, for example.
  • on-chip transient protection devices do not have sufficient capacity to effectively dissipate large transient events.
  • Both discrete and on-chip transient protection devices often have excessive amounts of intrinsic capacitance that makes such devices unsuitable for use in high speed applications.
  • the primary protection mechanism of both discrete and on-chip transient protection devices is through the conversion of undesired transient energy into heat. Thus, large transient magnitudes and/or repeated exposure to large transient magnitudes are likely to result in over-heating that in turn results in performance degradation of such devices.
  • FIG. IB is a cross section 150 of the PCB 102 of FIG. IA taken at IB.
  • Cross section 150 shows that the PCB comprises multi-layers 160 of material.
  • Cross section 150 also shows guard ring 104, on-chip transient protection device 110, connector 106 and discrete protection devices 108.
  • a voltage switchable dielectric material (also referred to as "VSDM”) can be used as transient protection material.
  • voltage switchable dielectric material was used to make an insulating substrate that can be made conductive.
  • the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating for making conductive traces.
  • electrochemical processing such as electroplating for making conductive traces.
  • U.S. Patent No. 6,797,145 discloses the use of voltage switchable dielectric material as an insulating substrate that can be made conductive for making conductive traces
  • U.S. Patent No. 6,797,145 briefly suggests the use of voltage switchable dielectric material as a transient protection material.
  • a printed circuit board (PCB) with integrated transient protection comprises a transient protection material that is selectively deposited on portions of one or more planes selected from a signal plane, a power plane and a ground plane, or any combination thereof.
  • the selectively deposited transient protection material is in contact with a conductive material in any of the one or more planes and bridges conductive elements within the PCB .
  • the different deposits of the selectively deposited transient protection material have variable characteristics depending on the location of the deposit in relation to transient sensitive components on the PCB and depending on the level of protection that is needed by the transient sensitive component.
  • One advantage of using such selectively deposited transient protection material to direct excess current to a ground, signal, or power distribution plane is that such a distribution plane acts as a heat sink and thus ameliorates degradation of transient sensitive electronic components on the PCB.
  • FIG. IA is a block diagram that illustrates a printed circuit board protected by a conductive guard ring.
  • FIG. IB is a cross section of PCB 102 of FIG. IA taken at IB.
  • FIG. 2 is a schematic that illustrates a polymer region between two contact regions of a circuit that requires protection from transients.
  • FIG. 3A is a graph that illustrates voltage clamping provided by embedded transient protection material.
  • FIG. 3B is a schematic that illustrates the placement of transient protection material for purposes of limiting voltage levels, according to certain embodiments.
  • FIG. 4A is a graph that illustrates current clamping provided by the selectively deposited transient protection material.
  • FIG. 4B is a schematic that illustrates the placement of transient protection material for purposes of limiting current levels, according to certain embodiments.
  • FIG. 5A is a schematic that illustrates the protection of a circuit trace from transients by using selectively deposited transient protection material to contact a portion of the circuit trace.
  • FIG. 5B is a graph that illustrates the unsafe voltage levels of regions that are not protected by selectively deposited transient protection material and clamped voltage levels for regions that are protected by selectively deposited transient protection material.
  • FIG. 6 is a block diagram that illustrates transient protection material selectively deposited between conductive portions of a distribution plane or between distribution planes, coated on the same layer of a PCB.
  • FIG. 7 is a block diagram that illustrates transient protection material selectively deposited between conductive portions and a via pad coated on the same layer of a PCB.
  • FIG. 8A is a block diagram that illustrates transient protection material selectively deposited between conductive portions such as two sections of copper material on a conductive plane.
  • FIG. 8B is a schematic that illustrates the placement of transient protection material for purposes of limiting voltage levels, according to certain embodiments.
  • FIG. 9 A is a block diagram that illustrates a transient protection region selectively deposited across a via anti-pad with a via pad present.
  • FIG. 9B is a schematic that illustrates the placement of transient protection material for purposes of limiting voltage levels, according to certain embodiments.
  • FIG. 1OA is a block diagram that illustrates a transient protection region selectively deposited across a via anti-pad without a via pad present.
  • FIG. 1OB is a schematic that illustrates the placement of transient protection material for purposes of limiting voltage levels, according to certain embodiments.
  • transient protection can be instituted by selectively depositing transient protection material into a PCB stackup.
  • transient protection materials are voltage switchable dielectric materials comprising base polymers that include silicon rubber, epoxy, polyimide, teflons and other polymers which are electrical dielectrics in their steady state but become electrically conductive when excited by a certain level of voltage or current
  • the transient protection materials may be in the form of any shape that is useful for protecting components on a PCB and that can be deposited on one or more layers of material in the PCB stackup, whether on the outer surface of the stackup or on internal layers of the stackup.
  • the selectively deposited transient materials in a given PCB stackup may have different properties depending on the location on the stackup at which the transient material is deposited.
  • FIG. 2 is a schematic that illustrates a polymer region (transient protection region) between two contact regions A and C of a circuit where protection from transients is needed.
  • symbol B indicates a region of selectively deposited embedded transient protection material.
  • region A and region C schematically represent the two contact regions where the transient protection polymer is attached to the circuit that needs protection from over- currents or over- voltages. Regions A, B and C are volumetric regions within a given PCB stackup rather than discrete points.
  • the selectively deposited transient protection material behaves in a bi-directional manner in that the material has the capability of clamping both positive and negative transients.
  • FIG. 3A is a graph that illustrates voltage clamping provided by the selectively deposited transient protection material.
  • the resistance of the selectively deposited transient protection material that offers bi-directional protection changes in response to applied voltage in the manner as indicated in FIG. 3A.
  • resistance is represented by the slope of curve 302.
  • a steep slope corresponds to a high resistance.
  • a shallow slope corresponds to a low resistance.
  • the low impedance reference planar region is in most cases a chassis ground plane but may also may be a power distribution plane, a signal plane, V-ground plane, an analog ground plane, a digital ground plane, or a lower voltage power distribution plane.
  • FIG. 3 B is a schematic that illustrates the placement of transient protection material for purposes of limiting voltage levels, according to certain embodiments.
  • FIG. 3B shows that the transient protection material 308 is positioned in parallel between the conductive material 304 and a low impedance reference plane 306.
  • FIG. 4A is a graph that illustrates current clamping provided by the selectively deposited transient protection material.
  • resistance is represented by the slope of curve 402.
  • a steep slope corresponds to a high resistance.
  • a shallow slope corresponds to a low resistance.
  • the resistance of the transient protection region is low.
  • the resistance of the transient protection polymer material increases and consequently allows less current to flow through the transient protection region.
  • the increase in resistance in the transient protection region limits the peak current to a safe level.
  • FIG. 4B is a schematic that illustrates the placement of transient protection material for purposes of limiting current levels, according to certain embodiments.
  • FIG. 4B shows that the transient protection material 404 is positioned in series in a signal plane 405.
  • FIG. 5A is a schematic that illustrates the protection of a circuit trace from transients by using selectively deposited transient protection material to contact a portion of the circuit trace.
  • FIG. 5A shows PCB region 500, victim circuit 504, victim circuit reference 506, and embedded protection region 508.
  • a transient voltage 502 enters PCB region 500 at victim circuit 504.
  • the transient protection region 508 is incorporated in the middle of the interconnect. When transient protection region 508 encounters the transient 502, transient protection region 508 operates to clamp the peak voltage to a safe level.
  • any excessively high levels of current due to transient voltage 502 are shunted to the victim circuit reference which can be a ground plane or power plane, etc. In other words, the excess current associated with a transient event is redirected to a low impedance reference plane.
  • FIG. 5B is a graph that illustrates the unsafe voltage levels of regions that are not protected by selectively deposited transient protection material and clamped voltage levels for regions that are protected by selectively deposited transient protection material.
  • FIG. 5B shows a graph with voltage along the vertical axis 509a and current on the horizontal axis 509b.
  • a transient voltage such as transient voltage 502 enters the PCB
  • voltage levels are at unsafe levels 510.
  • the transient voltage encounters the transient protection region such as transient protection region 508
  • the voltage is clamped to a safe level 512.
  • the use of transient protection material in PCBs involves two major aspects. First, the transient protection material needs to be optimally positioned within the PCB stackup. Second, the conductive trace and via geometries used for connecting the deposited VSDM or transient protection material to the circuits must be added.
  • the transient protection material can be selectively deposited on surfaces of laminates and cores
  • Selective deposition of the transient protection material can be accomplished through screen printing, stenciling, needle dispensing, or ink jet printing, for example.
  • Such methods of selective deposition will deposit prescribed volumes and geometries of VSDM or transient protection material, which are subsequently cured using appropriate curing methods.
  • Deposits of variable performing polymers may be deposited on the same layer or on different layers within the PCB. Because the deposit is selective, a reduced amount of material is required, and thus results in cost savings.
  • the manufacturing techniques for the structures illustrated in FIG. 6 and FIG. 7 may vary from implementation to implementation.
  • FIG. 6 and FIG 7 illustrate structures that include at least one region of selectively deposited transient protection material.
  • FIG. 6 is a block diagram that illustrates transient protection material selectively deposited between conductive portions of a distribution plane or between distribution planes, coated on the same layer of a PCB.
  • FIG. 6 shows a layer of conductive material 602 on which transient protection material 604 is selectively deposited.
  • FIG. 6 also shows a layer of dielectric material 606.
  • FIG. 7 is a block diagram that illustrates transient protection material selectively deposited between conductive portions and a via pad coated on the same layer of a PCB.
  • FIG. 7 shows transient protection material 704 selectively deposited between a conductive portion 702 such as a copper material and a via pad 706 on a conductive plane.
  • the conductive plane is positioned on a dielectric material 708.
  • the structures of FIG. 7 and 8 A can be stacked in a variety of ways so that the selectively deposited transient protection material can be on the surface of the PCB stackup or within the internal layers of the stackup.
  • FIG. 8A is a block diagram that illustrates transient protection material selectively deposited between conductive portions such as two sections of copper material on a conductive plane.
  • FIG. 8A shows a cross section of a transient protection region comprising transient protection polymer 802 selectively deposited between conductive layers 804 and 808.
  • FIG. 8A also shows a layer of dielectric material 806.
  • Figure 8 A also shows contact regions A and C where the VSDM or transient protection material contacts conductive foils 804 and 808, respectively.
  • the structure of FIG. 8A can provide transient protection for a variety of circuit topologies where two conducting regions are adjacent to each other and separated by a non- conductive region.
  • Such regions are formed by traditional processes well known in the art for PCB fabrication such a photolithographic imaging and chemical etching, but can also be formed by other methods such as laser direct imaging or laser structuring.
  • Examples of circuit topologies include but are not limited to transmission lines structures that are embedded in a distribution layer. Other non-limiting examples include slot lines, coplanar waveguides, edge- coupled differential pair transmission lines, moats of non-conductive areas separating different ground and power regions in distribution planes.
  • FIG 8B is a schematic of FIG 8A that illustrates the placement of VSDM or transient protection material for purposes of limiting voltage levels.
  • FIG 8B illustrates a circuit with conductive foil 804 adjacent to conductive foil 808.
  • the VSDM or transient protection material 802 is deposited to bridge between the conductive foils 804 and 808.
  • FIG. 9A is a block diagram that illustrates a transient protection region selectively deposited across a via anti-pad with a via pad present.
  • the antipad and via pad form an annulus within a ground plane (but is not restricted to a ground plane) into which VSDM or transient protection material is selectively deposited.
  • Such a geometry can be produced by using a print and etch process common to PCB fabrication on a copper clad laminate core.
  • the copper clad laminate core is also referred to herein as a core layer structure.
  • the copper clad laminate core can be glass reinforced with resin impregnation, random glass or fiber composite such as Dupont Thermount or it can be a film based material such as Dupont Kapton,
  • the via pad area and antipad area can be coated with a precious metal or other deposit to reduce the contact resistance between the copper and VSDM interface.
  • FIG. 9A shows a cross section of a transient protection region 902 that bridges an anti-pad region 904 of a via structure 906 with a via pad 908 present.
  • FIG. 9A also shows contact regions A and C where the transient protection material contacts the via pad 908 and conductive material 912, respectively.
  • Such a structure can be used to provide transient protection for a variety of circuit topologies where the conducting portion of the circuited to be protected is routed on the internal layers of the PCB stackup, or where the conducting portion of the circuit to be protected is on a different layer then the transient protection region in the PCB stackup.
  • Each core layer structure with selectively deposited VSDM or transient protection material can then be laminated into a printed circuit board using conventional techniques known in the art.
  • the VSDM or transient material is embedded in the PCB stackup.
  • Through-holes can be drilled into the PCB stackup.
  • the through-holes can be plated with copper.
  • Outer circuitry can be fabricated to connect pads onto which sensitive components can be subsequently assembled and connected to the embedded transient protection elements.
  • FIG 9B is a schematic of FIG 9A that illustrates the placement of VSDM or transient protection material for purposes of limiting voltage levels.
  • FIG 9B illustrates a circuit with conductive foil 912 adjacent to via pad 908.
  • the VSDM or transient protection material 902 is deposited to bridge the area between the conductive foil 912 and the via pad 908.
  • FIG. 1OA is a block diagram that illustrates a transient protection region selectively deposited across a via anti-pad without a via pad present.
  • FIG. 1OA shows a cross section of a transient protection region 1002 that bridges an anti-pad region 1004 of a via structure 1006 that is without a via pad.
  • Such a structure can be used to provide transient protection for circuits where non-functional pads are not present.
  • FIG 1OB is a schematic of FIG 1OA that illustrates the placement of VSDM or transient protection material for purposes of limiting voltage levels.
  • FIG 1OB illustrates a circuit with conductive foil 1012 adjacent to via structure 1006.
  • the VSDM or transient protection material 1002 is deposited to bridge between the conductive foil 1012 and the via structure 1006.
  • the dielectric thickness is less then about 4 mils. If the conductive foil on one side of the dielectric is a ground plane and the conductive foil on the opposing side of the dielectric is a power plane, then the core layer structure has the added benefit of embedded distributed capacitance as well as selective transient protection. A further benefit is the reduction in plane inductance by bringing the power conductive layer closer to the ground conductive layer. In other words, as the dielectric layer becomes thinner, capacitance is increased and inductance is decreased. By increasing capacitance and decreasing inductance, quieter power distribution systems are produced, which in turn allow cleaner signals at higher frequencies. Some components, such as discrete capacitors, may further be removed from the surface of the PCB, thus reducing cost.
  • the amount of capacitance generated in this embedded planar capacitor is dependent upon the dielectric constants of the transient protection material and the dielectric used in the composite, the planar area of the power-ground conductive layer pair and the thickness of the composite.
  • the amount of capacitance generated by this structure can be calculated as:

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Laminated Bodies (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/US2006/005984 2005-02-16 2006-02-16 Selective deposition of embedded transient protection for printed circuit boards Ceased WO2006089272A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007553397A JP2008533699A (ja) 2005-02-16 2006-02-16 プリント回路基板のための埋め込み過渡保護の選択的な堆積
CN200680004951.XA CN101595769B (zh) 2005-02-16 2006-02-16 印刷电路板的嵌入式瞬时保护的选择性沉积

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65372305P 2005-02-16 2005-02-16
US60/653,723 2005-02-16

Publications (2)

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WO2006089272A2 true WO2006089272A2 (en) 2006-08-24
WO2006089272A3 WO2006089272A3 (en) 2009-04-16

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PCT/US2006/005984 Ceased WO2006089272A2 (en) 2005-02-16 2006-02-16 Selective deposition of embedded transient protection for printed circuit boards
PCT/US2006/005639 Ceased WO2007050114A2 (en) 2005-02-16 2006-02-16 A substantially continuous layer of embedded transient protection for printed circuit boards

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US (2) US7593203B2 (https=)
JP (3) JP5241238B2 (https=)
CN (2) CN101595769B (https=)
TW (2) TWI397356B (https=)
WO (2) WO2006089272A2 (https=)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100038119A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
WO2001017320A1 (en) 1999-08-27 2001-03-08 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US7446030B2 (en) * 1999-08-27 2008-11-04 Shocking Technologies, Inc. Methods for fabricating current-carrying structures using voltage switchable dielectric materials
US20100038121A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US7695644B2 (en) * 1999-08-27 2010-04-13 Shocking Technologies, Inc. Device applications for voltage switchable dielectric material having high aspect ratio particles
US20100044079A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US7825491B2 (en) 2005-11-22 2010-11-02 Shocking Technologies, Inc. Light-emitting device using voltage switchable dielectric material
US20080035370A1 (en) * 1999-08-27 2008-02-14 Lex Kosowsky Device applications for voltage switchable dielectric material having conductive or semi-conductive organic material
US20100044080A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
TWI397356B (zh) * 2005-02-16 2013-05-21 聖米納公司 印刷電路板用嵌入式瞬態保護之實質連續層
TWI389205B (zh) * 2005-03-04 2013-03-11 Sanmina Sci Corp 使用抗鍍層分隔介層結構
US9781830B2 (en) 2005-03-04 2017-10-03 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
JP3993211B2 (ja) * 2005-11-18 2007-10-17 シャープ株式会社 多層プリント配線板およびその製造方法
US20100264225A1 (en) * 2005-11-22 2010-10-21 Lex Kosowsky Wireless communication device using voltage switchable dielectric material
CN101496167A (zh) 2005-11-22 2009-07-29 肖克科技有限公司 用于过电压保护的包括电压可变换材料的半导体器件
TWI276382B (en) * 2006-02-07 2007-03-11 Asustek Comp Inc Circuit board
US7981325B2 (en) 2006-07-29 2011-07-19 Shocking Technologies, Inc. Electronic device for voltage switchable dielectric material having high aspect ratio particles
US20080029405A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having conductive or semi-conductive organic material
JP2010521058A (ja) 2006-09-24 2010-06-17 ショッキング テクノロジーズ，インコーポレイテッド ステップ電圧応答を有する電圧切り換え可能な誘電体材料の組成及び該誘電体材料の製造方法
JP2010504437A (ja) * 2006-09-24 2010-02-12 ショッキング テクノロジーズ インコーポレイテッド 電圧で切替可能な誘電体材料および光補助を用いた基板デバイスをメッキする技法
US20120119168A9 (en) * 2006-11-21 2012-05-17 Robert Fleming Voltage switchable dielectric materials with low band gap polymer binder or composite
US7793236B2 (en) 2007-06-13 2010-09-07 Shocking Technologies, Inc. System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices
US20090050856A1 (en) * 2007-08-20 2009-02-26 Lex Kosowsky Voltage switchable dielectric material incorporating modified high aspect ratio particles
TWI421996B (zh) * 2008-01-10 2014-01-01 財團法人工業技術研究院 靜電放電防護架構
US8206614B2 (en) * 2008-01-18 2012-06-26 Shocking Technologies, Inc. Voltage switchable dielectric material having bonded particle constituents
US20090220771A1 (en) * 2008-02-12 2009-09-03 Robert Fleming Voltage switchable dielectric material with superior physical properties for structural applications
US8203421B2 (en) 2008-04-14 2012-06-19 Shocking Technologies, Inc. Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration
US20100047535A1 (en) 2008-08-22 2010-02-25 Lex Kosowsky Core layer structure having voltage switchable dielectric material
WO2010033635A1 (en) * 2008-09-17 2010-03-25 Shocking Technologies, Inc. Voltage switchable dielectric material containing boron compound
EP2342722A2 (en) 2008-09-30 2011-07-13 Shocking Technologies Inc Voltage switchable dielectric material containing conductive core shelled particles
US9208931B2 (en) 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductor-on-conductor core shelled particles
US8362871B2 (en) * 2008-11-05 2013-01-29 Shocking Technologies, Inc. Geometric and electric field considerations for including transient protective material in substrate devices
US8272123B2 (en) * 2009-01-27 2012-09-25 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US8399773B2 (en) 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US9226391B2 (en) * 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
US8968606B2 (en) 2009-03-26 2015-03-03 Littelfuse, Inc. Components having voltage switchable dielectric materials
TWI363583B (en) * 2009-07-15 2012-05-01 Quanta Comp Inc Audio circuit board
US9053844B2 (en) 2009-09-09 2015-06-09 Littelfuse, Inc. Geometric configuration or alignment of protective material in a gap structure for electrical devices
US9320135B2 (en) * 2010-02-26 2016-04-19 Littelfuse, Inc. Electric discharge protection for surface mounted and embedded components
US9224728B2 (en) * 2010-02-26 2015-12-29 Littelfuse, Inc. Embedded protection against spurious electrical events
US9082622B2 (en) 2010-02-26 2015-07-14 Littelfuse, Inc. Circuit elements comprising ferroic materials
WO2011137261A1 (en) * 2010-04-28 2011-11-03 Shocking Technologies, Inc. Embedded protection against spurious electrical events
JP2012018907A (ja) * 2010-06-11 2012-01-26 Nissan Motor Co Ltd 電機部品
EP2758992A4 (en) * 2011-09-21 2015-08-12 Littelfuse Inc VERTICAL SWITCHING INFORMATION FOR ESD PROTECTION
CN103716994B (zh) * 2012-09-28 2016-09-07 珠海方正科技高密电子有限公司 一种印制电路板的制作方法及其印制电路板
TWI496516B (zh) * 2013-08-06 2015-08-11 Pegatron Corp 電路板結構
TWI501709B (zh) * 2013-08-16 2015-09-21 Pegatron Corp 電路板
US9510439B2 (en) * 2014-03-13 2016-11-29 Honeywell International Inc. Fault containment routing
US9503090B2 (en) * 2014-08-19 2016-11-22 International Business Machines Corporation High speed level translator
TWI569392B (zh) * 2014-10-20 2017-02-01 欣興電子股份有限公司 凹槽式載板製造方法
US9980381B2 (en) 2014-12-16 2018-05-22 Motorola Solutions, Inc. Method and apparatus for intrinsically safe circuit board arrangement for portable electronic devices
DE102021130924B4 (de) * 2021-11-25 2024-01-04 Infineon Technologies Ag Schutz vor elektrostatischer Entladung einer elektronischen Komponente, welche in dem Laminat einer gedruckten Leiterplatte eingebettet ist
CN114187618B (zh) * 2021-12-09 2025-03-14 深圳市汇顶科技股份有限公司 指纹检测电路、指纹检测装置和制造指纹检测电路的方法
CN114814669A (zh) * 2022-05-06 2022-07-29 中国科学院近代物理研究所 一种磁场纹波测量方法及装置

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4133735A (en) 1977-09-27 1979-01-09 The Board Of Regents Of The University Of Washington Ion-sensitive electrode and processes for making the same
US4628022A (en) * 1983-07-13 1986-12-09 At&T Technologies, Inc. Multilayer circuit board fabrication process and polymer insulator used therein
US4992333A (en) * 1988-11-18 1991-02-12 G&H Technology, Inc. Electrical overstress pulse protection
DE3911711A1 (de) 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
US5010641A (en) * 1989-06-30 1991-04-30 Unisys Corp. Method of making multilayer printed circuit board
US5260848A (en) 1990-07-27 1993-11-09 Electromer Corporation Foldback switching material and devices
JP2773578B2 (ja) 1992-10-02 1998-07-09 日本電気株式会社 半導体装置の製造方法
US5382928A (en) * 1993-01-22 1995-01-17 The Whitaker Corporation RF filter having composite dielectric layer and method of manufacture
GB2277197B (en) 1993-04-13 1997-08-27 Motorola Inc Voltage protection arrangement
US5479031A (en) 1993-09-10 1995-12-26 Teccor Electronics, Inc. Four layer overvoltage protection device having buried regions aligned with shorting dots to increase the accuracy of overshoot voltage value
EP1233427B1 (en) 1994-07-14 2012-10-10 Surgx Corporation Single and multi-layer variable voltage protection devices
WO1996002922A2 (en) 1994-07-14 1996-02-01 Surgx Corporation Variable voltage protection structures and methods for making same
US6210537B1 (en) * 1995-06-19 2001-04-03 Lynntech, Inc. Method of forming electronically conducting polymers on conducting and nonconducting substrates
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US6172590B1 (en) 1996-01-22 2001-01-09 Surgx Corporation Over-voltage protection device and method for making same
US5796570A (en) * 1996-09-19 1998-08-18 National Semiconductor Corporation Electrostatic discharge protection package
US6013358A (en) 1997-11-18 2000-01-11 Cooper Industries, Inc. Transient voltage protection device with ceramic substrate
US6251513B1 (en) * 1997-11-08 2001-06-26 Littlefuse, Inc. Polymer composites for overvoltage protection
US6642297B1 (en) * 1998-01-16 2003-11-04 Littelfuse, Inc. Polymer composite materials for electrostatic discharge protection
GB2334627B (en) 1998-02-21 2003-03-12 Mitel Corp Vertical spark gap for microelectronic circuits
US6130459A (en) 1998-03-10 2000-10-10 Oryx Technology Corporation Over-voltage protection device for integrated circuits
US6064094A (en) 1998-03-10 2000-05-16 Oryx Technology Corporation Over-voltage protection system for integrated circuits using the bonding pads and passivation layer
US6549114B2 (en) * 1998-08-20 2003-04-15 Littelfuse, Inc. Protection of electrical devices with voltage variable materials
DE19958915A1 (de) * 1998-12-08 2000-06-29 Littelfuse Inc Schutz eines integrierten Schaltkreises mit spannungsvariablen Materialien
US6329603B1 (en) 1999-04-07 2001-12-11 International Business Machines Corporation Low CTE power and ground planes
US7446030B2 (en) 1999-08-27 2008-11-04 Shocking Technologies, Inc. Methods for fabricating current-carrying structures using voltage switchable dielectric materials
WO2001017320A1 (en) 1999-08-27 2001-03-08 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
NL1014319C2 (nl) 2000-02-08 2001-08-09 Fci S Hertogenbosch B V Connector omvattende een ESD onderdrukker.
US6373719B1 (en) 2000-04-13 2002-04-16 Surgx Corporation Over-voltage protection for electronic circuits
US6669871B2 (en) 2000-11-21 2003-12-30 Saint-Gobain Ceramics & Plastics, Inc. ESD dissipative ceramics
US7258819B2 (en) 2001-10-11 2007-08-21 Littelfuse, Inc. Voltage variable substrate material
AU2003224894A1 (en) * 2002-04-08 2003-10-27 Littelfuse, Inc. Voltage variable material for direct application and devices employing same
US6981319B2 (en) 2003-02-13 2006-01-03 Shrier Karen P Method of manufacturing devices to protect election components
US20040183135A1 (en) 2003-03-19 2004-09-23 Oh-Hun Kwon ESD dissipative structural components
US6853036B1 (en) 2003-08-06 2005-02-08 Esd Pulse, Inc. Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event
TWI397356B (zh) 2005-02-16 2013-05-21 聖米納公司 印刷電路板用嵌入式瞬態保護之實質連續層

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