Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/697—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having trapping at multiple separated sites, e.g. multi-particles trapping sites
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
  • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

• the present invention relates to non-volatile memories having nanocrystals for storage, and more particularly to the insulation of and over such nanocrystals.
• Nanocrystal memories have been found to be advantageous over floating gate memories due to increased immunity to charge leakage through gate dielectric defects.
• One issue in nanocrystal memories is the potential for electron trapping in the dielectric stack under the control gate. This problem occurs during hot carrier injection of electrons into the nanocrystals. A fraction of the electrons not trapped by the nanocrystals can be trapped in the dielectric stack, which leads to a shift in the threshold voltage. These electrons trapped in the dielectric stack are not electrically erasable so they accumulate with repeated program and erase cycles. Thus the shift in threshold voltage continues to grow with the repeated program erase operations and requires circuit designs that attempt to mitigate this effect. In addition to this, dielectric trapped charge can lead to degradation in reliability due to internal electric fields working concomitantly with external bias.
• electrons trapped in the portion of the dielectric stack between the control gate and the nanocrystals can degrade data retention of nanocrystals programmed with electrons by accelerating tunneling loss through the portion of the dielectric stack between the nanocrystals and the substrate.
• FIG. 1 is a cross section of a device structure at a stage in processing according to an embodiment of the invention
• FIG. 2 is a cross section of the device structure of FIG. 1 at a subsequent stage in processing
• FIG. 3 is a cross section of the device structure of FIG. 2 at a subsequent stage in processing
• HG. 4 is a cross section of the device structure of HG. 3 at a subsequent stage in processing
• FTG. 5 is a cross section of the structure of FIG. 4 at a subsequent stage in processing.
• a nanocrystal non- volatile memory has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped. This is better understood with reference to the drawings and the following description. Shown in FIG.
• a semiconductor device 10 comprising a substrate 12, a gate dielectric 14 over substrate 12, a plurality of nanocrystals 16 over the gate dielectric 14.
• Substrate 12 is preferably a bulk silicon substrate but could be an SOI substrate also and could be a different semiconductor material than silicon.
• Gate dielectric layer 14 is preferably a grown oxide that is 50 to 100 Angstroms in thickness and has a graded nitrogen content which is highest farthest from nanocrystals 16 and closest to substrate 12.
• Nanocrystals 16 in this example are made of silicon and have a density of between five times ten to the eleventh (5ell) and 1.2el2 per centimeter squared. Nanocrystals 16 vary in size between about 3 to 10 nanometers. Nanocrystals 16 are preferably deposited by chemical deposition, but other processes may also be used. Other processes for forming nanocrystals include recrystallization of a thin amorphous layer of silicon and the deposition of prefabricated nanocrystals. Subsequent to nanocrystal formation, nanocrystals 16 may be passivated by oxidizing them using nitrous oxide.
• semiconductor device 10 after forming a , nitride-doped oxide layer 18 over and around nanocrystals 16. It is preferably about 3 to five nanometers in thickness and forms a first portion of a dielectric between the nanocrystals and a control gate that is not yet formed.
• the nitrogen content in layer 18 is graded. The highest nitrogen content is closest to the nanocrystals and begins at about 5-10 atomic percent. The nitrogen content is reduced away from nanocrystals 16 to eventually less than about 2 atomic percent.
• This grading is preferably achieved by reacting small amounts of ammonia .with oxide forming gases such as dichlorosilane and nitrous oxide and gradually decreasing the flow rate of the ammonia.
• An alternative is to implant nitrogen into an oxide layer in a series of implant steps.
• the heaviest dose implant is with the highest energy and the lightest dose implant is with the lowest energy.
• This implantation is preferably performed in a remote plasma environment to prevent damage to layer 18.
• the nitrogen in the oxide layer during subsequent annealing steps saturates dangling bonds in the originally formed oxide layer.
• silicon-hydrogen bonds that have weak immunity to hot electrons are converted to more robust silicon-nitrogen bonds. Since the highest concentration of such bond defects is at the interface between dielectric layers, in this case between layers 14 and 18, and between the nanocrystals 16 and dielectric layer 18, a higher concentration of nitrogen is needed in these interface regions. Further away from the interface, the bond defects are fewer and require less nitrogen.
• Dielectric layer 20 is preferably silicon oxide and deposited by reacting a silicon- containing precursor such as silane or dichlorosilane with an oxidizer such as oxygen or nitrous oxide in a chemical vapor deposition chamber at between about 500 and 900 degrees Celsius. Layer 20 is typically between four and ten nanometers in thickness.
• semiconductor device 10 after performing remote plasma nitridation of layer 20 to form a nitrided layer 22.
• the nitrogen content in nitrided layer 22 is preferably less than about 2 atomic percent. Since achieving such small nitrogen content is difficult by CVD, remote plasma deposition is the preferred approach. The energy of the remote plasma can be reduced over time in conjunction with a reduction in the flow of the nitrogen-containing species in order to achieve a graded nitrogen concentration in nitrided layer 22. The higher nitrogen concentration in such case is at the interface of layers 18 and 22 and the lower concentration is at the top surface of layer 22. Implanting nitrogen is also an alternative but remote plasma is preferable due to there being less damage at and near the surface of layer 20 compared to implanting. This remote plasma deposition, with enough energy, can also be utilized to introduce additional nitrogen into layer 18. Additionally, oxygen can be implanted into layer 20 to aid in densification.
• annealing steps are performed, preferably at about greater than 700 degrees Celsius or higher.
• a first of these annealing steps is done in an inert ambient such as nitrogen or argon at about greater than 800 degrees Celsius. This step facilitates nitrogen bonding and expels free hydrogen from layers 18 and 22.
• a second of these annealing steps is in a dilute oxidizing ambient and is for removing non-stoichiometric defects that may still be present.
• a third of these annealing steps is performed close to or about the glass transition temperature, which is about 950 degrees Celsius. The high degree of atomic motion during this reflow condition facilitates the structure to relax the stress of layers 18 and 22.
• the second and third annealing steps may be able to be combined into a single annealing step.
• the annealing temperature preferably does not exceed 1100 degrees Celsius.
• FIG. 5 Shown in FIG. 5 is semiconductor device 10 after performing known steps to form an NVM device comprising a control gate 26, a sidewall spacer 28 around control gate 26, a source/drain region 30 on one side of control gate 26 and in substrate 12, and a source/drain region 32 on the other side of control gate 26 and in substrate 12.
• the resulting semiconductor device 10 of FlG. 5 is a transistor useful as the NVM device and for forming arrays of such devices.
• Layers 18 and 22 with their nitrogen content as described reduces threshold shift due to electron/hole trapping.
• Another benefit of the described approach is that layers 18 and 22 have increased density. Unlike thermally grown oxide such as layer 14, deposited oxides are less dense and stoichiometrically imperfect.

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• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Nanotechnology (AREA)
• Physics & Mathematics (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Crystallography & Structural Chemistry (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)
• Formation Of Insulating Films (AREA)
• Physical Or Chemical Processes And Apparatus (AREA)
• Carbon And Carbon Compounds (AREA)

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• 2005
  • 2005-01-26 US US11/043,826 patent/US7361567B2/en not_active Expired - Fee Related
  • 2005-12-14 KR KR1020077017264A patent/KR101219067B1/ko not_active Expired - Fee Related
  • 2005-12-14 AT AT05854006T patent/ATE473515T1/de not_active IP Right Cessation
  • 2005-12-14 DE DE602005022229T patent/DE602005022229D1/de not_active Expired - Lifetime
  • 2005-12-14 EP EP05854006A patent/EP1844492B1/en not_active Expired - Lifetime
  • 2005-12-14 CN CNA2005800409629A patent/CN101438392A/zh active Pending
  • 2005-12-14 JP JP2007552129A patent/JP4980931B2/ja not_active Expired - Fee Related
  • 2005-12-14 WO PCT/US2005/045207 patent/WO2006080999A2/en not_active Ceased
• 2006
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