CN101640176A - 在快闪存储器件中形成隧道绝缘层的方法 - Google Patents

在快闪存储器件中形成隧道绝缘层的方法 Download PDF

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CN101640176A
CN101640176A CN200910140308A CN200910140308A CN101640176A CN 101640176 A CN101640176 A CN 101640176A CN 200910140308 A CN200910140308 A CN 200910140308A CN 200910140308 A CN200910140308 A CN 200910140308A CN 101640176 A CN101640176 A CN 101640176A
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丁祐日
申承祐
李尚洙
金在文
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SK Hynix Inc
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Abstract

在快闪存储器件中形成隧道绝缘层的方法，包括：在半导体衬底上形成氧化物层，将氧化物层的表面形成为含氮层，和在半导体衬底与氧化物层之间限定的界面上形成氮累积层。

Description

在快闪存储器件中形成隧道绝缘层的方法
相关申请的交叉引用
本发明要求2008年7月29日提交的韩国专利申请10-2008-0073895的优先权，通过引用将其全部内容并入本文。
技术领域
本发明一般性涉及在快闪存储器件中形成隧道绝缘层的方法，更具体地涉及能够改善漏电流和击穿电压特性的在快闪存储器件中形成隧道绝缘层的方法。
背景技术
快闪存储器件是在断电情况下在存储单元中保持所存储数据的非易失性存储器件，并能够在快闪存储器件安装于电路板的状态下高速进行电擦除功能。由于有助于高度集成的结构，快闪存储器件已经成为许多研究的主题。通过在半导体衬底的有源区域上依次地层叠隧道氧化物层、浮置栅极、介电层和控制栅极，形成快闪存储器件的单位单元。与常规晶体管中的栅极氧化物层不同，隧道氧化物层本身作为数据通过其传输的通道；因此需要隧道氧化物层具有极好的薄膜特性。
在NAND快闪存储器中，由于以Fowler-Nordheim(F-N)隧穿法实施全部编程操作和擦除操作，所以如果编程操作和擦除操作重复多次，则隧道氧化物层劣化，从而使得快闪存储器件无法完全地实施其功能。因此，隧道氧化物层尽可能地薄以提高编程速度，同时氮注入到薄层中以防止薄膜特性劣化。通常，已经利用了改善薄膜特性的方法。该方法包括：实施氧化过程以生长纯氧化物层，随后利用N2O气体或者NO气体实施退火过程，以在隧道氧化物层和半导体衬底之间的界面上以2原子％至3原子％的浓度分布氮。
然而，通过在厚度刚已减小的隧道氧化物层上以2原子％至3原子％的浓度分布氮，难以令人满意地确保击穿电压特性或漏电流特性。此外，在PMOS晶体管中，栅极绝缘层的特性因硼的穿透而劣化。
发明内容
本发明提供在快闪存储器件中形成隧道绝缘层的方法，包括：实施氮化处理以形成隧道绝缘层，和形成氮累积层。
根据本发明一个实施方案的在快闪存储器件中形成隧道绝缘层的方法包括：在半导体衬底上形成氧化物层，将氧化物层的表面形成为含氮层，和在半导体衬底与氧化物层之间限定的界面上形成氮累积层。
优选通过自由基氧化过程形成氧化物层。优选在氧气(O2)、氢气(H2)和氩气(Ar)的气氛下和在800℃～950℃的温度下进行自由基氧化过程。
含氮绝缘层优选包括氧氮化硅(SiON)层。优选通过等离子体氮化处理过程形成含氮绝缘层。在形成氮累积层之后，含氮绝缘层优选具有5原子％至30原子％的氮浓度。
优选在氢气(H2)和氩气(Ar)的气氛下、在3Pa～10Pa的压力下、在150W～200W的功率下和在800℃～900℃的温度下，实施等离子体氮化处理过程。
优选通过退火过程，更优选利用一氧化二氮(N2O)气体，形成氮累积层。优选在预活化室(PAC)中，在常压(即大气压)和900℃～1100℃的温度下，实施该退火过程。在等离子体氮化处理过程之后，优选以异位方式实施退火过程。
附图说明
通过参考以下详述并结合附图进行考虑时，本发明的上述及其他特征和优点将容易地变得明显，其中：
图1A至图1C是说明根据本发明一个实施方案的在快闪存储器件中形成隧道绝缘层的方法的截面图；和
图2是显示氮浓度随着本发明一个实施方案的隧道绝缘层的深度变化而变化的SIMS(次级离子质谱)图。
具体实施方式
参考附图更详细地说明本发明的优选实施方案。
图1A至图1C是用于说明根据本发明一个实施方案的在快闪存储器件中形成隧道绝缘层的方法的截面图，图2是显示氮浓度随着本发明一个实施方案的隧道绝缘层的深度变化而变化的SIMS(次级离子质谱)图。
参考图1A，提供其上形成有阱区域(未显示)的半导体衬底10。阱区域优选形成为三重结构。为了形成具有三重结构的阱区域，在半导体衬底10上形成遮蔽氧化物层(未显示)，然后实施阱离子注入过程和阈值电压离子注入过程。
移除遮蔽氧化物层之后，优选在半导体衬底10(其上形成有阱区域)上形成氧化物层以形成隧道绝缘层之前，还实施清洁过程。优选通过使用HF溶液和标准清洁-1(standard cleaning-1)(SC-1)溶液实施清洁过程，以移除固有的氧化物层和杂质。
随后，在移除遮蔽氧化物层之后，在其上形成有阱区域的半导体衬底10上形成氧化物层12。优选通过自由基氧化过程形成氧化物层。在这种情况下，高度优选在O2气体、H2气体和氩气(Ar)的气氛下和在800℃～950℃的温度下实施自由基氧化过程。结果，形成纯二氧化硅(SiO2)层作为氧化物层12。氧化物层12优选具有
Figure G2009101403085D00031
至
Figure G2009101403085D00032
的厚度。
在所述的通过自由基氧化过程形成氧化物层12的情况下，能够获得更紧密的层，以防止隧道绝缘层的品质在后续的在高温下实施的过程中劣化。
参考图1B，使氧化物层12的表面氮化。实施氮化处理过程，例如说明性的等离子体氮化处理。在这种情况下，与常规氮化处理过程相比，为了更有效地进行化学反应，优选在800℃～900℃的高温下实施等离子体氮化处理过程。此外，优选在氩气(Ar)和氮气(N2)的气体气氛中、在3Pa至10Pa的压力下和在150W至200W的功率下，实施等离子体氮化处理过程。
通过如上所述的等离子体氮化处理过程，氧化物层12表面上的硅-氧(Si-O)组合中的氧被氮取代，所以在氧化物层12的表面上形成含氮绝缘层12a。结果，在氧化物层12的表面上形成一个氮峰。
优选形成氮化物层作为上述含氮绝缘层12a，所述氮化物层优选为氮化硅(Si3N4)层和氧氮化硅(SiON)层中的至少一种。在本发明的一个优选实施方案中，主要通过等离子体氮化处理过程形成高氮含量的氧氮化硅(SiON)层。结果，氧氮化硅(SiON)层可防止硼穿透进入之后形成的隧道绝缘层，以改善隧道绝缘层的击穿电压特性或者漏电流特征。
与在500℃或更低的低温下实施的常规等离子体氮化处理过程相比，在800℃或更高的高温下实施的等离子体氮化处理过程中更容易发生化学反应。因此，与在低温下实施的等离子体氮化处理过程相比，在高温下实施的等离子体氮化处理过程可显著地减少俘获位点(trap site)。结果，能够显著改善之后形成的隧道绝缘层的击穿电压特性或者漏电流特征。
同时，由于氧化物层12的表面在氮化处理过程期间发生反应以形成含氮绝缘层12a，所以与之前阶段中形成的氧化物层的厚度相比，氧化物层12的厚度减小。
参考图1C，实施用于在半导体衬底10与氧化物层12之间限定的界面上累积氮的过程。优选此时实施退火过程，更优选利用一氧化二氮(N2O)，作为用于累积氮的过程，并且用于累积氮的过程优选在形成含氮绝缘层12a之后以异位方式实施。在这种情况下，优选在一氧化二氮气体的气氛下、在常压(即大气压)下和在900℃～1100℃的温度下，实施N2O退火过程。而且，优选在预活化室(PAC)中实施N2O退火过程，以促进一氧化二氮(N2O)气体的分解。
结果，在半导体衬底10和氧化物层12之间的界面上形成注入氮的氮累积层12b。借助于氮累积层，在半导体衬底10和氧化物层12之间的界面上形成另一个氮单峰。由于上述氮累积层12b，可减小在半导体衬底10和氧化物层12之间的界面上不可避免地产生的界面俘获电荷的密度，因此可改善应力诱导的漏电流(SILC)和电流-电压(C-V)特性，以提高以后形成的隧道绝缘层的循环特性和保留特性。
特别地，在本发明的一个实施方案中，在N2O退火过程之后，包含于含氮绝缘层12a中的氮的浓度调节为5原子％至30原子％，使得以后形成的隧道绝缘层的击穿电压特性得以改善、和使得隧道绝缘层中的漏电流减小以改善漏电流特性。
通常，当在等离子体氮化处理过程之后实施N2O退火过程时，在氧化物层12的表面上形成的含氮绝缘层12a中包含的氮的浓度减小了40％～50％。因此，为了在N2O退火过程之后，获得具有期望浓度的包含于含氮绝缘层12a中的氮，应该调整N2O退火过程的条件，同时应该调节等离子体氮化处理过程中使用的氮的浓度。
同时，与形成含氮绝缘层12a之后的氧化物层相比，氧化物层12的厚度优选因N2O退火过程而增加了约
Figure G2009101403085D00051
至
Figure G2009101403085D00052
然而，优选应该适当地控制N2O退火过程的工艺条件，以将N2O退火过程之后氧化物层12的厚度增量限制为
Figure G2009101403085D00053
或更小。此外，含氮绝缘层12b的厚度可因N2O退火过程而部分增加。
通常，由于氧化物层12的表面损伤和所结合氮的不稳定性，难以利用氮峰的优点，所以在氮化处理过程之后实施后续的氧(O2)退火过程。然而，在本发明的说明性实施方案中，由于在氮化处理过程之后实施N2O退火过程，所以在氮化处理之后省略氧(O2)退火过程，以减少过程数目和氮的损失，并促进含氮绝缘层12a的密实化，从而防止以后形成的隧道绝缘层的阈值电压偏移特性和变量特性劣化。
最后，通过在形成氧化物层12之后依次实施的等离子体氮化处理过程(在高温下实施的)和N2O退火过程，形成了隧道绝缘层14，隧道绝缘层14是由氮累积层12b、氧化物层12和含氮绝缘层12a组成的堆叠层。
根据本发明上述实施方案，通过在800℃或更高的高温下实施的等离子体氮化处理过程，俘获位点显著减少，并形成隧道绝缘层14，隧道绝缘层14包括说明性地包括高氮含量的氧氮化硅(SiON)层、或者由高氮含量的氧氮化硅(SiON)层组成的含氮绝缘层12a，因此能够抑制硼穿透进入隧道绝缘层14，以改善隧道绝缘层的漏电流特性和击穿电压特性。
通常，氮化物层例如氮化硅(Si3N4)层和氧氮化硅(SiON)层的介电率为约7，而二氧化硅(SiO2)层的介电率为约3.9。因此，在隧道绝缘层14包括含氮绝缘层12a并且含氮绝缘层12a包括氧氮化硅(SiON)层或者由氧氮化硅(SiON)层组成的情况下，通过减小隧道绝缘层14的等效氧化物厚度(EOT)，隧道绝缘层14的物理厚度可增加，以改善循环和保留特性。
参考图2，在实施N2O退火过程之前，根据本发明一个实施方案的如图1A、1B和1C所示的隧道绝缘层14具有因在等离子体氮化处理过程期间获得的含氮绝缘层12a而在其表面上形成的一个氮峰(图2中以“A”表示)。在N2O退火过程完成后，隧道绝缘层14具有两个氮峰，所述两个氮峰由因含氮绝缘层12a而在隧道绝缘层14的表面上形成的氮浓度小于氮峰“A”的一个氮峰(图2中以“B”表示)，和因N2O退火过程期间得到的氮累积层12b而在半导体衬底10和隧道绝缘层14之间的界面上形成的另一个氮峰(图2中以“C”表示)组成。此时，可证实最终的隧道绝缘层14表面上的氮峰B的氮浓度维持为7原子％或更高。
因此，尽管根据本发明的一个实施方案的隧道绝缘层14具有两个氮峰，隧道绝缘层14表面的氮浓度说明性地维持为5原子％或更高，但是隧道绝缘层包括由具有高氮含量的氧氮化硅(SiON)层形成的含氮绝缘层12a并通过上述含氮绝缘层而密实化。因此，本发明可改善击穿电压特性、漏电流特性、循环特性、保留特性、阈值电压偏移特性、和变量特性，以改善器件可靠性。
虽然附图中未显示，但是在形成隧道绝缘层14之后，优选形成多晶硅层用于形成浮置栅极，然后实施后续过程以完成制造半导体器件的过程。
本发明具有以下效果。
第一，通过氮化处理过程，优选通过等离子体氮化处理过程，更优选在800℃或更高的高温下实施来形成隧道绝缘层，可显著地减少俘获位点，并且通过形成氧氮化硅(SiON)层抑制了硼的穿透，因此改善了击穿电压特性和漏电流特性。
第二，通过应用等离子体氮化处理过程，隧道绝缘层的等效氧化物厚度(EOT)减小，并且由于EOT减小，隧道绝缘层的物理厚度可增加。因此，可改善循环和保留特性。
第三，在等离子体氮化处理过程之后，实施用于形成隧道绝缘层的N2O退火过程，而不是实施在应用常规等离子体氮化处理过程时进行的后续O2退火过程。因此，过程数目减小，促进了氧化物层表面上的含氮绝缘层的密实化和氮损失，以防止阈值电压偏移特性和变量特性劣化。
虽然已经参考大量说明性实施方案描述了一些实施方案，但是应理解本领域技术人员可设计很多的其它改变和实施方案，这些也将落入本公开的原理的精神和范围内。更具体地，在公开、附图和所附权利要求的范围内，在本发明主题组合布置的构件和/或布置中能够具有变化和改变。除构件和/或布置的变化和改变之外，对本领域技术人员而言，可替代的用途也是明显的。

Claims (14)

1.一种在快闪存储器件中形成隧道绝缘层的方法，包括：
在半导体衬底上形成氧化物层；
将所述氧化物层的表面形成为含氮层；和
在所述半导体衬底与所述氧化物层之间限定的界面上形成氮累积层。
2.根据权利要求1所述的方法，包括通过自由基氧化过程形成所述氧化物层。
3.根据权利要求2所述的方法，包括在800℃～950℃的温度下进行所述自由基氧化过程。
4.根据权利要求2所述的方法，包括在氧气(O2)、氢气(H2)和氩气(Ar)的气氛下实施所述自由基氧化过程。
5.根据权利要求1所述的方法，包括通过等离子体氮化处理过程形成所述含氮绝缘层。
6.根据权利要求5所述的方法，包括在氢气(H2)和氩气(Ar)的气氛下实施所述等离子体氮化处理过程。
7.根据权利要求5所述的方法，包括在800℃～900℃的温度下实施所述等离子体氮化处理过程。
8.根据权利要求5所述的方法，包括在3Pa至10Pa的压力下和在150W至200W的功率下实施所述等离子体氮化处理过程。
9.根据权利要求1所述的方法，其中所述含氮绝缘层包括氧氮化硅(SiON)层。
10.根据权利要求1所述的方法，包括通过利用一氧化二氮(N2O)气体的退火过程形成所述氮累积层。
11.根据权利要求10所述的方法，包括在大气压力下和在900℃～1100℃的温度下实施所述退火过程。
12.根据权利要求10所述的方法，包括在预活化室(PAC)中实施所述退火过程。
13.根据权利要求10所述的方法，包括在形成所述含氮绝缘层之后，以异位方式实施所述退火过程。
14.根据权利要求1所述的方法，其中在形成所述氮累积层之后，所述含氮绝缘层的氮浓度为5原子％至30原子％。
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* Cited by examiner, † Cited by third party
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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EP3656356B1 (en) * 2011-02-25 2021-04-28 Corin Limited A computer-implemented method, a computing device and a computer readable storage medium for providing alignment information data for the alignment of an orthopaedic implant for a joint of a patient
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KR102066743B1 (ko) * 2014-01-09 2020-01-15 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성방법
US9953831B1 (en) * 2016-12-21 2018-04-24 Globalfoundries Inc. Device structures with multiple nitrided layers
US11322347B2 (en) * 2018-12-14 2022-05-03 Applied Materials, Inc. Conformal oxidation processes for 3D NAND

Family Cites Families (3)

* Cited by examiner, † Cited by third party
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