US20060246665A1 - Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories - Google Patents
Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories Download PDFInfo
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- US20060246665A1 US20060246665A1 US11/476,361 US47636106A US2006246665A1 US 20060246665 A1 US20060246665 A1 US 20060246665A1 US 47636106 A US47636106 A US 47636106A US 2006246665 A1 US2006246665 A1 US 2006246665A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Definitions
- the present invention relates to the manufacturing of semiconductor memory devices, such as non-volatile memories of the flash EEPROM (Electrically Erasable Programmable Read-Only Memories) type. Flash EEPROM memories can be erased with one operation in all the cells forming the memory.
- flash EEPROM Electrically Erasable Programmable Read-Only Memories
- the above dielectric layer is obtained in different ways and made out of different materials.
- a common procedure is to deposit three dielectric layers successively onto the floating gate region, this region being formed by a layer of amorphous or polycrystalline silicon (polysilicon) deposited onto a thin layer of silicon oxide known as the tunnel oxide.
- the so obtained multiple dielectric layer comprises: a first layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon oxide.
- the resulting dielectric is known as the ONO or ONO interpoly dielectric, as it is shown in FIG. 1 .
- the cell capability to retain its logic state is mainly guaranteed by the two layers of silicon oxide.
- the nitride layer facilitates integration of the triple layer inside the flow of the device manufacturing process.
- treatments made with oxidizing species O 2 , O, OH, H 2 O
- the nitride acts as a barrier against the diffusion of the oxidizing species to the floating gate, since it is not permeable to said oxidizing species.
- its presence is effective to prevent further oxidation of the floating gate, and therefore, the thickness of the interpoly dielectric from being changed in the course of subsequent steps of the device manufacturing process.
- a single oxide interpoly layer may be used whenever, in specific memory cells, the interpoly dielectric is not required to be particularly thin and/or no oxidizing treatments are provided after its formation.
- the thickness of the interpoly dielectric is, irrespective of its composition and forming method, jointly responsible of the capacitive coupling of the memory cell. Accordingly, it enters the setting of program and erase parameters, additionally to ensuring retention of the logic state over time.
- the overall electrical thickness of the interpoly dielectric obtained by the combination of the nitride oxide layer and the following dielectric layer can be brought down to 130 Angstroms or less in the options of ONO layer or the single silicon oxide layer (single oxide interpoly).
- FIGS. 8 and 9 are schematically enlarged vertical cross-section views taken through a portion of a flash memory cell during a process according to a modified embodiment of the invention.
- the process of forming an interpoly dielectric layer 2 for a non-volatile flash memory cell is carried out according to the steps hereafter described. It should be noted that the step of directly nitriding the amorphous or polycrystalline silicon layer is the same, and is followed by two alternative options, as concerning the dielectric depositing steps.
- a first of these alternative steps is marked “a” hereinafter and involves depositing ONO interpoly dielectric by the CVD (Chemical Vapor Deposition) technique onto batch or single wafers.
- CVD Chemical Vapor Deposition
- the second step is marked “b” hereinafter and involves depositing single oxide interpoly dielectric by the CVD (Chemical Vapor Deposition) technique onto batch or single wafers.
- CVD Chemical Vapor Deposition
- a layer of tunnel oxide 3 is grown over the substrate 1 and followed by the deposition of an amorphous or polycrystalline silicon layer 4 , as shown in FIG. 1 .
- This process step may be carried out now, or alternatively as step 5a-b below.
- This step exposes a mask to define the floating gate region from the silicon layer 4 .
- Masking is followed by dry etching the amorphous or polycrystalline layer and then removing the residual resist from the wafer.
- the surface of the amorphous or polycrystalline layer 4 used in forming the floating gate of the device is surface cleansed by means of chemicals in aqueous solution. This treatment is applied by either growing native chemical oxide, or by passivating said surface with Si—H bonds, or by wet or vapor HF-last, subsequent to the aqueous cleansing treatment.
- said surface is nitrided directly using radical nitrogen, on either batch or single wafers.
- Radical nitrogen (N+) is obtained by subjecting N 2 molecules to a plasma.
- this technology for example, is known as RPN (Remote Plasma Nitridation), DPN (Decoupled Plasma Nitridation), and MRG (Magnetic Radical Generator).
- RPN Remote Plasma Nitridation
- DPN Decoupled Plasma Nitridation
- MRG Magnetic Radical Generator
- interpoly dielectric is a single oxide interpoly, preventing oxidizing chemicals, such as O 2 , O, OH, and H 2 O, from migrating to the floating gate during later treatments subjected to the memory device being formed.
- the nitride oxide layer 5 can be regarded as a barrier layer.
- the silicon nitride oxide layer 5 obtained by direct surface nitridation of layer 4 as explained above and shown in FIG. 4 , has preferably a thickness dimension of 0.5 to 5.0 nm.
- the nitrogen distribution inside of said layer 5 should be no less than 1e22 at/cm 3 as peak value, for a total amount of no less than 1e15 at/cm 2 .
- the direct surface nitridation processes using radical nitrogen are carried out at temperatures of 500° to 800° C. for 30 seconds ( 30 ′′) to 3 minutes ( 3 ′) on single wafers.
- Either N 2 alone or nitrogen/inert gas mixtures such as N 2 /He and N 2 /Ar may be used as the process gas.
- step 5a-b This step is carried out, only when step 2a-b is skipped, using the same procedure as for step 2a-b.
- the interpoly dielectric 2 can now be formed as an ONO (Oxide-Nitride-Oxide) triple layer 6 , e.g., by using a CVD (Chemical Vapor Deposition) technique onto batch or single wafers.
- ONO Oxide-Nitride-Oxide
- CVD Chemical Vapor Deposition
- the physical thicknesses of the individual ONO layers are chosen so that the final electrical thickness of the interpoly dielectric is not greater than 130 ⁇ .
- the deposited interpoly dielectric may be densified by thermal treatment using O 2 , N 2 , or H 2 O species.
- the process can be extended to form a complete memory cell 8 , as shown in FIG. 7 .
- source and drain regions 9 , 10 can be formed in the substrate and a second polysilicon layer can be deposited and defined to form a control gate 11 according to conventional procedures.
- memory cell designs other than that shown in FIG. 7 could be employed with a silicon nitride barrier layer 5 without departing from the invention.
- This embodiment comprises forming a single dielectric layer 7 on top of the nitride oxide barrier layer 5 .
- the steps described here below are alternative to steps 6a and 7a above.
- the interpoly dielectric 2 is formed using the single oxide interpoly option, on either batch or single wafers. Briefly, a single dielectric layer 7 is deposited onto the barrier layer 5 , as shown in FIG. 8 . The physical thickness of layer 7 is chosen so that the final electrical thickness of the dielectric interpoly is not greater than 130 Angstroms.
- the deposited single layer 7 may be densified by thermal treatment using O 2 , N 2 , or H 2 O species, as shown in FIG. 9 .
- the dielectric quality is improved such that the overall thickness of the layer can be reduced to 130 Angstroms or even more. Also, the resistance of said layer to oxidizing species allows an interpoly dielectric to be inserted which comprises a single oxide interpoly layer, and this even in devices for which the process provides subsequent oxidizing treatments.
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- General Physics & Mathematics (AREA)
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Abstract
A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.
Description
- 1. Field of the Invention
- The present invention relates to the manufacturing of semiconductor memory devices, such as non-volatile memories of the flash EEPROM (Electrically Erasable Programmable Read-Only Memories) type. Flash EEPROM memories can be erased with one operation in all the cells forming the memory.
- 2. Description of the Related Art
- As it is well known in this particular technical field, re-programmable non-volatile memory cells, in particular flash EEPROM cells, are structured as a floating gate FETs (Field-Effect Transistors) and have a dielectric layer, called the interpoly dielectric, provided between their floating and control gate regions, this dielectric layer functioning as an insulator to the charge stored in the floating gate. The absence or presence of charge in the floating gate effectively sets the logic state of the memory, which logic state is defined as 0 or 1 in the binary code.
- The above dielectric layer is obtained in different ways and made out of different materials. A common procedure is to deposit three dielectric layers successively onto the floating gate region, this region being formed by a layer of amorphous or polycrystalline silicon (polysilicon) deposited onto a thin layer of silicon oxide known as the tunnel oxide. The so obtained multiple dielectric layer comprises: a first layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon oxide. The resulting dielectric is known as the ONO or ONO interpoly dielectric, as it is shown in
FIG. 1 . - Within the ONO layer, the cell capability to retain its logic state is mainly guaranteed by the two layers of silicon oxide. Indeed, the nitride layer facilitates integration of the triple layer inside the flow of the device manufacturing process. During the manufacturing steps that follow the formation of the interpoly dielectric, treatments made with oxidizing species (O2, O, OH, H2O) are applied. The nitride acts as a barrier against the diffusion of the oxidizing species to the floating gate, since it is not permeable to said oxidizing species. Thus, its presence is effective to prevent further oxidation of the floating gate, and therefore, the thickness of the interpoly dielectric from being changed in the course of subsequent steps of the device manufacturing process. In the state of the art, the need to have a nitride layer maintained sufficiently thick to shield from subsequent thermal treatments, and the concurrent need to keep the retention capability of the ONO layer unchanged, disallows to reduce the overall electrical thickness of the triple layer below 140 Angstroms.
- Instead of ONO layer, a single oxide interpoly layer may be used whenever, in specific memory cells, the interpoly dielectric is not required to be particularly thin and/or no oxidizing treatments are provided after its formation. The thickness of the interpoly dielectric is, irrespective of its composition and forming method, jointly responsible of the capacitive coupling of the memory cell. Accordingly, it enters the setting of program and erase parameters, additionally to ensuring retention of the logic state over time.
- A pressing demand for increased miniaturization of electronic devices and reduced power absorption, and the consequent need for ever lower device bias voltages, is urging recourse to active dielectrics of reduced thickness at no trade-off of their performance characteristics.
- It has been proposed, in prior patent specifications to the filing date of this Application, that a layer of silicon nitride be included in the manufacturing of flash memory cells. This layer is used in the ONO triple layer, and used for protection against mechanical and thermal stressing during the intermediate manufacturing steps, but is removed before the manufacturing process is completed. Such are the teachings of U.S. Pat. No. 5,352,619, for instance, which is incorporated herein by reference in its entirety.
- U.S. Pat. No. 6,137,132, which is incorporated herein by reference in its entirety, discloses using the silicon nitride as an anti-reflection material for the subsequent photoetching application. According to U.S. Pat. No. 5,926,730, which is incorporated herein by reference in its entirety, the silicon nitride is provided at the interface between the bottom silicon layer and a conductive layer within an active dielectric stack.
- An embodiment of this invention provides a method of manufacturing a non-volatile memory cell, e.g., of the flash EEPROM type, with a substantially thinner interpoly dielectric than the prior art, yet capable of ensuring proper performance of the device in terms of electrical characteristics and capability to retain a programmed logic state. The combined thickness of the dielectric layers between the floating and control gate regions can be reduced at 130 Angstroms or less, thereby improving or maintaining still the cell characteristics. The cell characteristics are: good capacitive coupling of the floating gate to the control gate, small leakage through the active and passive dielectric layers, long-term retention of charge, and reduced power usage by reason of the memory cell components having lower resistivity.
- The process manufactures, on a very large integration scale as well as on a single wafer, non-volatile memory devices of the flash EEPROM type having the above-outlined features.
- The process interposes, between the floating gate and the ONO interpoly dielectric or the dielectric constituted only by silicon oxide, a layer of silicon nitride oxide (oxynitride) which is obtained by direct nitridation of the polysilicon surface in the floating gate region using radical nitrogen.
- By nitriding the polysilicon surface directly, the overall electrical thickness of the interpoly dielectric obtained by the combination of the nitride oxide layer and the following dielectric layer can be brought down to 130 Angstroms or less in the options of ONO layer or the single silicon oxide layer (single oxide interpoly).
- Another embodiment of the invention provides an interpoly dielectric layer structure that separates a floating gate region from a control gate region and includes a thin layer of silicon nitride oxide formed above the floating gate region.
- The features and advantages of the process and the structure according to the invention will be apparent from the following description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings.
-
FIG. 1 shows a photo representation of a conventional flash memory cell obtained by an electron microscope. - FIGS. 2 to 7 are schematically enlarged vertical cross-section views taken through a portion of a flash memory cell during a process according to an embodiment of the invention.
-
FIGS. 8 and 9 are schematically enlarged vertical cross-section views taken through a portion of a flash memory cell during a process according to a modified embodiment of the invention. - Referring to
FIGS. 1 and 2 , and particularly to the example shown inFIG. 2 , a substrate of a semiconductor material, e.g., monocrystalline silicon, is generally shown at 1 in schematic form. This substrate is subjected to a series of process phases as provided by a method according to an embodiment of this invention. - The process phases and the structures described hereinafter do not form a complete process flow for manufacturing integrated circuits. Indeed, the invention can be used in combination with currently used integrated circuits manufacturing techniques, and only such conventional steps as are necessary to an understanding of this invention will be discussed here.
- Drawing views that show cross-sections through portions of an integrated circuit during its manufacturing are not drawn to scale, but rather to highlight important features of the invention.
- The process of forming an interpoly
dielectric layer 2 for a non-volatile flash memory cell is carried out according to the steps hereafter described. It should be noted that the step of directly nitriding the amorphous or polycrystalline silicon layer is the same, and is followed by two alternative options, as concerning the dielectric depositing steps. - A first of these alternative steps is marked “a” hereinafter and involves depositing ONO interpoly dielectric by the CVD (Chemical Vapor Deposition) technique onto batch or single wafers.
- The second step is marked “b” hereinafter and involves depositing single oxide interpoly dielectric by the CVD (Chemical Vapor Deposition) technique onto batch or single wafers.
- 1a-b A layer of
tunnel oxide 3 is grown over thesubstrate 1 and followed by the deposition of an amorphous orpolycrystalline silicon layer 4, as shown inFIG. 1 . - 2a-b This process step may be carried out now, or alternatively as step 5a-b below. This step exposes a mask to define the floating gate region from the
silicon layer 4. Masking is followed by dry etching the amorphous or polycrystalline layer and then removing the residual resist from the wafer. - 3a-b The surface of the amorphous or
polycrystalline layer 4 used in forming the floating gate of the device is surface cleansed by means of chemicals in aqueous solution. This treatment is applied by either growing native chemical oxide, or by passivating said surface with Si—H bonds, or by wet or vapor HF-last, subsequent to the aqueous cleansing treatment. - 4a-b Advantageously, said surface is nitrided directly using radical nitrogen, on either batch or single wafers. Radical nitrogen (N+) is obtained by subjecting N2 molecules to a plasma. According to the design of the radical nitrogen generator, this technology, for example, is known as RPN (Remote Plasma Nitridation), DPN (Decoupled Plasma Nitridation), and MRG (Magnetic Radical Generator). The above direct nitriding operation is to grow a
thin layer 5 of silicon nitride oxide serving dual functions: - i) improving the interface quality between the floating gate and the interpoly dielectric; and
- ii) in those cases where the interpoly dielectric is a single oxide interpoly, preventing oxidizing chemicals, such as O2, O, OH, and H2O, from migrating to the floating gate during later treatments subjected to the memory device being formed.
- The
nitride oxide layer 5 can be regarded as a barrier layer. - The silicon
nitride oxide layer 5, obtained by direct surface nitridation oflayer 4 as explained above and shown inFIG. 4 , has preferably a thickness dimension of 0.5 to 5.0 nm. - The nitrogen distribution inside of said
layer 5, as estimated by the SIMS/TOF-SIMS method, should be no less than 1e22 at/cm3 as peak value, for a total amount of no less than 1e15 at/cm2. The direct surface nitridation processes using radical nitrogen are carried out at temperatures of 500° to 800° C. for 30 seconds (30″) to 3 minutes (3′) on single wafers. Either N2 alone or nitrogen/inert gas mixtures such as N2/He and N2/Ar may be used as the process gas. - 5a-b This step is carried out, only when step 2a-b is skipped, using the same procedure as for step 2a-b.
- 6a The
interpoly dielectric 2 can now be formed as an ONO (Oxide-Nitride-Oxide)triple layer 6, e.g., by using a CVD (Chemical Vapor Deposition) technique onto batch or single wafers. The physical thicknesses of the individual ONO layers are chosen so that the final electrical thickness of the interpoly dielectric is not greater than 130 Å. - 7a Optionally, the deposited interpoly dielectric may be densified by thermal treatment using O2, N2, or H2O species.
- After forming the
interpoly dielectric 2, the process can be extended to form acomplete memory cell 8, as shown inFIG. 7 . For example, source anddrain regions FIG. 7 could be employed with a siliconnitride barrier layer 5 without departing from the invention. - A modified embodiment of the inventive process will now be described with reference to FIGS. 8 to 9. This embodiment comprises forming a
single dielectric layer 7 on top of the nitrideoxide barrier layer 5. The steps described here below are alternative to steps 6a and 7a above. - 6b The
interpoly dielectric 2 is formed using the single oxide interpoly option, on either batch or single wafers. Briefly, asingle dielectric layer 7 is deposited onto thebarrier layer 5, as shown inFIG. 8 . The physical thickness oflayer 7 is chosen so that the final electrical thickness of the dielectric interpoly is not greater than 130 Angstroms. - 7b Optionally, the deposited
single layer 7 may be densified by thermal treatment using O2, N2, or H2O species, as shown inFIG. 9 . - The direct nitridation of the amorphous or polycrystalline silicon layer using radical nitrogen succeeds in obtaining a very thin layer having a high nitrogen content, which would be impossible to achieve by conventional nitridation techniques.
- By providing a barrier between the floating gate and the interpoly dielectric, the dielectric quality is improved such that the overall thickness of the layer can be reduced to 130 Angstroms or even more. Also, the resistance of said layer to oxidizing species allows an interpoly dielectric to be inserted which comprises a single oxide interpoly layer, and this even in devices for which the process provides subsequent oxidizing treatments.
- Thus, a combination of the nitridation technique with conventional CVD, in order to form the interpoly dielectric in either of the aforementioned options (i.e., ONO interpoly or single oxide interpoly), affords a significant advantage over prior art methods. This advantage is that of the reduction of the overall electrical thickness of the interpoly dielectric, down to 130 Angstroms or less while keeping the charge retention capability of the memory device unchanged.
- All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.
- From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims (20)
1. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising:
depositing a thin oxide layer onto a semiconductor substrate;
depositing a silicon layer onto said thin oxide layer to form a floating gate region of the memory cell; and
directly nitriding a surface of said silicon layer, using radical nitrogen, thereby forming a thin layer of silicon nitride oxide thereon;
depositing a silicon oxide layer directly on the silicon nitride oxide layer; and
forming a control gate directly on the silicon oxide layer.
2. A process according to claim 1 , wherein the thickness of the silicon nitride oxide layer, formed by the directly nitriding step, varies between 0.5 to 5.0 nm.
3. A process according to claim 1 , wherein a nitrogen distribution inside the silicon nitride oxide layer, formed by the directly nitriding step, is no less than 1 e22 at/cm3 as peak value, for a total amount of no less than 1 e15 at/cm2.
4. A process according to claim 1 , wherein the silicon oxide layer is formed, on either batch or single wafers systems, subsequently to said directly nitriding step.
5. A process according to claim 1 , wherein a masking step to define the floating gate region of the cell and a step of dry etching the silicon layer are carried out immediately before said directly nitriding step.
6. A process according to claim 1 wherein a masking step to define the floating gate region of the cell and a step of dry etching the silicon layer are carried out immediately after the directly nitriding step.
7. A process according to claim 1 , wherein the silicon nitride oxide and silicon oxide layers together have a thickness that is equal to or less than 130 Angstroms.
8. A process according to claim 7 , further comprising densifying said silicon oxide layer by heat treatment under an N2, H2O and O2 atmosphere.
9. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising:
forming a thin dielectric layer on a semiconductor substrate;
forming a first conductive layer on said thin dielectric layer, the first conductive layer forming a floating gate region having an entire top surface;
directly nitriding a surface of the first conductive layer, using radical nitrogen, thereby forming a barrier layer on the entire top surface of the floating gate region;
forming interlevel dielectric layer on the barrier layer, wherein the interpoly dielectric is formed above the barrier layer and includes only a single layer of silicon oxide; and
forming a second conductive layer directly on the interlevel dielectric layer.
10. The process of claim 9 , wherein the barrier layer includes silicon nitride oxide having a thickness between 0.5 to 5.0 nm.
11. The process of claim 9 , wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1e22 at/cm3 as peak value, for a total amount of no less than 1 e15 at/cm2.
12. The process of claim 9 , wherein the interlevel dielectric layer is formed after forming the barrier layer.
13. The process of claim 9 , further comprising defining the first conductive layer to form the floating gate region of the memory cell immediately before forming the barrier layer.
14. The process of claim 9 , further comprising defining the first conductive layer to form the floating gate region of the memory cell immediately after forming the barrier layer.
15. The process of claim 9 , wherein the single layer of silicon oxide is formed by CVD.
16. A non-volatile memory cell, comprising:
a tunnel dielectric layer positioned on a semiconductor substrate that includes source and drain regions;
a floating gate formed on the tunnel dielectric layer;
an interlevel dielectric layer positioned above the floating gate region, the interlevel dielectric layer including only a single silicon oxide layer;
a control gate region positioned above the interlevel dielectric layer; and
a barrier layer of silicon nitride oxide formed between the floating gate region and the interlevel dielectric layer, the barrier layer having a thickness between 0.5 to 5.0 nm.
17. The memory cell of claim 16 , wherein the barrier layer is directly above and contacts a top surface of the floating gate.
18. The memory cell of claim 17 wherein the single silicon oxide layer directly contacts the barrier layer and directly contacts the control gate region.
19. The memory cell of claim 16 , wherein the barrier layer intervenes between the interlevel dielectric layer and the floating gate such that no portion of the floating gate contacts the interlevel dielectric layer.
20. The memory cell of claim 16 , wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1 e22 at/cm3 as peak value, for a total amount of no less than 1 e15 at/cm2.
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EP02425044A EP1333473A1 (en) | 2002-01-31 | 2002-01-31 | Interpoly dielectric manufacturing process for non volatile semiconductor memories |
EP02425044.1 | 2002-01-31 | ||
US10/356,351 US7084032B2 (en) | 2002-01-31 | 2003-01-30 | Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories |
US11/476,361 US20060246665A1 (en) | 2002-01-31 | 2006-06-27 | Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories |
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EP1333473A1 (en) | 2003-08-06 |
US7084032B2 (en) | 2006-08-01 |
US20030183869A1 (en) | 2003-10-02 |
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