CN101438392A - 非易失纳米晶体存储器及其方法 - Google Patents
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- 239000002159 nanocrystal Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 103
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 41
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims 2
- 229910052732 germanium Inorganic materials 0.000 claims 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 229910052735 hafnium Inorganic materials 0.000 claims 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims 2
- 229910052746 lanthanum Inorganic materials 0.000 claims 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 230000007423 decrease Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 230000005524 hole trap Effects 0.000 abstract 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 25
- 230000008901 benefit Effects 0.000 description 7
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 3
- 239000001272 nitrous oxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
一种纳米晶体非易失存储器(NVM)(10)具有控制栅极(26)和纳米晶体(16)之间的介质(22),其具有足以减少介质(22)中能够俘获电子的位置的氮含量。这是通过使氮浓度逐渐变化实现的。氮浓度在纳米晶体(16)附近最高,其中电子/空穴陷阱的浓度趋向于最高,并且朝向控制栅极(26)减小,在控制栅极处电子/空穴陷阱的浓度较低。这已被发现具有减少可俘获电荷的位置数目的有利作用。
Description
技术领域
本发明涉及具有用于存储的纳米晶体的非易失存储器,更具体地,涉及该纳米晶体的绝缘以及该纳米晶体上的绝缘。
背景技术
已经发现,由于纳米晶体存储器对栅介质缺陷引起的电荷泄漏具有增加的免疫力,因此优于浮栅存储器。纳米晶体存储器中的一个问题是,关于在控制栅极下面的介质叠层中俘获的电子的电势。在将电子热载流子注入到纳米晶体中的过程中出现该问题。未由纳米晶体俘获的小部分电子可能在介质叠层中被俘获,这导致了阈值电压的移位。由于介质叠层中俘获的这些电子随着重复的编程和擦除周期积累,因此它们是不可电擦除的。因此阈值电压的移位继续随着重复的编程和擦除操作增加,并且需要尝试减轻该效应的电路设计。除此以外,由于内部电场伴随着外部偏置工作,因此介质俘获的电荷可能导致可靠性的劣化。例如,控制栅极和纳米晶体之间的介质叠层部分中俘获的电子可能通过纳米晶体和基板之间的介质叠层部分加速隧穿损失,使利用电子编程的纳米晶体的数据保持劣化。
因此,需要一种方法和结构,其减轻和/或减少一个或多个该问题。
附图说明
本发明借助于示例说明,并且不限于附图,在附图中相似的参考符号表示相似的元素,并且其中:
图1是根据本发明的实施例的一个处理阶段中的器件结构的截面;
图2是后继处理阶段中的图1的器件结构的截面;
图3是后继处理阶段中的图2的器件结构的截面;
图4是后继处理阶段中的图3的器件结构的截面;以及
图5是后继处理阶段中的图4的结构的截面;并且
本领域的技术人员应当认识到,图中的元素是出于简化和清楚的目的说明的,因此没有必要依比例绘制。例如,图中的某些元素的尺寸可以相对于其他元素放大,有助于改善对本发明的实施例的理解。
具体实施方式
在一个方面,纳米晶体非易失存储器(NVM)具有控制栅极和纳米晶体之间的介质,其具有足以减少该介质中能够俘获电子的位置的氮含量。这是通过使氮浓度逐渐变化实现的。氮浓度在纳米晶体附近最高,其中电子/空穴陷阱的浓度趋向于最高,并且朝向控制栅极减小,在控制栅极处电子/空穴陷阱的浓度较低。这已被发现具有减少可俘获电荷的位置数目的有利作用。通过参考附图和下面的描述,这得到了更好的理解。
图1示出了一个半导体器件10,其包括基板12、基板12上的栅介质14、栅介质14上的多个纳米晶体16。基板12优选地是体硅基板,但是也可以是SOI基板,并且可以是不同于硅的半导体材料。栅介质层14优选地是生长的氧化物,其厚度为50~100埃,并且具有逐渐变化的氮浓度,其在距离纳米晶体16最远且距离基板12最近处最高。该示例中的纳米晶体16由硅制成,并且具有5el1~1.2el2/平方厘米的密度。纳米晶体16的尺寸在约3~10纳米之间变化。纳米晶体16优选地是通过化学淀积而淀积的,但是也可以使用其他的工艺。用于形成纳米晶体的其他工艺包括,薄的无定形硅层的再结晶以及预制纳米晶体的淀积。在纳米晶体形成之后,通过使用氧化亚氮使其氧化,可以将其钝化。
图2示出了一个在纳米晶体16上面和周围形成掺杂氮化物的氧化物层18之后的半导体器件10。其厚度优选地是3~5纳米,并且形成了纳米晶体同仍未形成的控制栅极之间的介质的第一部分。层18中的氮含量是逐渐变化的。距离纳米晶体最近处氮含量最高,并且约为5~10原子百分数。优选地,通过使小量的氨同诸如二氯硅烷和氧化亚氮的氧化物形成气体反应,并且逐渐地降低氨的流量,实现了该梯度。一种替换方案是,在一连串注入步骤中将氮注入到氧化物层中。最重剂量的注入具有最高的能量,而最轻剂量的注入具有最低的能量。该注入优选地是在远程等离子体环境中执行的,以防止对层18的损坏。在后继的退火步骤过程中,氧化物层中的氮使最初形成的氧化物层中的悬挂键饱和。特别地,对热电子具有弱免疫力的硅-氢键被转化为更牢固的硅-氮键。由于该键缺陷的最高浓度位于介质层之间的界面处,在该情况中位于层14和18之间以及纳米晶体16和介质层18之间的界面处,因此在这些界面区域中需要较高的氮浓度。离开该界面越远,键缺陷越少,并且需要越少的氮。这些区域中的过多的氮用作电子/空穴陷阱,对于存储器器件是有害的。此外,可以将氧注入到层18中,以协助增加浓度。
图3示出了在层18上面形成介质层20之后的半导体器件10。介质层20优选地是氧化硅,并且在约500~900摄氏度下,在化学气相淀积腔中,通过使诸如硅烷或二氯硅烷的含硅前体同诸如氧或氧化亚氮的氧化剂反应,淀积该介质层20。层20的厚度典型地为4~10纳米。
图4示出了在对层20执行远程等离子体氮化以形成氮化层22之后的半导体器件10。氮化层22中的氮含量优选地小于约2原子百分数。由于通过CVD实现该小的氮含量是困难的,因此远程等离子体淀积是优选方法。结合含氮物质的流量的减小,远程等离子体的能量可以随时间减小,以便于实现氮化层22中的逐渐变化的氮浓度。在该情况中,较高的氮浓度位于层18和22的界面处,并且较低的氮浓度位于层22的顶部表面处。注入氮也是一种替换方案,但是远程等离子体是优选的,原因在于,相比于注入,其在层20的表面处以及附近具有较小的损坏。该远程等离子体淀积,结合足够的能量,还可用于将额外的氮引入到层18中。此外,可以将氧注入到层20中,以协助增加浓度。
在执行氮化之后,优选地在大于700摄氏度或者更高的温度下,执行退火步骤。这些退火步骤中的第一退火步骤是在约高于800摄氏度的温度下在诸如氮或氩的惰性环境中完成的。该步骤有助于氮键合,并且从层18和22中逐出了自由的氢。这些退火步骤中的第二退火步骤是在稀释的氧化环境中执行的,并且用于移除仍可能存在的非化学配比缺陷。这些退火步骤中的第三退火步骤是在接近或者大约玻璃化转变温度下执行的,其约为950摄氏度。该回流条件过程中的高度的原子运动有助于该结构释放层18和22的应力。第二和第三退火步骤能够组合为单一的退火步骤。该退火温度优选地不超过1100摄氏度。
图5示出了执行已知步骤用于形成NVM器件之后的半导体器件10,该NVM器件包括控制栅极26、控制栅极26周围的侧壁隔层28、基板12中的位于控制栅极26一侧的源极/漏极区域30、以及基板12中的位于控制栅极26另一侧的源极/漏极区域32。所得到的图5的半导体器件10是用作NVM器件的晶体管,并且用于形成该器件的阵列。具有所述氮浓度的层18和22减小了由于电子/空穴俘获引起的阈值移位。所述方法的另一优点是,层18和22具有增加的浓度。不同于热生长的氧化物,诸如层14,淀积氧化物的密度较小,并且化学配比是不完美的。这典型地可由淀积氧化物相比于生长氧化物的显著较快的刻蚀速率看出。单独的退火对密度增加的影响是小的。通过远程等离子体注入获得的原子氮和氧的存在,由于较高的反应能力,有助于未饱和的键合完成,并且导致了密度较高的氧化物并因此改善了电气特性,诸如击穿电场和热载流子免疫性。
在前面的说明书中,参考具体的实施例描述了本发明。然而,本领域的普通技术人员应当认识到,不在偏离所附权利要求中阐述的本发明的范围的前提下,可以进行多种修改和变化。例如,栅介质层14被描述为生长氧化物,但是相反地,其也可以是淀积的高k介质。因此,说明书和附图应被视为说明性的,而非限制性的,并且所有该修改方案应涵盖于本发明的范围内。
上文针对具体的实施例描述了益处、其他优点和对问题的解决方案。然而,益处、优点、对问题的解决方案、以及可以使任何益处、优点、解决方案出现或变得更加显著的任何因素,不应被解释为任何或所有权利要求的关键的、必需的或基本的特征或要素。如此处使用的术语“包括”或其任何变化形式,目的在于涵盖非排他性的内含物,由此包括一系列要素的工艺、方法、物体或装置不仅包括这些列出的要素,而且可以包括未明确列出的或者对于该工艺、方法、物体或装置是固有的其他要素。
Claims (31)
1.一种用于形成半导体器件的方法,包括:
提供半导体基板;
在半导体基板的表面上形成第一绝缘层;
在第一绝缘层的表面上形成纳米晶体层;并且
在纳米晶体层上面形成具有逐渐变化的氮含量的第二绝缘层。
2.如权利要求1所述的方法,进一步包括在第二绝缘层上面形成第三绝缘层,其中第三绝缘层相比第二绝缘层,具有相对较低的氮含量。
3.如权利要求2所述的方法,其中形成第三绝缘层包括将第三绝缘层形成为具有小于第二绝缘层的逐渐变化的氮含量的最低氮含量的氮含量。
4.如权利要求2所述的方法,进一步包括,在温度为700~1100摄氏度的包括氧的环境中使半导体器件退火。
5.如权利要求2所述的方法,其中形成第三绝缘层进一步包括使用等离子体氮化来调节第三绝缘层的氮含量。
6.如权利要求5所述的方法,其中使用等离子体氮化包括随时间减小等离子体氮化源的等离子能量,以形成逐渐变化的氮含量。
7.如权利要求5所述的方法,其中使用等离子体氮化包括随时间减小氮源的流量,以形成逐渐变化的氮含量。
8.如权利要求1所述的方法,其中形成第二绝缘层包括使用氧氮化硅形成第二绝缘层。
9.如权利要求1所述的方法,其中形成第二绝缘层包括形成具有约2原子百分数~约10原子百分数的峰值氮含量的第二绝缘层。
10.如权利要求1所述的方法,其中形成第二绝缘层进一步包括使用等离子体氮化来调节第二绝缘层的氮含量。
11.如权利要求10所述的方法,其中使用等离子体氮化包括随时间减小等离子体氮化源的等离子能量,以形成逐渐变化的氮含量。
12.如权利要求10所述的方法,其中使用等离子体氮化包括随时间减小氮源的流量,以形成逐渐变化的氮含量。
13.如权利要求1所述的方法,其中形成第二绝缘层进一步包括:利用包括硅的流动气体、氧化源和氮源,使用化学气相淀积。
14.如权利要求13所述的方法,其中形成第二绝缘层进一步包括随时间减小氮源的流量,以形成逐渐变化的氮含量。
15.如权利要求1所述的方法,其中形成第一绝缘层包括形成具有随着离开半导体基板的距离增加而下降的氮含量的第一绝缘层。
16.如权利要求1所述的方法,其中形成第二绝缘层包括:在同纳米晶体层的界面处具有相对较多的氮,并且具有随着离开纳米晶体层的距离增加而相对减小的氮。
17.如权利要求1所述的方法,其中纳米晶体层的纳米晶体包括硅、锗中的至少一个或者金属。
18.如权利要求1所述的方法,进一步包括使用包括氮的材料涂覆纳米晶体。
19.如权利要求1所述的方法,其中形成第一绝缘层包括由包括硅、铪、镧和铝中的至少一个的氧化物形成第一绝缘层。
20.如权利要求1所述的方法,其中形成第二绝缘层进一步包括使用等离子体氧化来改善第二绝缘层的化学配比。
21.一种半导体器件,包括:
半导体基板;
第一绝缘层,其在半导体基板的表面上形成;
纳米晶体层,其在第一绝缘层的表面上形成;和
第二绝缘层,其在纳米晶体层上面形成,具有逐渐变化的氮含量。
22.如权利要求21所述的半导体器件,进一步包括第三绝缘层,其在第二绝缘层上面形成,其中第三绝缘层相比第二绝缘层,具有相对较低的氮含量。
23.如权利要求22所述的半导体器件,其中第三绝缘层具有小于第二绝缘层的逐渐变化的氮含量的最低氮含量的氮含量。
24.如权利要求21所述的半导体器件,其中第二绝缘层包括氧氮化硅。
25.如权利要求21所述的半导体器件,其中第二绝缘层具有约2原子百分数~约10原子百分数的峰值氮含量。
26.如权利要求21所述的半导体器件,其中第一绝缘层具有随着离开半导体基板的距离增加而下降的氮含量。
27.如权利要求21所述的半导体器件,其中第二绝缘层在同纳米晶体层的界面处具有相对较多的氮,并且具有随着离开纳米晶体层的距离增加而相对减小的氮。
28.如权利要求21所述的半导体器件,其中纳米晶体层的纳米晶体包括硅、锗中的至少一个或者金属。
29.如权利要求21所述的半导体器件,进一步包括涂覆有包括氮的层的纳米晶体。
30.如权利要求21所述的半导体器件,其中第一绝缘层由包括硅、铪、镧和铝中的至少一个的氧化物形成。
31.如权利要求21所述的半导体器件,其中半导体器件是在纳米晶体层中存储电荷的非易失存储器单元。
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US11/043,826 US7361567B2 (en) | 2005-01-26 | 2005-01-26 | Non-volatile nanocrystal memory and method therefor |
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Country | Link |
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US (1) | US7361567B2 (zh) |
EP (1) | EP1844492B1 (zh) |
JP (1) | JP4980931B2 (zh) |
KR (1) | KR101219067B1 (zh) |
CN (1) | CN101438392A (zh) |
AT (1) | ATE473515T1 (zh) |
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CN102709330A (zh) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | 一种具有低操作电压的be-sonos结构器件及形成方法 |
CN102709330B (zh) * | 2012-05-22 | 2016-04-27 | 上海华力微电子有限公司 | 一种具有低操作电压的be-sonos结构器件及形成方法 |
Also Published As
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---|---|
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JP4980931B2 (ja) | 2012-07-18 |
KR101219067B1 (ko) | 2013-01-18 |
WO2006080999A2 (en) | 2006-08-03 |
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