TWI407492B - 非揮發性奈晶記憶體及其製造方法 - Google Patents

非揮發性奈晶記憶體及其製造方法 Download PDF

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TWI407492B
TWI407492B TW095100396A TW95100396A TWI407492B TW I407492 B TWI407492 B TW I407492B TW 095100396 A TW095100396 A TW 095100396A TW 95100396 A TW95100396 A TW 95100396A TW I407492 B TWI407492 B TW I407492B
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insulating layer
forming
nitrogen content
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Rajesh A Rao
Ramachandran Muralidhar
Bruce E White
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Freescale Semiconductor Inc
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Description

非揮發性奈晶記憶體及其製造方法
本發明係關於用於儲存之具有奈晶之非揮發性記憶體，且更特定言之，係關於此等奈晶之絕緣及此等奈晶上之絕緣。
吾人己發現：歸因於奈晶記憶體對經由閘極介電缺陷之電荷漏泄之抗擾性增加，奈晶記憶體優於浮動閘極記憶體。奈晶記憶體中之一問題為在控制閘極下之介電堆疊中電子陷落之電位。此問題發生於電子之熱載子注入奈晶期間。電子之未由奈晶捕獲之一部分可被捕獲於介電堆疊中，此導致臨限電壓升高。捕獲於介電堆疊中之電子係不可電抹除的，因此隨著重複按程式操作及抹除週期而積聚。因此，臨限電壓伴隨著重複的程式抹除操作而繼續升高且需要嘗試減輕此效應之電路設計。除此之外，歸因於內部電場伴隨外部偏壓工作，介電捕獲電荷可導致可靠性降級。舉例而言，藉由加速穿過奈晶與基板間之介電堆疊之部分的穿隧損失，捕獲於控制閘極與奈晶間的介電堆疊之部分中之電子可使奈晶之以電子程式化的資料保存能力降級。
因此，需要減輕及/或減少此等問題之一或多個之方法及結構。
一奈晶非揮發性記憶體(NVM)(10)具有一介於控制閘極(26)與奈晶(16)之間的介電質(22)，該等奈晶具有足夠氮含量以減少介電質(22)中可捕獲電子之位置。此係藉由將該氮濃度分級而達成。該氮濃度在電子/電洞陷阱之濃度傾向於最高之奈晶(16)附近最高，且朝向電子/電洞陷阱之濃度較低之控制閘極(26)處降低。已發現此具有減少可捕獲電荷之位置之數量的有益效應。
在一態樣中，奈晶非揮發性記憶體(NVM)在控制閘極與奈晶之間具有介電質，奈晶具有足夠氮含量以減少介電質中可捕獲電子之位置。此係藉由將氮濃度分級而達成。氮濃度在電子/電洞陷阱之濃度傾向於最高之奈晶附近最高，且朝向電子/電洞陷阱之濃度較低之控制閘極處降低。此發現具有減少可捕獲電荷之位置之數目的有益效應。參照圖式及下列描述可更好地理解。
圖1所示為一半導體裝置10，其包含基板12、位於基板12上之閘極介電14、位於閘極介電14上之複數個奈晶16。基板12較佳為塊體矽基板，但亦可為SOI基板，且可為與矽不同的半導體材料。閘極介電層14較佳為厚度為50埃至100埃之生長氧化物，且具有分級氮含量(在距離奈晶16最遠且距離基板12最近處最高)。此實例中之奈晶16由矽製成且具有介於每平方公分五千億(5e11)與1.2e12之間的密度。奈晶16之尺寸在約3奈米至10奈米之間變化。奈晶16較佳藉由化學沉積法沉積，但是亦可使用其他方法。形成奈晶之其他方法包括再結晶一薄的矽之非晶形層以及沉積預製奈晶。奈晶形成後，藉由使用氧化亞氮使奈晶16氧化，可使其鈍化。
圖2所示為在奈晶16之上及周圍形成氮摻雜氧化層18後之半導體裝置10。氮摻雜氧化層18較佳厚度為約3奈米至5奈米，且在奈晶與尚未形成之控制閘極之間形成第一部分介電質。層18中之氮含量係分級的。距離奈晶最近處為最高氮含量且起始於約5－10原子百分比。距離奈晶16越遠氮含量越低，最終低於約2原子百分比。較佳地，藉由將小數量之氨與諸如二氯矽烷及氧化亞氮之氧化形成氣體反應且逐漸減少氨的流動速率來達到此分級。一替代方法為以一連串植入步驟將氮植入氧化層中。最重的劑量植入具有最高的能量，且最輕的劑量植入具有最低的能量。較佳地，此植入在一遠端電漿環境中執行，以防止損害層18。在隨後的退火步驟期間氧化層中之氮使原先形成的氧化層中之懸鍵飽和。詳言之，將對熱電子具有弱抗擾性之矽－氫鍵結轉換為更穩固的矽－氮鍵結。由於此等鍵結缺陷之最高濃度在介電層之間(在此例中為層14與層18之間以及在奈晶16與介電層18之間)之介面處，在此等介面區域中需要較高濃度之氮。越遠離介面處，鍵結缺陷越少，且需要越少的氮。此等區域中之過多的氮由於充當了電子/電洞陷阱而對記憶體裝置有害。此外，可將氧植入層18中以輔助增濃。
圖3所示為在層18上形成介電層20後之半導體裝置10。介電層20較佳為二氧化矽且藉由將諸如矽烷或二氯矽烷之一含矽前驅體與諸如氧或氧化亞氮之氧化劑在一約500攝氏度與900攝氏度之間的化學氣相沉積室中反應而沉積。通常，層20之厚度介於四奈米與十奈米間。
圖4所示為在執行層20之遠端電漿氮化以形成氮化層22後之半導體裝置10。較佳地，氮化層22中之氮含量小於約2原子百分比。由於藉由CVD難以達到此小的氮含量，故遠端電漿沉積為較佳的方法。隨著時間的過去，可減少遠端電漿之能量，同時減少含氮化合物之流動，以便在氮化層22中達成分級的氮濃度。在此狀況下，較高的氮濃度在層18與層22之介面處，且較低的濃度在層22之頂面處。植入氮亦為一替代方法，但是遠端電漿為較佳，此係由於較之植入，在層20之表面及其附近存在較少損害。由於具有足夠的能量，此遠端電漿沉積亦可用於將額外的氮引入層18中。此外，可將氧植入層20以輔助增濃。
在執行氮化以後，較佳在約大於700攝氏度或更高之溫度執行退火步驟。退火步驟之第一步在約大於800攝氏度之諸如氮或氬之惰性環境中進行。此步驟有助於氮鍵結且自層18及層22排除了游離氫。退火步驟之第二步係在稀釋氧化環境中執行且用於移除可能仍存在的非化學計量缺陷。退火步驟之第三步係在接近或約玻璃轉移溫度(約為950攝氏度)下執行。在此回焊狀態期間之高溫原子運動有助於該結構鬆馳層18及層22的應力。可將第二及第三步驟組合為單一退火步驟。較佳地，退火溫度不超過1100攝氏度。
圖5所示為執行已知步驟以形成一NVM裝置以後之半導體裝置10，該NVM裝置包含一控制閘極26、控制閘極26附近之一側壁間隔物28、控制閘極26之一側上及基板12中之源極/汲極區30以及控制閘極26之另一側上及基板12中之源極/汲極區32。圖5之所得半導體裝置10為一電晶體，該電晶體可用於NVM裝置且用於形成此等裝置之陣列。由於電子/電洞捕獲，具有所述氮含量之層18及層22減少了臨限移位。所述方法之另一益處在於層18及層22具有增加的密度。與諸如層14之熱生長氧化物不同，沉積氧化物較不密集且化學計量不完全。較之生長氧化物，此通常可表現在沉積氧化物之顯著更快的蝕刻速率上。退火自身對增加密度幾乎無影響。藉由遠端電漿植入獲取之原子氮及氧之存在有助於不飽和鍵結完成(由於更高的反應性)，且導致氧化物更密集且結果改良了諸如擊穿電場及熱載子抗擾性之電特徵。
在前述說明中，已參照特定實施例描述了本發明。然而，熟習該項技術者瞭解，在不脫離下文申請專利範圍中所提出之本發明的範疇之情況下，可進行各種修改及變化。舉例而言，閘極介電層14描述為生長氧化物，但是其可代之以高k沉積介電質。因此，應認為本說明及圖式係說明性的而非限制性的，且意欲將所有此等修改皆包括於本發明之範疇中。
上文已關於特定實施例而描述了本發明之益處、其他優勢以及問題之解決方案。然而，並不認為該等益處、優勢、問題的解決方案以及可帶來任何將發生或變得更顯著之益處、優勢或解決方案的任何元件係任何或所有申請專利範圍之關鍵、必需或本質特徵或元件。如本文所使用，術語"包含"或其任何變體皆意欲涵蓋一非排除式包括，使得包含一系列元件之製程、方法、物品或器件不僅包括彼等元件，而且可包括未清楚列出或此製程、方法、物品或器件固有之其他元件。
10．．．(NVM)記憶體
12．．．基板
14．．．閘極介電層
16．．．奈晶
18．．．介電層
20．．．介電層
22．．．層
26．．．控制閘極
28．．．側壁間隔物
30．．．汲極區
32．．．汲極區
圖1為依據本發明之一實施例在一處理階段之裝置結構的截面；圖2為圖1之裝置結構在後續處理階段的截面；圖3為圖2之裝置結構在後續處理階段的截面；圖4為圖3之裝置結構在後續處理階段的截面；以及圖5為圖4之結構在後續處理階段的截面；且熟習此項技術者應瞭解，圖式中之元件係為了簡潔、清晰而加以說明，且不必按比例繪製。舉例而言，圖中某些元件之尺寸可相對於其他元件而加以誇示，以幫助提高對本發明之實施例的理解。
10．．．(NVM)記憶體
12．．．基板
14．．．閘極介電層
16．．．奈晶
18．．．介電層
22．．．層
26．．．控制閘極
28．．．側壁間隔物
30．．．汲極區
32．．．汲極區

Claims (31)

  1. 一種用於形成一半導體裝置之方法，其包含：提供一半導體基板；在該半導體基板之一表面上形成一第一絕緣層；在該第一絕緣層之一表面上形成一奈晶層；及在該奈晶層上形成一具有一分級氮含量之第二絕緣層。
  2. 如請求項1之方法，其進一步包含在該第二絕緣層上形成一第三絕緣層，其中該第三絕緣層較之該第二絕緣層具有相對較低的氮含量。
  3. 如請求項2之方法，其中形成該第三絕緣層包含形成該第三絕緣層以具有較該第二絕緣層之該分級氮含量之最低氮含量更少的氮含量。
  4. 如請求項2之方法，其進一步包含在攝氏700度至1100度之溫度下在包含氧之環境中對該半導體裝置退火。
  5. 如請求項2之方法，其中形成該第三絕緣層進一步包含使用電漿氮化來調變該第三絕緣層之氮含量。
  6. 如請求項5之方法，其中使用電漿氮化包含隨時間而減少一電漿氮化源之電漿能量，以形成該第三絕緣層之一分級氮含量。
  7. 如請求項5之方法，其中使用電漿氮化包含隨時間而減少一氮源之流動，以形成該第三絕緣層之一分級氮含量。
  8. 如請求項1之方法，其中形成該第二絕緣層包含使用氮氧化矽形成該第二絕緣層。
  9. 如請求項1之方法，其中形成該第二絕緣層包含形成具有約二原子百分比至約十原子百分比之峰值氮含量之該第二絕緣層。
  10. 如請求項1之方法，其中形成該第二絕緣層進一步包含使用電漿氮化來調變該第二絕緣層之氮含量。
  11. 如請求項10之方法，其中使用電漿氮化包含隨時間而減少一電漿氮化源之電漿能量，以形成該分級氮含量。
  12. 如請求項10之方法，其中使用電漿氮化包含隨時間而減少一氮源之流動，以形成該分級氮含量。
  13. 如請求項1之方法，其中形成該第二絕緣層進一步包含使用由包含矽、氧化源及氮化源之流動氣體而執行之化學氣相沉積。
  14. 如請求項13之方法，其中形成該第二絕緣層進一步包含隨時間而減少一氮源之流動，以形成該分級氮含量。
  15. 如請求項1之方法，其中形成該第一絕緣層包含形成具有隨距離該半導體基板越遠而減少之氮含量的該第一絕緣層。
  16. 如請求項1之方法，其中形成該第二絕緣層包含在與該奈晶層之一介面處具有相對較多的氮以及隨距離該奈晶層越遠而具有相對較少的氮。
  17. 如請求項1之方法，其中該奈晶層之奈晶包含矽、鍺或一金屬中之至少一者。
  18. 如請求項1之方法，其進一步包含將包含氮之材料塗佈於該等奈晶上。
  19. 如請求項1之方法，其中形成該第一絕緣層包含自包含矽、鉿、鑭及鋁中之至少一者之氧化物形成該第一絕緣層。
  20. 如請求項1之方法，其中形成該第二絕緣層進一步包含使用電漿氧化來改良該第二絕緣層之化學計量。
  21. 一種半導體裝置，其包含：一半導體基板；在該半導體基板之一表面上形成之一第一絕緣層；在該第一絕緣層之一表面上形成之一奈晶層；以及在該奈晶層上形成之一具有一分級氮含量之第二絕緣層。
  22. 如請求項21之半導體裝置，其進一步包含一在該第二絕緣層上形成之第三絕緣層，其中該第三絕緣層較之該第二絕緣層具有相對較低的氮含量。
  23. 如請求項22之半導體裝置，其中該第三絕緣層具有較該第二絕緣層之該分級氮含量的最低氮含量更少之氮含量。
  24. 如請求項21之半導體裝置，其中該第二絕緣層包含氮氧化矽。
  25. 如請求項21之半導體裝置，其中該第二絕緣層具有約二原子百分比至約十原子百分比之一峰值氮含量。
  26. 如請求項21之半導體裝置，其中該第一絕緣層具有隨距離該半導體基板越遠而減少之氮含量。
  27. 如請求項21之半導體裝置，其中該第二絕緣層包含在與 該奈晶層之一介面處具有相對較多的氮以及隨距離該奈晶層越遠而具有相對較少的氮。
  28. 如請求項21之半導體裝置，其中該奈晶層之奈晶包含矽、鍺或一金屬中之至少一者。
  29. 如請求項21之半導體裝置，其進一步包含塗佈有包含氮之一層體之奈晶。
  30. 如請求項21之半導體裝置，其中該第一絕緣層自包含矽、鉿、鑭及鋁中之至少一者的氧化物形成。
  31. 如請求項21之半導體裝置，其中該半導體裝置為一在該奈晶層中儲存電荷之非揮發性記憶體單元。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100673205B1 (ko) * 2004-11-24 2007-01-22 주식회사 하이닉스반도체 플래쉬 메모리소자의 제조방법
US20060166435A1 (en) * 2005-01-21 2006-07-27 Teo Lee W Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics
US7338894B2 (en) * 2005-01-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor device having nitridated oxide layer and method therefor
JP2007036025A (ja) * 2005-07-28 2007-02-08 Nec Electronics Corp 不揮発性メモリ半導体装置およびその製造方法
US7525149B2 (en) * 2005-08-24 2009-04-28 Micron Technology, Inc. Combined volatile and non-volatile memory device with graded composition insulator stack
TWI289336B (en) * 2005-11-07 2007-11-01 Ind Tech Res Inst Nanocrystal memory component, manufacturing method thereof and memory comprising the same
US7767588B2 (en) * 2006-02-28 2010-08-03 Freescale Semiconductor, Inc. Method for forming a deposited oxide layer
US7773493B2 (en) * 2006-09-29 2010-08-10 Intel Corporation Probe-based storage device
US8686490B2 (en) * 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US20080150009A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US20080150004A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US7846793B2 (en) * 2007-10-03 2010-12-07 Applied Materials, Inc. Plasma surface treatment for SI and metal nanocrystal nucleation
US7799634B2 (en) * 2008-12-19 2010-09-21 Freescale Semiconductor, Inc. Method of forming nanocrystals
US7871886B2 (en) 2008-12-19 2011-01-18 Freescale Semiconductor, Inc. Nanocrystal memory with differential energy bands and method of formation
US8021970B2 (en) * 2009-03-20 2011-09-20 Freescale Semiconductor, Inc. Method of annealing a dielectric layer
JP6125846B2 (ja) * 2012-03-22 2017-05-10 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
CN102709330B (zh) * 2012-05-22 2016-04-27 上海华力微电子有限公司 一种具有低操作电压的be-sonos结构器件及形成方法
CN102709315A (zh) * 2012-05-22 2012-10-03 上海华力微电子有限公司 一种具有锥形能带的be-sonos结构器件及形成方法
US8994006B2 (en) * 2012-10-02 2015-03-31 International Business Machines Corporation Non-volatile memory device employing semiconductor nanoparticles
US8895397B1 (en) 2013-10-15 2014-11-25 Globalfoundries Singapore Pte. Ltd. Methods for forming thin film storage memory cells
US9171858B2 (en) 2013-12-30 2015-10-27 Globalfoundries Singapore Pte. Ltd. Multi-level memory cells and methods for forming multi-level memory cells
US9953841B2 (en) * 2015-05-08 2018-04-24 Macronix International Co., Ltd. Semiconductor device and method of fabricating the same
DE102020100099A1 (de) * 2019-09-30 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gatestrukturen in halbleitervorrichtungen
US11756832B2 (en) * 2019-09-30 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structures in semiconductor devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297095B1 (en) * 2000-06-16 2001-10-02 Motorola, Inc. Memory device that includes passivated nanoclusters and method for manufacture
US6320784B1 (en) * 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof
US6413819B1 (en) * 2000-06-16 2002-07-02 Motorola, Inc. Memory device and method for using prefabricated isolated storage elements
US6444545B1 (en) * 2000-12-19 2002-09-03 Motorola, Inc. Device structure for storing charge and method therefore
TW525263B (en) * 2000-09-28 2003-03-21 Chartered Semiconductor Mfg Formation of interfacial oxide layer at the Si3N4/Si interface by H2/O2 annealing
TW569377B (en) * 2002-03-20 2004-01-01 Taiwan Semiconductor Mfg Improvement method for thickness uniformity of super-thin nitridation gate dielectric

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2001263370A1 (en) * 2000-06-16 2002-01-02 Motorola, Inc. Memory device including nanoclusters and method for manufacture
JP2002261175A (ja) 2000-12-28 2002-09-13 Sony Corp 不揮発性半導体記憶装置およびその製造方法
JP2002231834A (ja) 2001-02-02 2002-08-16 Ricoh Co Ltd 半導体記憶装置
US6713127B2 (en) * 2001-12-28 2004-03-30 Applied Materials, Inc. Methods for silicon oxide and oxynitride deposition using single wafer low pressure CVD
JP2004207613A (ja) * 2002-12-26 2004-07-22 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7338894B2 (en) * 2005-01-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor device having nitridated oxide layer and method therefor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320784B1 (en) * 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof
US6297095B1 (en) * 2000-06-16 2001-10-02 Motorola, Inc. Memory device that includes passivated nanoclusters and method for manufacture
US6413819B1 (en) * 2000-06-16 2002-07-02 Motorola, Inc. Memory device and method for using prefabricated isolated storage elements
TW525263B (en) * 2000-09-28 2003-03-21 Chartered Semiconductor Mfg Formation of interfacial oxide layer at the Si3N4/Si interface by H2/O2 annealing
US6444545B1 (en) * 2000-12-19 2002-09-03 Motorola, Inc. Device structure for storing charge and method therefore
TW569377B (en) * 2002-03-20 2004-01-01 Taiwan Semiconductor Mfg Improvement method for thickness uniformity of super-thin nitridation gate dielectric

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