Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/051—Manufacture or treatment of vertical BJTs
  • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/051—Manufacture or treatment of vertical BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/40—Vertical BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs

Definitions

• This invention relates to self-aligned bipolar transistor (BT) for which the extrinsic base implant, extrinsic base suicide, and the emitter are self-aligned to one another.
• BT bipolar transistor
• the extrinsic base layer is implanted after the . patterning of the emitter polys ⁇ licon layer.
• These conventional patterning processes still rely on lithography to align the emitter polysilicon layer pattern to the emitter opening and the subsequent contact.
• the emitter polysilicon layer pattern is typically large enough to allow for tolerance in the lithographic processes for the emitter contact Therefore, for this type of integration scheme, the extrinsic base implant and silic ⁇ de are non-self aligned and are spaced far away from the emitter base junction, which results in high base resistance.
• the maximum oscillation frequency of such a non-self aligned transistor is limited by a base resistance (Rb) caused by such spacing.
• the extrinsic base is delimitated by a permanent spacer formed around a temporary emitter pedestal or by the temporary emitter pedestal itself.
• the temporary pedestal is later removed by lithography and etching to be replaced by a polysilicon emitter.
• the permanent spacer must then be of sufficient width for the second lithographic pattern edge with its associated critical dimensions (CD) and alignment tolerance to be formed on top of the spacer.
• the spacer width has to be sufficient to provide emitter-base isolation. This adds a structural constraint on the emitter dimension and minimum distance between the heavy doped extrinsic base area and the em ⁇ tter-base junction.
• the emitter polysilicon layer and the extrinsic base suicide are defined by lithography which adds to the lateral dimension and base resistance.
• the lateral profile of the extrinsic base doping is determined by a dual spacer formed around a temporary emitter pedestal.
• the emitter polysilicon layer and the extrinsic base suicide are defined by lithography which adds to the lateral dimension and the base resistance.
• Another drawback of this integration scheme is that the temporary pedestal lays on top of a thick stack of oxide nitride and polysilicon layers. In this case, the stack is needed to later form the em ⁇ tter-base isolation and, consequently, the dopant implantation through such a thick stack have to be of high energy to achieve low base resistance in the extrinsic base region. This results in less control over the doping profile and loss of intrinsic base region due to dopant diffusion.
• the invention presents a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and then forming an intrinsic base above the collector.
• the invention patterns an alignment layer over the substrate to have an alignment opening and then patterns an emitter pedestal (sacrificial placeholder) on the substrate in the alignment opening.
• the invention can perform a first implant to form first extrinsic base portions in regions of the substrate not protected by the emitter pedestal and the alignment layer.
• the invention removes the emitter pedestal and forms ah emitter in the alignment opening, which is self-aligned to the first extrinsic base implant.
• the invention After removing the alignment layer, the invention performs a second implant to form second extrinsic base portions in regions of the substrate not protected by the emitter. Then, sidewall spacer is formed on the emitter and a third implant is performed to form third extrinsic base portions in regions of the substrate not protected by the emitter and the sidewall spacer.
• the process of forming the emitter comprises depositing an emitter material conformally within the alignment opening.
• the thickness of the emitter material within the i alignment opening determines the width of the emitter.
• This confo ⁇ nali deposition process again leaves a recess in the emitter material where the alignment opening is positioned.
• a mask is formed within the recess the emitter material not protected by the mask is removed.
• the invention forms a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associated spacers, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal, was positioned.
• This embodiment provides a process of forming the extrinsic base that first performs a first impurity implant into the regions of the substrate not protected by the emitter pedestal, without any spacers present. This allows the sides of the extrinsic base regions to be directly vertically below and directly vertically aligned with sides of the lower portion of the emitter. After this first implant, the invention then forms first sidewall spacer on the emitter pedestal and performs a second impurity implant into regions of the substrate not protected by the emitter pedestal or the first sidewall spacer. The invention then removes the first sidewall spacer and repeats the implant process with a wider sidewall spacer. Therefore, the invention forms second sidewall spacer on the emitter pedestal. These second sidewall spacers extend further ,from the emitter pedestal than did the first sidewall spacer. Then, the invention performs a third impurity implant into regions of the substrate not protected by the emitter pedestal or the second sidewall spacer.
• This processing causes the extrinsic base to include multiple steps adjacent the sides of the emitter when viewed in cross-section. These steps comprise lengths of the extrinsic base that extend different depths into the substrate, wherein each successive length of the extrinsic base away from the emitter and the intrinsic base extend further into the substrate. Also, the thickness of the first sidewall spacer and the second sidewall spacer is independent of the thickness of the isolation regions that will be formed adjacent the lower portion of the emitter later.
• the invention Before the invention removes the emitter pedestal, it forms an alignment layer adjacent the emitter pedestal. When the emitter pedestal is removed, this leaves an emitter opening in the alignment layer. Then, the subsequent processing forms the emitter in the emitter openings of the alignment layer. Also, the invention forms an etch stop layer on the substrate and the thickness of the etch stop layer is controlled to reduce the energy required for the process of forming the extrinsic base regions.
• The-resulting structure has a collector and intrinsic base in the substrate, extrinsic base regions in the substrate adjacent the intrinsic base, and an emitter above the intrinsic base.
• the emitter has a T-shape where the upper portion is wider than the lower portion.
• the sides of the extrinsic base regions can be directly vertically below and directly vertically aligned with the sides of a lower portion of the emitter that ⁇ s directly above the intrinsic base, or can be positioned below the emitter.
• Figure 1 is a schematic diagram of a partially completed bipolar transistor according to the invention
• Figure 2 is a schematic diagram of a partially completed bipolar transistor according to the invention
• Figure 3 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 4 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 5 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 6 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 7 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 8 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 9 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 10 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 11 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 12 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 13 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 14 is a schematic diagram of a partially completed bipolar transistor according o the invention.
• Figure 15 is a schematic diagram of a partially completed bipolar transistor according o the invention.
• Figure 16 is a schematic diagram of a partially completed bipolar transistor according o the invention
• Figure 17 is a schematic diagram of a partially completed bipolar transistor according invention
• Figure 18 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 19 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 20 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 21 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 22 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 23 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 24 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 25 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 26 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 27 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 28 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 29 is a schematic diagram of a partially completed bipolar transistor according vention.
• Figure 30 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 31 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 32 is a schematic diagram of a partially completed bipolar transistor according invention
• Figure 33 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 34 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 35 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 36 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 37 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 38 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 39 is a schematic diagram of a partially completed bipolar transistor according nvention.
• Figure 40 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 41 is a schematic diagram of a partially completed bipolar transistor according nvention
• Figure 42 is a schematic diagram of a partially completed bipolar transistor according vention. i
• Figure 43 is a schematic diagram of a partially completed bipolar transistor according vention.
• Figure 44 is a schematic diagram of a partially completed bipolar transistor according vention.
• Figure 45 is a schematic diagram of a partially completed bipolar transistor according vention.
• Figure 46 is a schematic diagram of a partially completed bipolar transistor according vention
• Figure 47 is a schematic diagram of a partially completed bipolar transistor according to the invention
• Figure 48 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 49 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 50 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 51 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 52 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 53 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 54 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 55 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 56 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• Figure 57 is a schematic diagram of a partially completed bipolar transistor according to the invention.
• the various solutions toward improving bipolar transistors that are discussed in the background section leave room for improvement in bipolar transistors in a number areas.
• the extrinsic base implant to be self-aligned to the emitter opening; 2) the extrinsic base suicide to be self-aligned to the emitter opening; 3) the emitter polysilicon pattern to be self-aligned to the emitter opening; 4) the dopant profile to be formed in proximity of the emitter-base junction to optimize the base resistance ' and emitter- base leakage current; and 5) the extension base implant to be performed through only a thin oxide layer.
• the invention forms a transistor in an integrated circuit structure that begins by forming a collector 12 in a substrate 10 and an intrinsic base 14 above the collector 12. Regions 18 are shallow trench isolation (STI) of the substrate 10 that separate the transistor from other structures.
• regions 16 comprise, for example, doped polysilicon 17 and various deposited oxides 18, 19.
• STI shallow trench isolation
• the invention forms a thin (10-20 nm) etch stop layer 20 (such as a deposited oxide), a nitride layer 26, and an alignment layer 22 which can comprise any suitable material, such as undoped polysilicon, etc.
• the thickness of the etch stop layer 20 is controlled to reduce the energy required for the process of forming the extrinsic base regions 82, 172, 192 that are discussed below.
• Another deposited oxide layer 24 is formed over the alignment layer 22 in the structure in Figure 2.
• a photoresist 30 is patterned over the oxide layer 24 and, as shown in Figure 4, a material removal process (such as etching) is used to pattern the oxide layer 24, the alignment layer 22, and the nitride layer 26 stopping on the etch stop layer 20. This process forms an alignment opening 40.
• a sacrificial material 50 such as undoped polysilicon
• This sacrificial material 50 will eventually become the emitter pedestal that is used to align the implants and the emitter.
• This conformal deposition process forms a second opening 52 in the first opening 40.
• a mask material 60 (such as nitride) is deposited into the second opening 52.
• the mask material 60 is used to pattern the sacrificial material 50 into the emitter pedestal structure 50.
• any conventional material removal process such as etching, etc., can be used to pattern the sacrificial material 50.
• the first of a series of extrinsic base implant impurity doping processes is performed as indicated by arrows 80 in Figure 8. This process forms the first section of the extrinsic base 82.
• nitride 90 is deposited and is selectively removed down to a level equal to nitride layer 26 (as shown in Figure 10) using any selective material removal process that is designed to only attack the nitride 90 and leave the remaining structures substantially intact The remaining thickness of nitride 90 will serve as an isolation dielectric between the emitter and the base.
• the emitter pedestal 50 is removed and in Figure 12 both oxide 24 and oxide layer 20 are removed (again using selective removal processes).
• the emitter material 130 (such as doped polysilicon, or any other conductive material) is deposited in a conformal deposition process that produces a third opening 132 in a similar manner to second opening 52, as described above.
• a mask material 140 such as a deposited oxide or other masking material is formed within the third opening 132 (as shown in Figure 14) and then the exposed portions of the emitter material 130 and the undoped polysilicon 22 are removed using material 140 as a mask, which results in the structure shown Figure 15.
• this material removal process is continued (or a different material removal process can be commenced) to remove the exposed portions of the nitride layer 26, 90.
• any conventional material removal process such as etching, can be utilized in these steps.
• a second impurity 170 is implanted into the exposed portions of the substratel 0 to form the second portion of the extrinsic base 172.
• spacer 180 is formed along the sidewalls of the emitter 130.
• the spacer 180 can comprise, for example, a nitride (or other similar material) that is deposited and then removed in a directional removal process (such as anisotropic etching) that removes the nitride from horizontal surfaces at a faster rate than it removes the nitride material from vertical surfaces, thereby leaving the sidewall spacer 180 along the sidewalls of the emitter 130 as shown in Figure 18.
• a third impurity implant 190 is performed to form the third portion of the extrinsic base implant 192.
• the etch stop layer 20 and the mask 140 are removed, again using any selective material removal process, such as etching.
• the boundary of the conductor 17 is defined using conventional patterning processes (such as masking and etching).
• a suicide region 220 is formed over the conductors 17 and the extrinsic base region 192 using well-known suiciding processes that involve applying heat in the presence of a metal, as is well known to those ordinarily skilled in this art field.
• the suicide regions 220 are formed without having to use alignment masks, etc., and therefore, self-aligned suicide regions or salicides 220.
• the suicide 220 of the extrinsic base 192 and the top of the emitter 130 is self-aligned to the extent to base 82, 172, 192 and the emitter 130.
• the spacers 180 and the alignment features such as the nitride 90, the emitter pedestal 50, etc.
• the silicide 220, the extrinsic base 82, 172, 192, and the emitter 130 are all self-aligned with each other and do not require the more expensive and less accurate mask-type alignment processes.
• the resulting structure shown in Figure 22 has a collector 12 and intrinsic base 14 in the substrate 10, extrinsic base regions 82, 172, 192 in the substrate 10 adjacent the intrinsic base 14, an emitter 130 above the intrinsic base 14 and self-aligned silicide regions 220.
• the emitter 130 has a T-shape where the upper portion is wider than the lower portion.
• the extrinsic base 82, 172, 192 includes multiple steps, when viewed in cross-section. These steps comprise lengths of the extrinsic base 82, 172, 192 that extend different depths into the substrate 10, wherein each successive length of the extrinsic base 82, 172, 192 away from intrinsic base . 14 extends further into the substrate 10 from the top of the substrate 10.
• FIG. 23-41 produces a similar structure as the embodiment shown in Figures 1-22, using different processing techniques.
• the same or similar items that are discussed above with respect to the embodiment shown in Figures 1-22 are identified with the same identification character or number and a redundant discussion of such elements is avoided for brevity.
• the structure shown Figure 23 is similar to the structure shown in Figure 2 except that .
• layers 22, 24, and 26 are replaced with layer 230 which can comprise, for example, nitride.
• a mask 30 is formed in a similar manner as shown below in Figure 3, and in Figure 25, the same opening 40 discussed below in Figure 4 is formed.
• the sacrificial material 50 is formed and the same is patterned in Figures 27-28 as discussed below with respect to Figures 6 and 7. Note that in Figure 28, the mask material 60 is removed while in Figure 7 the mask material 60 is allowed to remain.
• the same impurity implant 80 is made in Figure 29 as was made in Figure 8. Then, in Figure 30, the sacrificial material 50 is removed.
• FIG. 31 conformal nitride (310) and undoped polysilicon (312) layers are deposited over the structure.
• sidewall spacer 320 (such as deposited oxide) is formed in a similar sidewall spacer formation process that formed the previous sidewall spacer 180.
• a selective removal process removes the undoped polysilicon layer 312. This removal process does not affect the regions of the undoped polysilicon 312 that are protected by the spacers 320.
• the spacers 320 are removed and in Figure 35 the exposed portion of the nitride layer 310 is removed. Following this, the remaining undoped polysilicon 312 is removed, as shown in Figure 36, and the central exposed portion of the etch stop layer 20 is removed, again using a selective material removal processes, as shown Figure 37
• the emitter material 130 is deposited as was done in Figure 13, above.
• the mask 140 is formed in the recess 132 of the emitter material.
• the exposed portions of the emitter material 130 are removed, again in a selective material removal process, as shown in Figure 40.
• the nitride regions 310 and 230 are removed (again in a selective material removal process) resulting in the structure shown in Figure 41.
• the structure shown in Figure 41 is substantially similar to the structure shown in Figure 16 and processing steps similar to the those shown in Figures 17-22 are performed on the structure to complete this embodiment of the invention.
• the second embodiment is shown in Figures 42-57. More specifically, as shown in Figure 42, this process begins with a structure that is somewhat similar to that shown in Figure 2 and includes the etch stop layer 20 and the sacrificial material 50 above the etch stop layer 20.
• the sacrificial layer 50 is patterned using standard photolithographic techniques to form an emitter pedestal 50 for the lower portion of the emitter on the substrate 10 above the 41049
• the invention forms an extrinsic base 82, 172, 192 in regions of the substrate 10 not protected by the emitter pedestal 50, as shown in Figures 44-46.
• the invention provides a process of forming the extrinsic base 82, 172, 192 that first performs a first impurity implant 80 into the regions of the substrate 10 not protected by the emitter pedestal 50, without any spacer present, to form the initial portion of the extrinsic base 82, as shown ⁇ n Figure 44. This allows the sides of the initial portion of the extrinsic base 82 to be directly vertically below and directly vertically aligned with sides of the lower portion of the emitter 130 ( Figure 55) that will eventually replace the emitter pedestal 50.
• the invention then forms first sidewall spacer 54 on the emitter pedestal 50 and performs a second impurity implant 170 into regions of the substrate 10 not protected by the emitter pedestal 50 or the first sidewall spacer 450, as shown Figure 45.
• the invention then removes the first sidewall spacer 54 and repeats the implant process with a wider sidewall spacer 460, as shown Figure 46. More specifically, the invention forms second sidewall spacer 460 on the emitter pedestal 50.
• the second sidewall spacer 460 extends further from the emitter pedestal 50 than did the first sidewall spacer 450.
• the invention performs a third impurity implant 190 into regions of the substrate 10 not protected by the emitter pedestal 50 or the second sidewall spacer 460. After this, and shown Figure 47, the second sidewall spacer 460 is removed.
• this processing causes the extrinsic base 82, 172, 192 to include multiple steps 82, 172, 192 adjacent the intrinsic base 14, when viewed in cross- section. These steps are also referred to herein as a retrograde doping profile. These steps comprise lengths of the extrinsic base 82, 172, 192 that extend different depths into the substrate 10, wherein each successive length of the extrinsic base 82, 172, 192 away from the intrinsic base 14 extend further (deeper) into the substrate 10.
• the intrinsic base 14 has a shape that mirrors the multiple step shape of the extrinsic base 82, 172, 192.
• the thicknesses of the first sidewall spacer 450 and the second sidewall spacer 460 are independent of the thickness of the isolation regions 20, 480 (shown in Figure 57) that will be formed adjacent the lower portion of the emitter 130 later. Therefore, unlike conventional methodologies, with the invention the dimensions of the steps in the extrinsic base 82, 172, 192 is completely independent of the spacer or isolation regions that will be formed next to the lower portion of the emitter 130. Thus, the invention can position the edges of the extrinsic base wherever -necessary to optimize the performance of the transistor, without regard to the dimensions of the isolation regions 20, 480 that will be positioned adjacent to the lower portion of the T- shaped emitter 130.
• the invention prepares a layer 480 for the emitter 130 that will be formed in Figure 55. More specifically, in Figure 48 conformai nitride 480 and oxide 482 layers are formed over the structure. In Figure 49, the oxide layer 482 is patterned to expose a portion of the nitride layer 480. Next, in Figure 50, additional nitride is added to the previous nitride layer 480 to form a thicker nitride layer 500. In Figure 51, the nitride 480, 500 is etched down to a level below the top of the emitter pedestal 50. Then, in Figure 52, the oxide layer 482 is removed. Finally, in Figure 53, the emitter pedestal 50 is removed leaving opening 530.
• Figure 54 illustrates an optional embodiment that forms sidewall spacer 540 on the sidewalk of layer 480. If tins sidewall spacer 540 is utilized, when the emitter 130 is formed, it will be spaced from the side of the extrinsic base 82, 172, 192. In this description, the "side" of the extrinsic base is the vertical portion of region 482 that it is adjacent to the intrinsic base 14. Therefore, these optional sidewall spacer 540 can be used, when necessary, to provide additional control regarding the horizontal spacing between the side of the extrinsic base 82, 172, 192 and the sides of the lower portion of the T-shaped emitter structure 130.
• the various material deposition and removal processes that are discussed above are well known to those ordinarily skilled in the art and will vary depending upon which materials are used in the specific design, and a detailed discussion of the same is avoided herein for brevity.
• the invention removes the emitter pedestal 50, it forms a layer 480 adjacent the emitter pedestal 50.
• the position of the emitter opening 530 in the layer 480 is completely self aligned by previously formed structures and does not require any lithographic-type structures, which avoids many problems of conventional methodologies.
• the invention forms the T-shaped emitter 130 where the emitter pedestal 50 was positioned.
• the emitter 130 can be formed of many useful conductors, such as polysilicon.
• the exposed portion of layer 480 is removed, and in Figure 57, the exposed portion of the etch stop layer 20 is removed. These processing steps form isolation regions 20, 480 that isolates the emitter 130 from the extrinsic base 82, 172, 192.
• the sides of the extrinsic base region 82 are directly vertically below and directly horizontally aligned with the sides of a lower portion of the emitter ⁇ 30 that is directly above the intrinsic base 14.
• the top of the intrinsic base 14 has the same width as the lower section of the emitter 130 and the extrinsic base regions 14 do not extend below the lower portion of the emitter 130.
• the lateral dimension of the transistor is reduced by maximizing the use of self-alignment
• the extrinsic base 82, 172, 192 is partially implanted prior to the polysilicon emitter 130 formation to form a doping profile in proximity of the emitter-base junction.
• the emitter polysilicon 130 pattern is self-aligned to the emitter opening 130 and the extrinsic base implant 82, 172, 192.
• the temporary emitter pedestal 50 lays on the thin etch stop layer 20 which allows for low energy ion implantation, which provides better control of the extrinsic base doping profile depth and lateral diffusion.
• the use of the disposable pedestal 50 to form the extrinsic base 82, 172, 192 doping allows for an optimum profile that is independent of other structures of the transistor such as emitter-base isolation regions 20, 100.
• This invention is applicable to the manufacture of very-large-scale integrated circuits in which high switching speeds are desired, and particularly in the manufacture of high- performance computing devices.

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