WO2006049195A1 - キャパシタ層形成材及びそのキャパシタ層形成材を用いて得られる内蔵キャパシタ層を備えたプリント配線板 - Google Patents
キャパシタ層形成材及びそのキャパシタ層形成材を用いて得られる内蔵キャパシタ層を備えたプリント配線板 Download PDFInfo
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- WO2006049195A1 WO2006049195A1 PCT/JP2005/020183 JP2005020183W WO2006049195A1 WO 2006049195 A1 WO2006049195 A1 WO 2006049195A1 JP 2005020183 W JP2005020183 W JP 2005020183W WO 2006049195 A1 WO2006049195 A1 WO 2006049195A1
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- forming material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
Definitions
- the present invention relates to a capacitor layer forming material and a printed wiring board including a built-in capacitor layer obtained using the capacitor layer forming material.
- a multilayer printed wiring board incorporating a capacitor circuit uses one or more of the insulating layers located in the inner layer as a dielectric layer. Then, as disclosed in Patent Document 1, an upper electrode and a lower electrode as capacitors are arranged opposite to inner layer circuits located on both surfaces of the dielectric layer to form a capacitor circuit, which has been used as a built-in capacitor. In order to form this capacitor circuit, it is common to use a capacitor layer forming material having a layer structure of a first conductive layer Z dielectric layer Z second conductive layer similar to a double-sided copper-clad laminate.
- the built-in capacitor circuit is manufactured in various ways, such as by etching the conductive layer of the capacitor layer forming material in advance to form a capacitor circuit and bonding it to the inner layer substrate, or by etching after bonding to the inner layer substrate. This method has been adopted.
- Capacitors have been able to reduce the power consumption of electronic and electrical devices by storing surplus electricity, etc., so that they have a basic quality required to have as large an electric capacity as possible.
- Patent Document 2 the formation of the dielectric layer is disclosed in Patent Document 2 on the surface of the metal foil.
- various production methods such as a sol-gel method using a chemical gas phase reaction method have been adopted on the surface of an electrode material having a composite layer of copper and nickel-phosphorus alloy.
- the sol-gel method is particularly excellent from the viewpoint of forming a thin dielectric layer.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2003-105205
- Patent Document 2 JP-A-9-040933
- Patent Document 3 Japanese Patent Laid-Open No. 2004-250687
- Patent Document 4 US Pat. No. 6,541,137
- Patent Document 5 Japanese Unexamined Patent Publication No. 2003-171480
- Patent Document 6 Japanese Patent Laid-Open No. 2003-124580
- the capacitor layer forming material has a layer structure of the first conductive layer Z dielectric layer Z second conductive layer
- thinning the dielectric layer means that the capacitor layer forming material itself The thickness is reduced, the strength cannot be maintained, and there is a disadvantage that the safety during handling is high because the probability of damage such as breakage during handling is high.
- a fluorine resin substrate, a liquid crystal polymer or the like is used as a substrate material, and a multilayer substrate using these substrates Attempts have been made to manufacture.
- the press working temperature is extremely high, between 300 ° C and 400 ° C, and the substrate material is hard. Therefore, considering the formation of a built-in capacitor layer inside a multilayer printed wiring board using these fluororesin substrates and liquid crystal polymers as substrate materials, high-temperature pressing at 300 ° C to 400 ° C is required. As a result, it is desirable that the material has sufficient strength to withstand the expansion and contraction of the surrounding material that does not fluctuate in material even when pressed by a hard substrate material.
- the adhesion to the dielectric layer as the lower electrode of the capacitor circuit is stable, and a fine capacitor circuit shape can be formed.
- a fluorine resin substrate, a liquid crystal polymer, etc. are used as the substrate material.
- a capacitor layer forming material that does not deteriorate in strength even after a high-temperature caking process of 300 ° C to 400 ° C on the printed wiring board.
- the inventors of the present invention can obtain good adhesion between the dielectric layer and the lower electrode by using the following capacitor layer forming material, and the dielectric layer becomes thin.
- the strength of the capacitor layer forming material was maintained and the handling was improved.
- Shika is also a capacitor layer forming material that does not deteriorate in strength even when it is subjected to a 300 ° C to 400 ° C high-temperature caulking process on a printed wiring board made of a fluororesin substrate or liquid crystal polymer.
- the capacitor layer forming material described later the electric capacity of the capacitor circuit is also improved.
- FIG. 1 shows a schematic cross section of the capacitor layer forming material.
- the capacitor layer forming material 1 includes a dielectric layer 3 between a first conductive layer 2 used for forming an upper electrode and a second conductive layer 4 used for forming a lower electrode.
- the capacitor layer forming material according to the present invention is characterized in that a single layer of nickel or a nickel alloy is used for the second conductive layer 4 used for forming the lower electrode.
- the thickness of the nickel layer or the nickel alloy layer as the second conductive layer is 10 ⁇ m to 100 ⁇ m.
- a nickel foil or a nickel alloy foil manufactured by a rolling method or an electrolytic method for the second conductive layer it is preferable to use a nickel foil or a nickel alloy foil manufactured by a rolling method or an electrolytic method for the second conductive layer.
- the dielectric layer is preferably formed by a sol-gel method on the nickel layer or nickel alloy layer constituting the second conductive layer.
- a nickel alloy layer is used for the second conductive layer of the capacitor layer forming material according to the present invention, it is preferable to use a nickel-phosphorus alloy or a nickel-cobalt alloy.
- a printed wiring board having an internal capacitor circuit can be manufactured by using various methods and using various capacitor layer forming materials.
- the capacitor circuit built in the printed wiring board obtained in this way can be applied to the second conductive layer constituting the lower electrode even if it is repeatedly subjected to hot pressing in the range of 300 ° C to 400 ° C. Since the composite foil with the high temperature and heat resistance characteristics is provided, no abnormality occurs in the shape of the lower electrode, and it has resistance to the expansion and contraction behavior of the surrounding materials due to heat. Therefore, built-in capacitor circuit formation of multilayer printed wiring board using fluorine resin substrate and liquid crystal polymer substrate It is suitable for.
- the printed wiring board referred to in the present invention is described as including a conceptual product including a small package substrate that is directly mounted with an IC chip or the like from a product such as a mother board of a computer. .
- the capacitor layer forming material according to the present invention includes a nickel layer or a nickel alloy layer excellent in high temperature and heat resistance as the second conductive layer constituting the lower electrode. Even if the hot press force in the range of 300 ° C to 400 ° C, which is used for the production of multilayer printed wiring boards using a substrate, is repeatedly applied, the capacitor circuit shape is formed and the bottom electrode shape remains abnormal after that. It does not occur and has resistance to the expansion and contraction behavior of surrounding materials due to heat. In addition, it is possible to maintain good adhesion between the second conductive layer and the dielectric layer. As a result, the printed wiring board including the built-in capacitor circuit obtained by using the capacitor layer forming material according to the present invention is of high quality.
- the nickel layer or the nickel alloy layer is adopted as the second conductive layer for the following four reasons.
- (1) It can be obtained as a metal foil, and a dielectric layer can be formed on the surface by the sol-gel method in the state of the foil.
- (2) It has excellent acid resistance and anti-softening properties against the severe thermal history applied when forming a dielectric layer by the sol-gel method.
- (3) By changing the nickel alloy composition, the adhesion to the dielectric layer can be controlled at a certain level.
- (4) By using a single component metal layer it is possible to form a fine capacitor circuit when forming the lower electrode shape by etching.
- the nickel layer or nickel alloy layer referred to here is mainly intended to use a metal foil. Accordingly, the nickel layer is a layer formed of a pure nickel foil having a so-called purity of 99.9% (other unavoidable impurities) or more. And nickel alloy layer is nickel-phosphorus alloy It is a layer formed using.
- the phosphorus content of the nickel-phosphorus alloy mentioned here is preferably 0.1 wt% to l wt%.
- the phosphorus component of the nickel-phosphorus alloy layer diffuses into the dielectric layer and may adhere to the dielectric layer if it is subjected to high-temperature loads in the manufacturing process of the capacitor layer forming material and the normal printed wiring board manufacturing process.
- the phosphorus content is preferably in the range of 0.1 wt% to l wt%.
- a stable quality capacitor circuit can be obtained even if there is a certain variation if the phosphorus content is in the range of 0.2 wt% to 3 wt%. Can be formed. If the optimum range is pointed out, the phosphorus content of 0.25 wt% to lwt% ensures the best adhesion with the dielectric layer, and at the same time the good dielectric constant.
- the nickel content in the present invention is a value converted as [P component weight] Z [Ni component weight] X 100 (wt%).
- Nickel foils and nickel alloy foils as listed here are excellent in heat resistance and are 400 ° C.
- tensile strength (strength) when viewed as a composite foil that is difficult to cause soft wrinkles even when heated for about 10 hours, and reduces the tensile strength after heating to 50 kgfZmm 2 This can be maintained.
- a temperature load exceeding 400 ° C. is applied using a composite material in which a -kel layer and a copper layer are laminated as a material constituting the second conductive layer, the nickel layer and the copper layer Interdiffusion with the layer occurs, the anti-soft property of nickel itself cannot be maintained, and the toughness as a capacitor forming material is lowered, resulting in a lack of the ringing property.
- the crystal structure of the nickel foil and the nickel alloy foil referred to in the present invention is that in which the crystal grains have improved strength as much as possible. Further More specifically, it is preferable that the average crystal grain size is reduced to a level of 0.5 m or less, high mechanical strength and physical properties are provided.
- the thickness of the nickel layer or nickel alloy layer is preferably 10 ⁇ m to 100 ⁇ m. If the thickness is less than 10 m, handling properties when viewed as a metal foil are remarkably lacking, and it is extremely difficult to form a dielectric layer on the surface.
- the nickel layer or nickel alloy layer used to form the second conductive layer may be used for a resistance circuit or the like. When the thickness is less than 10 m, it becomes difficult to use.
- the nickel foil or nickel alloy foil used in the configuration of the second conductive layer described above one manufactured by an electrolytic method or a rolling method can be used.
- the rolling method is a method in which the components of the ingot are adjusted by a metallurgical process and processed into a foil shape with a rolling roll while performing an appropriate annealing operation. is there.
- the deposited metal structure varies depending on the electrolytic solution, electrolysis conditions, etc., and as a result, the physical strength is also affected.
- a solution known as a nickel plating solution can be widely used.
- Nickel sulfate is used and the nickel concentration is 5 to 30 gZl, liquid temperature is 20 to 50 ° C, pH is 2 to 4, current density is 0.3 to: LOAZdm 2 conditions,
- nickel concentration is used 5 to 30 g / l, Pi P Gin acid Kajikumu 50 to 500 g / l, solution temperature 20 ⁇ 50 o C, pH8 ⁇ ll, current density 0.
- a nickel-phosphorus alloy foil is produced by electrolysis
- a phosphoric acid based solution is used as the electrolytic solution.
- a dielectric layer is formed on the surface of the nickel foil or nickel alloy foil.
- the dielectric layer can also be formed by a so-called sol-gel method, a coating method that forms a dielectric layer by coating using a dielectric filler-containing resin solution containing a dielectric filler and a binder resin, and a dielectric filler.
- sol-gel method a coating method that forms a dielectric layer by coating using a dielectric filler-containing resin solution containing a dielectric filler and a binder resin, and a dielectric filler.
- Various known methods such as a method of laminating the contained film can be employed.
- the significance of using a nickel foil or a nickel alloy foil as the second conductive layer as in the present invention is unnecessary when forming a dielectric layer by the sol-gel method in which many heating processes exist in the processing process. Expecting excellent heat resistance and anti-softening properties such as no oxidation! /.
- the first conductive layer for forming the upper electrode is provided on the dielectric layer.
- various known methods such as a method of bonding using a metal foil, a method of forming a conductive layer by a plating method, a method of using a method such as sputtering deposition, etc. are adopted. Is possible.
- the capacitor layer forming material according to the present invention By using the capacitor layer forming material according to the present invention described above, it becomes possible to form a lower electrode excellent in adhesion to the dielectric layer, and the lower electrode is a material excellent in heat resistance. For this reason, even if hot pressing in the range of 300 ° C to 400 ° C is performed multiple times, oxidation deterioration does not occur, and physical property change hardly occurs.
- any method without particular limitation can be adopted. However, as shown in the following examples, it is preferable to employ a method for manufacturing a printed wiring board in which an extra dielectric layer other than the portion where the capacitor circuit is formed can be removed as much as possible.
- a first composite foil having a nickel layer was manufactured, and the first composite foil was used.
- a capacitor layer forming material was manufactured, and a printed wiring board equipped with a built-in capacitor circuit was manufactured.
- a nickel foil having a thickness of 20 m was manufactured by depositing and peeling nickel on the force sword electrode under the following electrolytic solution and electrolysis conditions.
- the thickness referred to in the present specification is a thickness based on the basis weight when an attempt is made to form a dissimilar metal layer having a predetermined thickness on the flat surface by the plating method.
- the foil thickness is shown as gauge thickness. The same applies to the following examples and comparative examples.
- the obtained nickel foil was evaluated for the tensile strength and elongation after heating in a normal state and at 400 ° C for 10 hours in a vacuum. The results are shown in Table 1. The tensile strength and elongation were measured in accordance with the measurement of the printed circuit board copper foil defined in IPC-TM-650 defined in IPC-MF-150F. The same applies hereinafter.
- the above-described nickel foil was used for forming the second conductive layer used for forming the lower electrode of the capacitor layer forming material, and a dielectric layer was formed on the surface of the nickel foil using a sol-gel method.
- the nickel foil before forming the dielectric layer by the sol-gel method was heated at 250 ° C. for 15 minutes and irradiated with ultraviolet rays for 1 minute as a pretreatment. The same applies to the following examples and comparative examples.
- methanol heated to near the boiling point was carotenized with ethanolamine as a stabilizer so as to have a concentration of 50 mol% to 60 mol% with respect to the total amount of metals.
- this Zonolegenole solution was applied to the surface of the nickel foil using a spin coater, dried in an air atmosphere at 250 ° CX for 5 minutes, and thermally decomposed in an air atmosphere at 500 ° CXI for 5 minutes. Furthermore, this coating process was repeated 6 times to adjust the film thickness. Finally, a baking process was performed in a nitrogen substitution atmosphere at 600 ° C. for 30 minutes to form a dielectric layer.
- a copper layer having a thickness of 3 m is formed as a first conductive layer by sputtering vapor deposition, and the first conductive layer and the second conductive layer are formed on both sides of the dielectric layer. And a capacitor layer forming material.
- a predetermined voltage was applied and interlayer withstand voltage measurement was performed, but the short-circuit phenomenon between the first conductive layer and the second conductive layer was strong.
- the peel strength at the interface between the second conductive layer and the dielectric layer was measured.
- the peel strength was 50 gfZcm, which was higher than the following comparative examples.
- the electrode area of the upper electrode is lmm 2
- the average capacitance density is 284 nFZcm 2, which is a very good value, with a dielectric loss of 2%, which provides a good capacitor circuit with good electric capacity and low dielectric loss. I can see that.
- the etching resist remaining on the circuit surface after the formation of the upper electrode 5
- the exposed dielectric layer in the region other than the circuit portion was removed.
- the dielectric layer is removed by wet blasting and is a fine powder with a center particle size of 14 m.
- a slurry-like polishing liquid (polishing agent concentration 14 vol%) in which abrasive is dispersed in water is collided with the surface to be polished as a high-speed water stream from a slit nozzle with a length of 90 mm and a width of 2 mm at a water pressure of 0.2 MPa.
- the dielectric layer was removed by polishing.
- the etching resist was peeled off, washed with water, and dried to obtain the state shown in FIG. 2 (c).
- a copper foil 6 is provided with a semi-cured resin layer 7 having a thickness of 80 ⁇ m on one side.
- Fig. 3 (e) where copper foil 8 with a grease layer is overlaid and hot-pressed under heating conditions of 180 ° CX for 60 minutes, and the outer layer is laminated with copper foil layer 6 and insulating layer 7 ' It was. Then, the outer second conductive layer 4 shown in FIG.
- the etching factor of the lower electrode is 6.2, and it can be understood that the etching is good.
- the etching factor in this specification means that the height of the cross section of the circuit is h, the length of the upper base when the circuit cross section is considered to be substantially trapezoidal, and L is the length of the lower base. Calculated as 2h / (LL)
- a copper plating layer 24 is provided based on a conventional method, and etched to obtain the state shown in FIG. 4 (g). .
- the copper foil 8 with a resin layer is superposed and hot pressed under a heating condition of 180 ° C x 60 minutes, and the outer layer is insulated from the copper foil layer 6.
- Layer 7 ' was attached to the state shown in Fig. 5 (i).
- the copper plating layer 24 is provided based on a conventional method, and the etching is performed as shown in FIG. (j) state.
- the conventional method was also employed for the etching method and via hole formation at this time.
- the printed wiring board 10 including the built-in capacitor circuit could be manufactured.
- This example is different from the electrolytic nickel foil of Example 1 only in that a nickel foil having a thickness of 50 ⁇ m manufactured by a rolling method is used. Other capacitor layer forming materials and The same applies to the production of a printed wiring board having a built-in capacitor circuit. Therefore, a duplicate description is omitted, and only the rolled nickel foil is described.
- This rolled nickel foil was made into a nickel foil by a rolling process using a pure nickel ingot having a purity of 99.9 wt% or more. When using this rolled nickel foil, in order to remove the oil adhering during rolling, it is necessary to thoroughly clean it with alkali degreasing with a sodium hydroxide solution, pickling with dilute sulfuric acid solution, and washing with water.
- Example 2 Used after. In the same manner as in Example 1, a capacitor layer forming material was manufactured, and a printed wiring board provided with a built-in capacitor circuit was manufactured. The rolled nickel foil used here was evaluated for the tensile strength and elongation after heating in a normal state and at 400 ° C. for 10 hours in a vacuum. The results are shown in Table 1.
- the capacitor layer forming material manufactured as described above was subjected to interlayer withstand voltage measurement by applying a predetermined voltage, but the short-circuit phenomenon between the first conductive layer and the second conductive layer was I could't see it.
- the peel strength at the interface between the second conductive layer and the dielectric layer was measured. As a result, the peel strength was 50 gfZcm.
- the electrode area of the upper electrode is lmm 2
- the average capacitance density is 217 nFZcm 2, which is a very good value
- the dielectric loss is 2.7%, which is a good capacitor circuit with good capacitance and low dielectric loss.
- the etching factor of the lower electrode of the built-in capacitor circuit at this time is 6.1, and it can be understood that the etching is good.
- This example is different from the electrolytic nickel foil of Example 1 only in that a nickel phosphorus alloy foil having a thickness of 20 ⁇ m manufactured by an electrolytic method is used.
- Other capacitor layer forming materials The same applies to the manufacture of printed wiring boards with built-in capacitor circuits. Therefore, the duplicated explanation is omitted and only the production of the nickel-phosphorus alloy foil is explained.
- a nickel-phosphorus alloy foil having a thickness of 20 m and a phosphorous content of 0.3 wt% was deposited by depositing and stripping a nickel-phosphorus alloy on a force sword electrode under the following electrolyte solution and electrolysis conditions. Manufactured.
- the capacitor layer forming material manufactured as described above was subjected to interlayer withstand voltage measurement by applying a predetermined voltage.
- the short-circuit phenomenon between the first conductive layer and the second conductive layer was I could't see it.
- the peel strength at the interface between the second conductive layer and the dielectric layer was measured. As a result, the peel strength was 14 gfZcm.
- the electrode area of the upper electrode is lmm 2
- the average capacitance density is 366 nFZcm 2, which shows a very good value, with a dielectric loss of 1.1%, a good capacitor circuit with good electrical capacity and low dielectric loss. It can be seen that Furthermore, the etching factor of the lower electrode of the built-in capacitor circuit at this time was 6.3, indicating that good etching was possible.
- a nickel phosphorus alloy foil (phosphorus content 0.3 wt%) having a thickness of 50 m manufactured by a rolling method was used. Yes The same applies to the production of printed wiring boards including other capacitor layer forming materials and built-in capacitor circuits. Therefore, the duplicated explanation is omitted and only the rolled nickel foil is explained.
- This rolled nickel foil was made into a nickel-phosphorus alloy foil by a rolling process using a nickel-phosphorus alloy ingot having a phosphorus content of 8 wt%.
- the capacitor layer forming material manufactured as described above was subjected to interlayer withstand voltage measurement by applying a predetermined voltage, but the short-circuit phenomenon between the first conductive layer and the second conductive layer was I could't see it.
- the peel strength at the interface between the second conductive layer and the dielectric layer was measured. As a result, the peel strength was 15 gfZcm.
- the electrode area of the upper electrode is lmm 2
- the average capacitance density is 333nFZcm 2 and shows a very good value, with a dielectric loss of 1.1%, a good capacitor circuit with good electric capacity and low dielectric loss. It can be seen that Furthermore, the etching factor of the lower electrode of the built-in capacitor circuit at this time is 6.0, and it can be understood that the etching is good.
- the comparative example described below is different only in that the second conductive layer of Example 1 is composed of a normal 35 m thick electrolytic copper foil. Therefore, the explanation of the duplicated explanation will be omitted as much as possible. Therefore, an electrolytic copper foil having a thickness of 35 m was used for forming the second conductive layer, and a capacitor layer forming material was manufactured by forming a dielectric layer on one side thereof by the sol-gel method in the same manner as in Example 1. At this stage, the interlayer withstand voltage was measured, but a short phenomenon occurred between the first conductive layer and the second conductive layer, and it was difficult to commercialize the capacitor layer forming material. Therefore, we also manufacture printed wiring boards with the following built-in capacitor circuits. There wasn't. The electrolytic copper foil used here was evaluated for tensile strength and elongation after heating at 400 ° C for 10 hours in a normal state and in vacuum. The results are shown in Table 1.
- the comparative example described here differs only in that the second conductive layer of Example 1 is a composite foil in which a pure nickel layer of about 3 m thickness is formed on an electrolytic copper foil of 35 m thickness. It is. Therefore, the explanation of the duplicate explanation will be omitted as much as possible.
- the composite foil used for forming the second conductive layer was manufactured by providing an electrolytic nickel method with a pure nickel layer having a thickness of about 3 / zm on both surfaces of an electrolytic copper foil having a thickness of 35m.
- the same electrolytic solution and electrolytic conditions as in Example 1 were used for the formation of the pure nickel layer.
- the composite foil used here was evaluated in the normal state and the tensile strength and elongation after heating in a vacuum at 400 ° C. for 10 hours. The results are shown in Table 1.
- a layer forming material was used. Interlayer withstand voltage measurement was performed at this stage, but a short phenomenon occurred between the first conductive layer and the second conductive layer, and the product yield was 60%.
- the bow I peel strength at the interface between the second conductive layer and the dielectric layer was measured. As a result, the peel strength is lOgfZcm, and a certain degree of peel strength can be obtained, but it is a lower value than in the above examples.
- Example 3 In the comparative example described here, the second conductive layer of Example 1 was formed on a 35 m thick electrolytic copper foil with a nickel-phosphorus alloy layer (phosphorus content 8 wt%) about 3 ⁇ m thick. The only difference is the use of the composite foil. Therefore, the explanation of the duplicated explanation will be omitted as much as possible.
- the composite foil used for forming the second conductive layer was manufactured by providing an electrolytic copper method with a nickel-phosphorus alloy layer having a thickness of about 3 m on both surfaces of an electrolytic copper foil having a thickness of 35 / zm.
- the nickel-phosphorus alloy layer was formed using the following electrolytic solution and electrolytic conditions.
- the rolled nickel foil used here was evaluated for the tensile strength and elongation after heating in a normal state and at 400 ° C. for 10 hours in a vacuum. The results are shown in Table 1.
- Example 3 Note that, using the capacitor layer forming material manufactured in Comparative Example 3, the same process as in Example 1 was performed. A printed wiring board with a storage capacitor was manufactured. As a result, when the electrode area of the upper electrode was lmm 2 , the average capacity density was 370 nFZcm 2 and the dielectric loss was 2.0%. Compared with the example, the capacitance and dielectric loss are very good. Furthermore, the etching condition of the lower electrode of the built-in capacitor circuit at this time is that the etching of the copper layer under the pure nickel layer is fast when the circuit cross section is observed. As the side etching progresses, the pure nickel layer remains widely and overhangs, and it is difficult to accurately measure the etching factor. It can not be said.
- Comparative Example 1 in which ordinary electrolytic copper foil is used for the second conductive layer, physical damage such as tensile strength is very prominent at the stage of forming the dielectric layer by the sol-gel method. In addition, it is difficult to produce a capacitor layer forming material. From an industrial viewpoint, its use is considered almost impossible.
- the comparative examples include the performance of maintaining the physical strength of the second conductive layer, the adhesion between the second conductive layer and the dielectric layer, the average capacity density and dielectric as the capacitor layer forming material. It is clear that the loss, the etching factor, and the total balance of each quality are lacking.
- the second conductive layer of the capacitor layer forming material is made of nickel foil or nickel-phosphorus alloy foil 1
- excellent total balance is achieved. It is possible to obtain a capacitor layer forming material. This is because the nickel foil or nickel-phosphorus alloy foil constituting the second conductive layer has a very good tensile strength and elongation after heating at 400 ° C for 10 hours, and is processed into a capacitor layer forming material.
- the average capacitance density and dielectric loss of a capacitor that does not cause a short-circuit phenomenon between the first conductive layer and the second conductive layer are values that are practically satisfactory. However, even if it is checked up to a printed wiring board having a built-in capacitor, the etching factor of the lower electrode is extremely good, and a high-quality printed wiring board can be obtained without any problems.
- the capacitor layer forming material according to the present invention uses a nickel foil or nickel-phosphorus alloy foil excellent in high-temperature heat resistance for the second conductive layer constituting the lower electrode. It is particularly suitable for manufacturing a multilayer printed wiring board using a polymer substrate. Even after repeated hot pressing in the range of 300 ° C to 400 ° C used for the production of printed wiring boards using these substrates, the capacitor circuit shape is formed and the lower electrode shape is maintained. Abnormality does not occur, and it has resistance to the expansion and contraction behavior of the surrounding material due to heat. In addition, because it has such excellent heat resistance characteristics, the nickel foil or There is no problem even if the sol-gel method is used on the surface of the Kerlin alloy foil to receive a severe thermal history during the formation of the dielectric layer.
- FIG. 1 is a schematic cross-sectional view of a capacitor layer forming material according to the present invention.
- FIG. 2 is a schematic diagram showing a manufacturing flow of a printed wiring board including a built-in capacitor circuit using the capacitor layer forming material according to the present invention.
- FIG. 3 is a schematic diagram showing a manufacturing flow of a printed wiring board including a built-in capacitor circuit using the capacitor layer forming material according to the present invention.
- FIG. 4 is a schematic diagram showing a manufacturing flow of a printed wiring board including a built-in capacitor circuit using the capacitor layer forming material according to the present invention.
- FIG. 5 is a schematic diagram showing a manufacturing flow of a printed wiring board including a built-in capacitor circuit using the capacitor layer forming material according to the present invention.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05799990A EP1827064A4 (en) | 2004-11-04 | 2005-11-02 | CAPACITOR LAYER FORMING MATERIAL, AND CIRCUIT BOARD HAVING INTERNAL CAPACITOR LAYER OBTAINED USING SUCH CAPACITOR LAYER FORMING MATERIAL |
US11/744,250 US20080130196A1 (en) | 2004-11-04 | 2007-05-04 | Capacitor Layer Forming Material and Printed Wiring Board Having Embedded Capacitor Layer Obtained by using the Capacitor Layer Forming Material |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-321298 | 2004-11-04 | ||
JP2004321298A JP3816508B2 (ja) | 2004-11-04 | 2004-11-04 | キャパシタ層形成材及びそのキャパシタ層形成材を用いて得られる内蔵キャパシタ層を備えたプリント配線板 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/744,250 Continuation-In-Part US20080130196A1 (en) | 2004-11-04 | 2007-05-04 | Capacitor Layer Forming Material and Printed Wiring Board Having Embedded Capacitor Layer Obtained by using the Capacitor Layer Forming Material |
Publications (1)
Publication Number | Publication Date |
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WO2006049195A1 true WO2006049195A1 (ja) | 2006-05-11 |
Family
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PCT/JP2005/020183 WO2006049195A1 (ja) | 2004-11-04 | 2005-11-02 | キャパシタ層形成材及びそのキャパシタ層形成材を用いて得られる内蔵キャパシタ層を備えたプリント配線板 |
Country Status (7)
Country | Link |
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US (1) | US20080130196A1 (ja) |
EP (1) | EP1827064A4 (ja) |
JP (1) | JP3816508B2 (ja) |
KR (1) | KR100922467B1 (ja) |
CN (1) | CN101049055A (ja) |
TW (1) | TW200629993A (ja) |
WO (1) | WO2006049195A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008129704A1 (ja) * | 2007-04-18 | 2008-10-30 | Ibiden Co., Ltd. | 多層プリント配線板及びその製造方法 |
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JP4503583B2 (ja) * | 2006-12-15 | 2010-07-14 | 日本メクトロン株式会社 | キャパシタ用接着シートおよびそれを用いたキャパシタ内蔵型プリント配線板の製造方法 |
KR101448907B1 (ko) * | 2007-11-13 | 2014-10-14 | 삼성디스플레이 주식회사 | 액정표시장치의 백라이트 유닛 및 이를 포함하는액정표시장치 |
JP4844578B2 (ja) * | 2008-03-11 | 2011-12-28 | Tdk株式会社 | 電子部品の製造方法 |
JP5098743B2 (ja) * | 2008-03-26 | 2012-12-12 | Tdk株式会社 | 電子部品の製造方法 |
JP5082060B2 (ja) | 2008-05-22 | 2012-11-28 | 学校法人明星学苑 | 低特性インピーダンス電源・グランドペア線路構造 |
JP2010087499A (ja) * | 2008-09-30 | 2010-04-15 | Ibiden Co Ltd | コンデンサ装置の製造方法 |
US20100309608A1 (en) * | 2009-06-07 | 2010-12-09 | Chien-Wei Chang | Buried Capacitor Structure |
EP3273755B1 (en) * | 2009-09-15 | 2018-11-07 | Kabushiki Kaisha Toshiba | Process for producing a ceramic circuit board |
JP2013062265A (ja) * | 2010-01-15 | 2013-04-04 | Sanyo Electric Co Ltd | コンデンサ内蔵基板の製造方法 |
CN102143654A (zh) * | 2010-01-29 | 2011-08-03 | 旭硝子株式会社 | 元件搭载用基板及其制造方法 |
JP5757163B2 (ja) | 2011-06-02 | 2015-07-29 | ソニー株式会社 | 多層配線基板およびその製造方法、並びに半導体装置 |
CN103298274B (zh) * | 2012-02-24 | 2016-02-24 | 北大方正集团有限公司 | 一种埋容印制电路板的制作方法以及埋容印制电路板 |
JP5722813B2 (ja) * | 2012-03-02 | 2015-05-27 | Jx日鉱日石金属株式会社 | 電解銅箔及び二次電池用負極集電体 |
JP6015159B2 (ja) | 2012-06-22 | 2016-10-26 | Tdk株式会社 | 薄膜コンデンサ |
JP6287105B2 (ja) * | 2013-11-22 | 2018-03-07 | ソニー株式会社 | 光通信デバイス、受信装置、送信装置及び送受信システム |
CN113725002B (zh) * | 2021-09-02 | 2023-03-14 | 江门市东有科技有限公司 | 一种单层电容器及其制备方法 |
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- 2005-11-02 KR KR1020077010118A patent/KR100922467B1/ko not_active IP Right Cessation
- 2005-11-02 WO PCT/JP2005/020183 patent/WO2006049195A1/ja active Application Filing
- 2005-11-02 CN CNA2005800368421A patent/CN101049055A/zh active Pending
- 2005-11-03 TW TW094138544A patent/TW200629993A/zh unknown
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WO2008129704A1 (ja) * | 2007-04-18 | 2008-10-30 | Ibiden Co., Ltd. | 多層プリント配線板及びその製造方法 |
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Also Published As
Publication number | Publication date |
---|---|
EP1827064A1 (en) | 2007-08-29 |
JP2006135036A (ja) | 2006-05-25 |
US20080130196A1 (en) | 2008-06-05 |
TW200629993A (en) | 2006-08-16 |
EP1827064A4 (en) | 2008-06-11 |
JP3816508B2 (ja) | 2006-08-30 |
KR20070074599A (ko) | 2007-07-12 |
CN101049055A (zh) | 2007-10-03 |
KR100922467B1 (ko) | 2009-10-21 |
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