WO2006049007A1 - チャージポンプ回路 - Google Patents
チャージポンプ回路 Download PDFInfo
- Publication number
- WO2006049007A1 WO2006049007A1 PCT/JP2005/019010 JP2005019010W WO2006049007A1 WO 2006049007 A1 WO2006049007 A1 WO 2006049007A1 JP 2005019010 W JP2005019010 W JP 2005019010W WO 2006049007 A1 WO2006049007 A1 WO 2006049007A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- output
- charge pump
- pump circuit
- capacitor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Definitions
- the present invention relates to a charge pump circuit that outputs a predetermined voltage.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2000-0666747
- Figure 5 shows the same charge pump circuit described in Patent Document 1.
- the charge pump circuit 101 includes an input terminal 107 to which a power supply voltage V is input and a clock.
- the load is a power source portion of an electronic circuit that shares a predetermined function of the electronic device.
- first and second rectifier elements 110 and 111 which are diode elements, are connected in series.
- An output capacitor 112 and a series body of a resistor 113 and a resistor 114 for dividing the output voltage are connected to the output terminal 109.
- a voltage at a connection point between the resistor 113 and the resistor 114 is input to the operational amplifier 115 as a feedback voltage.
- Opamp 115 compares the feedback voltage with the reference voltage V and outputs a high level signal or low level.
- the output of the operational amplifier 115 is input to the base of an NPN bipolar transistor 116 whose emitter is grounded.
- the collector of the transistor 116 is connected to the collector of an NPN bipolar transistor 117 whose emitter is grounded and whose base and collector are connected.
- the collector of the transistor 117 is a constant current source 118 s that draws a constant current I from the input terminal 107.
- the base of the transistor 117 is connected to the base of an NPN bipolar transistor 119 whose emitter is grounded.
- the collector of transistor 119 is the current Error circuit 120 is connected to the IN terminal.
- the OUT1 terminal of the current mirror circuit 120 is connected to the collector of an NPN bipolar transistor 121 whose emitter is grounded, and the NPN bipolar transistor 122 whose emitter is grounded and whose base and collector are connected. Connected to the collector. The base of the transistor 121 is connected to the clock input terminal 108.
- an inverter 123 is connected to the clock input terminal 108, and the inverter 123 inverts and outputs the clock signal CLK.
- the output of the inverter 123 is input to the base of an NPN bipolar transistor 124 whose emitter is grounded.
- the collector of the transistor 124 is connected to the OUT2 terminal of the power mirror circuit 120 and is connected to the base of an NPN bipolar transistor 125 whose emitter is grounded.
- the base of the transistor 122 is connected to the base of an NPN bipolar transistor 126 having an emitter grounded.
- the collector of the transistor 126 is connected to the base of a PNP bipolar transistor 127 whose emitter is connected to the input terminal 107 and whose collector is connected to the collector of the transistor 125.
- the other end of the boost capacitor 128 is connected to the connection point between the collector of the transistor 125 and the collector of the transistor 127, and one end of the boost capacitor 128 is connected to the connection point of the first and second rectifier elements 110 and 111. Connected.
- the charge pump circuit 101 operates as follows. If the voltage at the connection point of resistor 113 and resistor 114, that is, the feedback voltage is lower than the reference voltage V, operational amplifier 115 is low.
- the transistor 116 Since the level signal is output, the transistor 116 is turned off. When the transistor 116 is turned off, a constant current I flows through the transistor 117, and the current mirror circuit 1 passes through the transistor 119.
- Constant current I flows through the 20 IN terminals.
- the OUT1 terminal of the current mirror circuit 120
- the constant current I flows through the child and OUT2 terminals.
- transistor 124 is on, transistor 125 is s
- the boost capacitor 128 increases, and the negative voltage of the first rectifying element 110, that is, the positive voltage of the second rectifying element 111 also increases. Then, the electric charge temporarily stored in the boost capacitor 128 moves to the positive side force negative side of the second rectifying element 111 and is stored in the output capacitor 112. In this way, when the feedback voltage is lower than the reference voltage V, the boost operation is performed and the voltage at the output terminal 109 is increased.
- the operational amplifier 115 When the feedback voltage is higher than the reference voltage V, the operational amplifier 115 outputs a high level signal.
- Transistor 116 is turned on.
- the transistors 117 and 119 are turned off and no current flows through the IN terminal of the current mirror circuit 120.
- no current flows through the OUT1 and OUT2 terminals of the current mirror circuit 120.
- the transistors 125 and 127 are both turned off regardless of whether the clock signal CLK is high or low, the charge does not move with respect to the first and second rectifier elements 110 and 111.
- the boost operation is stopped.
- the boosting operation is performed during the period of the clock signal CLK, and the output voltage rises slightly. After that, the output voltage gradually decreases as the output capacitor 112 is discharged according to the load weight, and the boosting operation is stopped until the feedback voltage becomes lower than the reference voltage V.
- Patent Document 1 Japanese Unexamined Patent Publication No. 2000-0666747
- the present invention has been made in view of the strong reasons, and an object of the present invention is to provide a charge pump circuit having a short output voltage ripple period and a small ripple voltage even when the load is light.
- a charge pump circuit includes first and second rectifier elements connected in series between an input terminal and an output terminal, and an output terminal.
- Output capacitor and a boost capacitor having one end connected to the connection point of the first and second rectifier elements, and the electric charge is increased by the voltage at the other end of the boost capacitor.
- An integrator that outputs the voltage obtained by integrating the difference between the feedback voltage from the output terminal and the reference voltage in the charge pump circuit that moves the rectifier element in order and accumulates it in the output capacitor to make the output terminal a predetermined voltage.
- a transistor on the power supply side and the ground side to which the clock signal is input, and a variable current source for supplying a current corresponding to the output voltage of the integrator to one of them, and according to the current flowing by the variable current source For boosting voltage And a clock inverter that outputs the other end of the capacitor.
- Another charge pump circuit includes first and second rectifier elements connected in series between an input terminal and an output terminal, an output capacitor connected to the output terminal, A boost capacitor whose one end is connected to the connection point of the first and second rectifier elements, and the electric charge is moved in order through the first and second rectifier elements by the voltage at the other end of the boost capacitor and output.
- the charge pump circuit that stores the output terminal at a predetermined voltage by being stored in the capacitor, an integrator that outputs a voltage obtained by integrating the difference between the feedback voltage from the output terminal and the reference voltage, and the input terminal and the first terminal A variable current source provided between the rectifying element and flowing a current corresponding to the output voltage of the integrator to the first rectifying element.
- the apparatus further includes one or a plurality of rectifier elements connected in series with the first and second rectifier elements.
- the rectifying element is a diode element.
- the rectifying element is a switch element, and the first and second rectifying elements are alternately turned on and off.
- a charge pump circuit includes an integrator that outputs a voltage obtained by integrating a difference between a feedback voltage of an output terminal and a reference voltage, and a variable current source that supplies a current corresponding to the output voltage.
- FIG. 1 is a circuit diagram of a charge pump circuit according to an embodiment of the present invention.
- FIG. 2 is a circuit diagram of a charge pump circuit according to another embodiment of the present invention.
- FIG. 3 is a circuit diagram of a charge pump circuit according to still another embodiment of the present invention.
- FIG. 4 is a circuit diagram of a charge pump circuit according to still another embodiment of the present invention.
- FIG. 5 is a circuit diagram of a conventional charge pump circuit.
- FIG. 1 is a circuit diagram of a charge pump circuit according to an embodiment of the present invention.
- this charge pump circuit 1 has a power supply voltage V
- the first and second rectifying elements 10 and 11 which are diode elements, are connected in series.
- the diode element it is also possible to use, for example, a MOS type transistor in which a force gate and drain are connected, which shows a PN junction diode in FIG.
- An output capacitor 12 and a series body of a resistor 13 and a resistor 14 for dividing the output voltage are connected to the output terminal 9.
- the output capacitor 12 has a large capacity to suppress the ripple voltage as much as possible, and the resistors 13 and 14 are high to reduce the current flowing toward the ground potential! ⁇ Become resistance value! / Speak.
- the voltage at the connection point between the resistor 13 and the resistor 14 is input to the integrator 15 as a feedback voltage.
- the integrator 15 outputs a voltage obtained by integrating the difference between the feedback voltage and the reference voltage V, and outputs the voltage.
- the current value of a variable current source 32 to be described later of the clock inverter 16 is controlled by the voltage.
- the clock inverter 16 inverts the clock signal CLK input from the clock input terminal 8 and outputs a voltage having a waveform corresponding to the current value of the variable current source 32.
- the output of the clock inverter 16 is connected to the other end of the boost capacitor 17 for boosting operation, and one end of the boost capacitor 17 is connected to the connection point of the first and second rectifier elements 10 and 11.
- the integrator 15 includes an operational amplifier 20, a capacitor 21, and a resistor 22.
- a connection point between the resistor 13 and the resistor 14 is connected between the inverting input terminal of the operational amplifier 20 and one end of the capacitor 21.
- the reference voltage V is input to the non-inverting input terminal, and the above-described feedback is input to the inverting input terminal.
- the feedback voltage is input, and the voltage obtained by integrating the difference between the feedback voltage and the reference voltage V from the output terminal is
- the output terminal of the operational amplifier 20 becomes the output of the integrator 15.
- the other end of the capacitor 21 is connected to one end of the resistor 22, and the other end of the resistor 22 is connected to the output terminal of the operational amplifier 20. Since the capacity of the capacitor 21 may be relatively small, the integrator 15 can also be integrated when many parts of the components of the charge pump circuit 1 are integrated in an integrated circuit.
- the clock inverter 16 includes a power supply side transistor 30 that is a PMOS type transistor, a ground side transistor 31 that is an NMOS type transistor, and a variable current source 32, and includes a power supply side transistor 30 and a ground side transistor 31. Is connected to the clock input terminal 8 and the power
- the source of the star 30 is connected to the input terminal 7, and the source of the ground side transistor 31 is connected to the variable current source 32.
- the drain of the power supply side transistor 30 and the drain of the ground side transistor 31 are connected to each other, and the connection point is the output of the clock inverter 16.
- the variable current source 32 flows a current toward the ground potential, and the current value is controlled by the output voltage of the integrator 15 as described above.
- the variable current source 32 can also be provided between the input terminal 7 and the power supply side transistor 30.
- the electric charge to which the force is supplied is accumulated in the output capacitor 12 by sequentially moving the first and second rectifier elements 10 and 11 by the voltage at the other end of the boost capacitor 17. As a result, a predetermined voltage is output from the output terminal 9.
- the output voltage of the output terminal 9 is divided by the resistor 13 and the resistor 14, and the voltage at the connection point, that is, the feedback voltage is integrated by the integrator 15.
- the current value of the variable current source 32 is controlled by the output voltage (integrated voltage) of the integrator 15 so that it increases when it increases and decreases when it decreases.
- the current value controls the degree of decrease when the output voltage of the clock inverter 16 decreases, and as a result, the charge moving through the first and second rectifying elements 10 and 11 is determined.
- the integrated voltage output from the integrator 15 slightly increases and the current value of the variable current source 32 increases.
- the output voltage of the clock inverter 16 decreases, if the current value of the variable current source 32 is large, the output voltage decreases. The amount of charge that moves from the positive side to the negative side of the first rectifying element 10 is increased.
- the load connected to the output terminal 9 is lightened, the integrated voltage output from the integrator 15 slightly decreases and the current value of the variable current source 32 decreases.
- the charge moving through the first and second rectifying elements is controlled according to the load, and when the load is light, the moving charge is reduced and the ripple voltage is reduced.
- the ripple voltage is reduced, the ripple period is short even if the discharge amount of the output capacitor 12 is very small.
- no period for stopping the boosting operation is provided, since unnecessary charges do not move through the first and second rectifying elements 10 and 11, current consumption is suppressed.
- this charge pump circuit 2 has an input terminal 7, a clock input terminal 8 and an output terminal 9, similarly to the charge pump circuit 1, and has an output capacitor 12 and an output voltage.
- a series body of a resistor 13 and a resistor 14 for voltage division, an integrator 15, a clock inverter 16 and a boost capacitor 17 are provided.
- the first and second rectifying elements 40 and 41 of a PMOS transistor which is a switch element are connected in series.
- the output of the inverter 42 that inverts the clock signal CLK is connected to the gate of the first rectifier element 40, and the output of the inverter 43 that further inverts the output of the inverter 42 is connected to the gate of the second rectifier element 41.
- the output is connected.
- Inverters 42 and 43 are supplied with the output voltage of output terminal 9 as the power source.
- the charge pump circuit 2 generally operates in the same manner as the charge pump circuit 1. However, the charge pump circuit 2 synchronizes with the change in the negative voltage of the first rectifier 40 via the boost capacitor 17.
- the second rectifier elements 40 and 41 are alternately turned on and off. That is, when the clock signal CLK at the clock input terminal 8 is at a high level, the voltage on the negative side of the first rectifier element 40 decreases via the boost capacitor 17 and the first rectifier element 40 is turned on. Charge is temporarily stored in the boost capacitor 17. Next, when the clock signal CLK becomes low level, the negative voltage of the first rectifier element 40, that is, the positive voltage of the second rectifier element 41 rises, and the second rectifier element 41 is turned on and boosted. The charge stored temporarily in the capacitor 17 is stored in the output capacitor 12.
- a force NMOS transistor or the like which shows a PMOS transistor in FIG. 2 may be used. It is also possible to provide a non-overlap period for the signals that control the gates of the first and second rectifying elements 40 and 41. In these cases, it is necessary to change the output polarity of the inverters 42 and 43 or to add a delay element. However, since this method is a normal technique for those skilled in the art, description thereof is omitted.
- variable current source is provided in series with the first and second rectifying elements.
- this charge pump circuit 3 has an input terminal 7, a clock input terminal 8 and an output terminal 9, similarly to the charge pump circuit 1, and has an output capacitor 12 and an output voltage. It has a series body of a resistor 13 and a resistor 14 for voltage division, an integrator 15 and a boost capacitor 17. Between the input terminal 7 and the output terminal 9, the first and second rectifier elements 10 and 11, which are diode elements, are connected in series. Further, a variable current source 51 is provided between the input terminal 7 and the first rectifying element 10. The variable current source 51 is controlled by the output voltage of the integrator 15. The other end of the boost capacitor 17 is connected to the output of the clock inverter 52. The clock inverter 52 inverts and outputs a clock signal CLK that is manually driven by eight clock human power terminals, but does not have a variable current source.
- the charge pump circuit 3 generally operates in the same manner as the charge pump circuit 1, but the current value of the variable current source 51 is controlled by the integrated voltage output from the integrator 15. Since this current value is the amount of electric charge that can move per unit time, this determines the electric charge that moves through the first and second rectifying elements 10 and 11. Thus, when the load is light, as with the charge pump circuit 1, the ripple voltage becomes small and the ripple period becomes short. In addition, current consumption is suppressed.
- the charge pump circuit 3 can be obtained by modifying the force charge pump circuit 2 which is a modification of the charge pump circuit 1 and using switch elements as the first and second rectifier elements. It is also possible to provide a variable current source in series with them.
- charge pump circuit 4 in addition to the constituent elements of charge pump circuit 1, charge pump circuit 4 includes a third rectifying element 11a provided between second rectifying element 11 and output terminal 9.
- a second boost capacitor 17a having one end connected to a connection point between the second rectifier element 11 and the third rectifier element 11a is provided.
- the other end of the second boost capacitor 17a is connected to the output of the second clock inverter 16a having the same configuration as that of the clock inverter 16.
- the gates of the second power supply side transistor 30a and the second ground side transistor 3la of the second clock inverter 16a are connected to the output of the inverter 18 that inverts the clock signal CLK.
- the current value of the second variable current source 32a is controlled by the output voltage of the integrator 15.
- the powerful charge pump circuit 4 operates as follows.
- the clock signal CLK is at a high level
- the negative voltage of the first rectifying element 10 decreases and the negative voltage of the second rectifying element 11 increases. Accordingly, the electric charge moves from the positive side to the negative side of the first rectifying element 10 and is temporarily stored in the boost capacitor 17, and the second boost from the positive side to the negative side of the third rectifying element 11a.
- the charge temporarily stored in capacitor 17a moves and is stored in output capacitor 12.
- the clock signal CLK becomes a low level
- the negative voltage of the first rectifying element 10 rises and the negative voltage of the second rectifying element 11 falls. Accordingly, the positive-side force of the second rectifying element 11 is also temporarily stored in the second boost capacitor 17a by moving the charge temporarily stored in the boost capacitor 17 to the negative side.
- one of the two clock inverters 16 and 16a may not have a variable current source. This is because there are cases where it is sufficient to control the electric charge moving through one rectifier element, V. In addition to the third rectifying element 11a, it is needless to say that more rectifying elements can be provided. Similarly to the charge pump circuit 1, the charge pump circuits 2 and 3 can be modified.
- the charge pump circuit according to the embodiment of the present invention has been described above! As described above, the present invention The present invention is not limited to those described in the embodiments, and various design changes can be made within the scope of the matters described in the claims.
- the integrator 15 can be composed of other internal circuits.
- the output voltage has a positive value.
- the present invention can also be applied to the output voltage having a negative value.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/576,622 US20080030261A1 (en) | 2004-11-05 | 2005-10-17 | Charge Pump Circuit |
CN2005800368027A CN101048930B (zh) | 2004-11-05 | 2005-10-17 | 电荷泵电路 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004322865A JP4666345B2 (ja) | 2004-11-05 | 2004-11-05 | チャージポンプ回路 |
JP2004-322865 | 2004-11-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006049007A1 true WO2006049007A1 (ja) | 2006-05-11 |
Family
ID=36319021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/019010 WO2006049007A1 (ja) | 2004-11-05 | 2005-10-17 | チャージポンプ回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20080030261A1 (ja) |
JP (1) | JP4666345B2 (ja) |
CN (1) | CN101048930B (ja) |
TW (1) | TW200631294A (ja) |
WO (1) | WO2006049007A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9484810B2 (en) | 2013-08-13 | 2016-11-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008029098A (ja) * | 2006-07-20 | 2008-02-07 | Oki Electric Ind Co Ltd | 昇圧回路 |
JP5183899B2 (ja) * | 2006-08-28 | 2013-04-17 | ローム株式会社 | 昇圧回路 |
CN101295470B (zh) * | 2007-04-25 | 2010-05-26 | 群康科技(深圳)有限公司 | 伽马电压输出电路和液晶显示装置 |
US8040175B2 (en) * | 2007-10-24 | 2011-10-18 | Cypress Semiconductor Corporation | Supply regulated charge pump system |
US20090140794A1 (en) * | 2007-11-29 | 2009-06-04 | Chi-Hao Wu | Constant-current charge pump |
TW200933562A (en) * | 2008-01-31 | 2009-08-01 | Tpo Displays Corp | Images display system |
US8049551B2 (en) * | 2008-06-17 | 2011-11-01 | Monolithic Power Systems, Inc. | Charge pump for switched capacitor circuits with slew-rate control of in-rush current |
JP5072731B2 (ja) * | 2008-06-23 | 2012-11-14 | 株式会社東芝 | 定電圧昇圧電源 |
JP2010035387A (ja) * | 2008-07-31 | 2010-02-12 | Daikin Ind Ltd | 電圧形駆動素子のゲート駆動装置 |
JP2011061891A (ja) * | 2009-09-07 | 2011-03-24 | Renesas Electronics Corp | 負荷駆動回路 |
WO2011067902A1 (ja) * | 2009-12-03 | 2011-06-09 | パナソニック株式会社 | 半導体集積回路およびそれを備えた昇圧回路 |
TWI423572B (zh) * | 2010-02-03 | 2014-01-11 | Univ Nat Chiao Tung | 高速升壓之充電泵電路 |
JP5581907B2 (ja) | 2010-09-01 | 2014-09-03 | 株式会社リコー | 半導体集積回路及び半導体集積回路装置 |
TWI463769B (zh) * | 2012-03-05 | 2014-12-01 | Novatek Microelectronics Corp | 充電幫浦裝置 |
US8922184B2 (en) * | 2012-03-22 | 2014-12-30 | Realtek Semiconductor Corp. | Integrated switch-capacitor DC-DC converter and method thereof |
KR20150024611A (ko) * | 2013-08-27 | 2015-03-09 | 삼성전기주식회사 | 전하 펌프 회로 |
PL227598B1 (pl) * | 2013-12-14 | 2018-01-31 | Uniwersytet Jagiellonski | Sposób pomiaru wolnozmiennego ładunku elektrycznego i układ do pomiaru wolnozmiennego ładunku elektrycznego |
US9819260B2 (en) * | 2015-01-15 | 2017-11-14 | Nxp B.V. | Integrated circuit charge pump with failure protection |
EP3350927A1 (en) * | 2015-09-15 | 2018-07-25 | Firecomms Limited | Glitch compensation in electronic circuits |
WO2018071819A1 (en) * | 2016-10-14 | 2018-04-19 | Cirrus Logic International Semiconductor, Ltd. | Charge pump input current limiter |
US10826452B2 (en) | 2017-02-10 | 2020-11-03 | Cirrus Logic, Inc. | Charge pump with current mode output power throttling |
US10651800B2 (en) | 2017-02-10 | 2020-05-12 | Cirrus Logic, Inc. | Boosted amplifier with current limiting |
WO2018207614A1 (ja) * | 2017-05-09 | 2018-11-15 | ソニーセミコンダクタソリューションズ株式会社 | 電源回路 |
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US6118346A (en) * | 1998-05-20 | 2000-09-12 | National Semiconductor Corp. | Dynamic matching of up and down currents in charge pumps to reduce spurious tones |
WO2001015228A1 (fr) * | 1999-08-19 | 2001-03-01 | Seiko Epson Corporation | Panneau de cablage, procede de fabrication d'un panneau de cablage, dispositif semiconducteur, procede de fabrication d'un dispositif semiconducteur, carte a circuit imprime et appareil electronique |
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US6927441B2 (en) * | 2001-03-20 | 2005-08-09 | Stmicroelectronics S.R.L. | Variable stage charge pump |
TWI245493B (en) * | 2001-10-24 | 2005-12-11 | Media Tek Inc | Apparatus for calibrating a charge pump and method therefor |
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2004
- 2004-11-05 JP JP2004322865A patent/JP4666345B2/ja not_active Expired - Fee Related
-
2005
- 2005-10-17 WO PCT/JP2005/019010 patent/WO2006049007A1/ja not_active Application Discontinuation
- 2005-10-17 CN CN2005800368027A patent/CN101048930B/zh not_active Expired - Fee Related
- 2005-10-17 US US11/576,622 patent/US20080030261A1/en not_active Abandoned
- 2005-10-26 TW TW094137535A patent/TW200631294A/zh not_active IP Right Cessation
Patent Citations (3)
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JPH0199433A (ja) * | 1987-10-09 | 1989-04-18 | Nec Corp | バランス型正負電流源回路 |
JP2001211636A (ja) * | 1999-12-23 | 2001-08-03 | Texas Instr Deutschland Gmbh | Dc/dcコンバータ及びdc/dcコンバータの動作方法 |
JP2004222398A (ja) * | 2003-01-14 | 2004-08-05 | Toppan Printing Co Ltd | チャージポンプ回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9484810B2 (en) | 2013-08-13 | 2016-11-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
CN101048930A (zh) | 2007-10-03 |
JP2006136134A (ja) | 2006-05-25 |
US20080030261A1 (en) | 2008-02-07 |
JP4666345B2 (ja) | 2011-04-06 |
TWI364156B (ja) | 2012-05-11 |
TW200631294A (en) | 2006-09-01 |
CN101048930B (zh) | 2012-06-06 |
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