WO2006038259A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2006038259A1 WO2006038259A1 PCT/JP2004/014356 JP2004014356W WO2006038259A1 WO 2006038259 A1 WO2006038259 A1 WO 2006038259A1 JP 2004014356 W JP2004014356 W JP 2004014356W WO 2006038259 A1 WO2006038259 A1 WO 2006038259A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- retainer ring
- semiconductor device
- manufacturing
- wafer
- polishing
- Prior art date
Links
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/27—Work carriers
- B24B37/30—Work carriers for single side lapping of plane surfaces
- B24B37/32—Retaining rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Definitions
- the present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing technique of a semiconductor device having a step of chemical mechanical polishing (CMP) of a semiconductor wafer. is there.
- CMP chemical mechanical polishing
- a semiconductor device manufacturing process includes various CMP processes. For example, a CMP process when forming a buried insulating film as an element isolation region on a semiconductor wafer by the STI (Shallow Trench Isolation) method, and a CMP process when flattening an interlayer insulating film formed on a semiconductor wafer There are a CMP process for forming a plug by embedding a conductive material in a through hole formed in an interlayer insulating film, or a CMP process for forming a buried wiring by a damascene method.
- STI Shallow Trench Isolation
- Patent Document 1 Japanese Patent Laid-Open No. 9-19863 (Patent Document 1) or the corresponding US Pat. No. 5795215 discloses a polishing head structure made of a plastic material on an aluminum wafer outer edge holding ring backing ring. A technique for screwing the wafer outer edge retaining ring is described.
- Patent Document 2 In Japanese Patent Laid-Open No. 2003-124169 (Patent Document 2), a retainer ring is attached to a holder of a wafer holding head, and a protective sheet is stretched inside the retainer ring, and the wafer is interposed via the protective sheet.
- an insert having a female thread portion is inserted into one of the through holes provided in each of the holder and the retainer ring, and the other through hole is inserted.
- a technique is described in which a bolt member having a threaded portion is penetrated and the insert and the bolt member are screwed together to attach the holder and the retainer ring.
- Patent Document 3 In Japanese Patent Laid-Open No. 2003-179014 (Patent Document 3), a retainer ring is attached to a holder of a wafer holding head, and a protective sheet is stretched inside the retainer ring, and the wafer is interposed via the protective sheet. In wafer polishing equipment that presses against the polishing pad to polish In addition, the outer peripheral edge portion of the protective sheet is sandwiched between the retainer ring and the holder, and tension adjusting means for the protective sheet is provided on the inner peripheral side of the sandwiching portion, and the protective sheet stretched by the tension adjusting means A technique is described in which the tension is variable.
- Patent Document 4 Japanese Patent Application Laid-Open No. 11-291162 (Patent Document 4) or the corresponding US Pat. No. 6,277,008 discloses a retainer ring, a resin part made of hard plastic such as polyethylene terephthalate, and stainless steel. And a technique in which the resin part is formed so as to cover the entire surface of the holding member.
- Patent Document 5 Japanese Patent Laid-Open No. 2003-179015 (Patent Document 5) or corresponding US Pat. No. 6,251,215 discloses a carrier head for a chemical mechanical polishing apparatus having a flexible lower portion. And a retaining ring having a rigid upper portion, the retaining ring contacting the polishing pad during polishing and a lower portion having a bottom surface made of a first material, and A technique is described that has an upper portion made of a second material that is more rigid than the first material.
- Patent Document 6 Japanese Patent Laid-Open No. 2001-71255 (Patent Document 6) or corresponding European Patent Publication No. 1080841 discloses that a retainer ring is fixed to a carrier in a polishing head, An elastic membrane is provided, and the peripheral portion of the elastic membrane is sandwiched and fixed between the retainer ring and the carrier, and the carrier is supplied with a fluid for supplying a pressure variable fluid between the elastic membrane and the carrier. Techniques for providing paths are described.
- Patent Document 7 Japanese Patent Laid-Open No. 2004-6653 (Patent Document 7) or the corresponding US Pat. No. 6773338 discloses that a wafer fixed to a porous film on the lower plate edge portion of the polishing head A technique is described in which a retainer ring for preventing it from being detached is crimped and fixed by a clamp ring fastened to a lower plate with a bolt.
- Patent Document 8 discloses a housing having a stepped structure therein, a retainer ring fixed around the housing, and an elastic membrane held by the retainer ring And a technique relating to a polishing head provided with a mechanism for introducing air into a sealed space formed by a housing, a retainer ring, and an elastic film or sucking air from the sealed space.
- Patent Document 9 discloses a wafer carrier for a wafer polishing apparatus.
- the carrier body includes a carrier body, a retainer ring that supports the wafer being polished in the circumferential direction, and a thin film member that transmits a pressing force to the wafer, and the carrier body uses air pressure that presses the thin film member.
- a technique is described in which a first pressing means is provided and a second pressing means for pressing the retainer ring downward by air pressure is provided separately from the first pressing means.
- Patent Document 1 Japanese Patent Laid-Open No. 9-19863
- Patent Document 2 Japanese Patent Laid-Open No. 2003-124169
- Patent Document 3 Japanese Patent Laid-Open No. 2003-179014
- Patent Document 4 JP-A-11 291162
- Patent Document 5 Japanese Unexamined Patent Publication No. 2003-179015
- Patent Document 6 Japanese Patent Laid-Open No. 2001-71255
- Patent Document 7 Japanese Unexamined Patent Application Publication No. 2004-6653
- Patent Document 8 Japanese Patent Laid-Open No. 11-333711
- Patent Document 9 Japanese Patent Laid-Open No. 2003-39306
- the semiconductor wafer held by the wafer holding unit is pressed against the polishing pad attached to the rotating platen (polishing surface plate) of the CMP apparatus while supplying the polishing liquid.
- the semiconductor wafer is polished.
- the uniformity of the polishing amount in the semiconductor wafer surface of the CMP apparatus largely depends on the surface shape of the retainer ring attached to the wafer holder. Since the surface of the retainer ring is polished together with the semiconductor wafer, the surface state of the retainer ring affects the polishing state of the semiconductor wafer (particularly the wafer edge portion). Since the polishing rate of the wafer edge of the semiconductor wafer changes depending on the wear state of the retainer ring, the uniformity of the in-plane polishing amount of the semiconductor wafer becomes unstable as the wear of the retainer ring progresses, and the quality of the manufactured semiconductor device May fluctuate. For this reason, it is necessary to periodically replace the retainer ring to control the flatness of the surface of the retainer ring.
- Retainer rings are expensive consumables, so the low cost of retainer rings can improve replacement life and reduce semiconductor device manufacturing costs. Is desired. If complicated work is required to replace the retainer ring, the operation rate of the CMP device may be lowered, and the manufacturing cost of the semiconductor device may be increased. For this reason, the retainer ring which can be replaced
- the retainer ring is fixed to the wafer holding portion when the retainer ring is replaced, the product wafer (semiconductor wafer for manufacturing a semiconductor device) is replaced with a new retainer ring.
- the condition of retainer ring Before starting the CMP process, it is necessary to adjust or confirm the polishing rate of the edge part of the semiconductor wafer by adjusting the condition of retainer ring. This lowers the operating rate of the CMP device and increases the manufacturing cost of the semiconductor device.
- One object of one invention disclosed in the present application is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.
- One invention disclosed in the present application is that the semiconductor wafer is held on the wafer holding part by retainer ring that also has a grease material force screwed to the wafer holding part from below, and the entire back surface of the wafer (peripheral part)
- mechanical pressure is often applied to semiconductor wafers under pressure with static gas pressure (or compressible fluid pressure) or quasi-static gas pressure through a membrane (or flexible thin film). Machine polishing.
- one invention disclosed in the present application is that the semiconductor wafer is held in the wafer holding part by the retainer ring that is screwed to the wafer holding part from below and held by the retainer ring. It is to be polished.
- one invention disclosed in the present application is that the semiconductor wafer is held in the state where the semiconductor wafer is held in the wafer holding portion by retainer ring having a grease material force screwed to the wafer holding portion from below.
- a screw hole for screwing the retainer ring is formed in a groove formed on the lower surface of the retainer ring after polishing.
- one invention disclosed in the present application is a state in which the semiconductor wafer is held on the wafer holding portion by retainer ring having a grease material force screwed to the wafer holding portion from below.
- the semiconductor wafer is subjected to mechanical mechanical polishing, the diaphragm is fixed to the wafer holding portion with a diaphragm fixing member, and the retainer ring is screwed to the diaphragm fixing member from below.
- one invention disclosed in the present application is that the semiconductor wafer is held in the wafer holding part by the retainer ring that is screwed to the wafer holding part from below and held by the retainer ring. Polishing is performed, and the elastic film is fixed to the wafer holding portion with an annular metal member. A retainer ring is screwed to the metal member from below.
- the manufacturing cost of the semiconductor device can be reduced.
- FIG. 1 is a cross-sectional view of a principal part of a semiconductor wafer showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;
- FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2;
- FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;
- FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;
- FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;
- FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;
- FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
- FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
- FIG. 10 is an explanatory diagram showing a processing sequence of a CMP process.
- FIG. 11 is an explanatory diagram showing a schematic configuration of a CMP apparatus.
- FIG. 12 is an explanatory diagram showing a schematic configuration of a CMP apparatus.
- FIG. 13 is an explanatory diagram showing a state in which a semiconductor wafer is subjected to CMP processing by one of a plurality of platens constituting a CMP apparatus.
- FIG. 14 is a cross-sectional view of a main part of the polishing head.
- FIG. 15 is a cross-sectional view of the main part of the vicinity of the retainer ring of the polishing head.
- FIG. 16 is a plan view of a diaphragm fixing ring.
- FIG. 17 is a plan view showing a state in which the retainer ring is attached to the diaphragm fixing ring.
- FIG. 18 is a cross-sectional view of the main part showing a state where the retainer ring is attached to the diaphragm fixing ring.
- FIG. 19 is a cross-sectional view of the principal part showing a state where the retainer ring is attached to the diaphragm fixing ring.
- FIG. 20 is a cross-sectional view of the main part showing a state where the retainer ring is attached to the diaphragm fixing ring.
- FIG. 21 is a cross-sectional view of a principal part showing a polishing head of a first comparative example.
- FIG. 22 is a cross-sectional view of a principal part showing a polishing head of a second comparative example.
- FIG. 23 is an explanatory view showing a wear model of the retainer ring.
- FIG. 24 is a cross-sectional view conceptually showing a state where the polishing liquid has entered between the diaphragm fixing ring and the retainer ring.
- FIG. 25 is a plan view showing the lower surface of the diaphragm fixing ring when the retainer ring is removed after the CMP process.
- FIG. 26 is a plan view of a retainer ring according to another embodiment of the present invention.
- FIG. 27 is a cross-sectional view of a retainer ring according to another embodiment of the present invention.
- a pure silicon region a region containing impurity-doped silicon as a main component, or silicon such as GeSi is the main component. It includes a mixed crystal region as a constituent element.
- MIS is not limited to pure metals, unless explicitly stated otherwise, and includes polysilicon (including amorphous) electrodes, silicide layers, and other materials that exhibit metal-like properties.
- I when referring to MIS is not limited to an oxide film such as a silicon oxide film, unless otherwise specified, and is not limited to a nitride film, an oxynitride film, an alumina film, or other ordinary dielectrics, high A dielectric, a ferroelectric film, etc. are included.
- a wafer is a silicon or other semiconductor single crystal substrate used for manufacturing a semiconductor integrated circuit (generally a substantially disk shape, a semiconductor wafer, other semiconductor chips or pellets obtained by dividing them into unit integrated circuit regions, and The substrate region), an epitaxial substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and their composite substrates.
- a semiconductor integrated circuit generally a substantially disk shape, a semiconductor wafer, other semiconductor chips or pellets obtained by dividing them into unit integrated circuit regions, and The substrate region
- an epitaxial substrate generally a substantially disk shape, a semiconductor wafer, other semiconductor chips or pellets obtained by dividing them into unit integrated circuit regions, and The substrate region
- a sapphire substrate a glass substrate
- other insulating, anti-insulating or semiconductor substrates and their composite substrates.
- CMP Chemical mechanical polishing
- a slurry in a state where the surface to be polished is in contact with a polishing pad having a relatively soft cloth-like sheet material and the like.
- the polishing is performed by moving the surface to be polished relative to the hard grindstone surface in order to perform polishing.
- Other fixed barrels are used, and non-abrasive abrasive-free CMP is used.
- Polishing liquid is generally a suspension of chemical etching chemicals mixed with abrasive barrels, but with abrasive grains mixed! Wow! /, Including things.
- Embedded wiring or embedded metal wiring is generally a single damascene (single machine).
- the unnecessary conductive film on the insulating film is removed.
- single damascene is an embedded wiring process that embeds in two stages: plug metal and wiring metal.
- dual damascene generally refers to an embedded wiring process in which plug metal and wiring metal are embedded at once.
- copper embedded wiring is often used in a multilayer configuration.
- semiconductor device refers to an epitaxial substrate, an SOI substrate, and an SOI substrate, unless specifically stated that the device is made only on a single crystal silicon substrate. (Silicon On Insulator) substrate, TFT (Thin Film Transistor) liquid crystal manufacturing substrate, etc.
- a semiconductor integrated circuit chip or a semiconductor chip refers to a wafer in which a wafer process (wafer process or previous process) has been completed divided into unit circuit groups. .
- a low dielectric constant insulating film is a dielectric constant lower than the dielectric constant of an oxide silicon film (eg, TEOS (Tetraethoxysilane) oxide film) contained in a passivation film.
- the insulating film which has can be illustrated.
- FIG. 9 is a cross-sectional view of the main part in the manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor).
- MISFET Metal Insulator Semiconductor Field Effect Transistor
- a powerful semiconductor wafer (wafer, semiconductor substrate) 1 such as p-type single crystal silicon having a specific resistance of about 10 ⁇ cm is prepared.
- an element isolation region 2 made of an insulator is formed on the main surface of the semiconductor wafer 1 on the semiconductor element formation side by using, for example, an STI (Shallow Trench Isolation or SGI: Shallow Groove Isolation) method.
- the element isolation region 2 can be formed as follows, for example.
- an insulating film 3 having a strong force such as silicon nitride is formed on the main surface of the semiconductor wafer 1, and the insulating film 3 is patterned using a photolithography method, a dry etching method, or the like.
- the semiconductor substrate 1 is etched to a predetermined depth to form an element isolation groove 2 a on the main surface of the semiconductor wafer 1.
- an insulating film 4 such as silicon oxide after the bottom and side walls of the device isolation trench 2a are oxidized by a thermal acid method if necessary. To form.
- CMP Chemical Mechanical Polishing
- the insulating film 4 is placed in the element isolation trench 2a.
- the other unnecessary portions of the insulating film 4 are removed.
- the element isolation region 2 made of the insulating film 4 filling the element isolation trench 2a can be formed.
- the remaining insulating film 3 is removed.
- the element isolation region 2 functions to isolate elements (semiconductor elements such as MISFETs) formed on the semiconductor wafer 1. This eliminates electrical interference between the formed elements and allows individual elements to be controlled independently.
- a ⁇ -type well 6 is formed in the region of the semiconductor wafer 1 where the n-channel MISFET is to be formed.
- the p-type well 6 can be formed by ion implantation of a p-type impurity such as boron (B).
- an insulating film 7 a for forming a gate insulating film is formed on the surface of the p-type well 6.
- the insulating film 7a also has a force such as a thin oxide silicon film, and can be formed by, for example, a thermal oxidation method.
- the gate electrode 8 is formed on the insulating film 7 a of the p-type well 6.
- a polycrystalline silicon film is formed on the main surface of a semiconductor wafer 1 and phosphorus (P) is ion-implanted into the polycrystalline silicon film to form a low-resistance n-type semiconductor film.
- P phosphorus
- the gate electrode 8 made of the patterned polycrystalline silicon film can be formed.
- the insulating film 7a under the gate electrode 8 becomes the gate insulating film 7 of the MISFET.
- n-type impurities such as phosphorus (P) or arsenic (As) into regions on both sides of the gate electrode 8 of the p-type well 6, (a pair of) n-type semiconductor regions Form 9.
- a side wall spacer or side wall 10 having a force such as silicon oxide is formed on the side wall of the gate electrode 8.
- the sidewall 10 can be formed, for example, by depositing an oxide silicon film on the semiconductor wafer 1 and anisotropically etching the oxide silicon film.
- the (pair) n + type semiconductor regions 11 are formed on the gate electrode 8 of the p-type well 6 and the regions on both sides of the sidewall 10 (P).
- n-type impurities such as arsenic (As).
- annealing treatment heat treatment
- the n + type semiconductor region 11 has a higher impurity concentration than the n ⁇ type semiconductor region 9.
- an n-type semiconductor region (impurity diffusion layer) that functions as a source or drain of the n-channel MISFET is formed by the n + -type semiconductor region 11 and the n ⁇ type semiconductor region 9.
- the gate electrode 8 and the n + type semiconductor region 11 are exposed.
- a metal silicide film for example, a cobalt silicide (CoSi) film
- CoSi cobalt silicide
- n-channel MISFET Metal Insulator Semiconductor Field Effect Transistor 13 is formed. It is also possible to form a p-channel MISFET by reversing the n-type and p-type conductivity types.
- a relatively thin insulating film (etching stubber film) 21 such as a silicon nitride film, a relatively thick silicon oxide film, etc.
- An insulating film (interlayer insulating film) 22 that also has a force is sequentially deposited using, for example, a CVD method.
- the insulating film 21 on the lower layer side can function as an etching stopper film when a contact hole 23 described later is formed. Further, the insulating film 21 on the lower layer side can be omitted if unnecessary.
- a CMP process is performed to polish the insulating film 22, and the surface of the insulating film 22 is planarized.
- the insulating film 22 and the insulating film 21 are formed.
- a contact hole (opening) 23 is formed in an upper portion of the n + type semiconductor region (source, drain) 11 or the like.
- a part of the main surface of the semiconductor wafer 1 for example, a part of the n + type semiconductor region 11 (silicide film 12 on the surface thereof) or the gate electrode 8 (silicide film 12 on the surface thereof) Some parts are exposed.
- a noria film for example, titanium nitride film
- a tungsten film 24b is formed by CVD or the like so as to fill the contact hole 23 on the noria film 24a.
- CMP is performed to polish the tungsten film 24b and the barrier film 24a until the upper surface of the insulating film 22 is exposed.
- CMP treatment unnecessary tungsten film 24b and barrier film 24a on insulating film 22 are removed, and tungsten film 24b and barrier film 24a are left in contact hole 23, so that the plug embedded in contact hole 23 is left. 24 can be formed.
- an insulating film (etching dust film) 25, an insulating film (interlayer insulating film) 26, and an insulating film 27 are sequentially formed on the insulating film 22 in which the plug 24 is embedded.
- the insulating film 25 is made of, for example, a silicon nitride film or a silicon carbide film, and can function as an etching stover film when the insulating film (interlayer insulating film) 26 is etched.
- the insulating film 26 as an interlayer insulating film can be formed of a low dielectric constant material (a so-called Low-K insulating film, Low-K material) or the like.
- the insulating film 27 can be formed of, for example, an oxide silicon film, and has functions such as ensuring the mechanical strength, surface protection, and moisture resistance of the insulating film 26 during CMP processing, for example. it can.
- the insulating films 25, 26, 27 are selectively removed to form openings (wiring openings, wiring grooves) 28. At this time, the upper surface of the plug 24 is exposed at the bottom of the opening 28.
- a relatively thin conductive barrier film (for example, titanium nitride film) 29 is formed on the entire main surface of the semiconductor wafer 1 (that is, on the insulating film 27 including the bottom and side walls of the opening 28).
- the main conductor film 30 having a relatively thick copper force is formed on the conductive barrier film 29 so as to fill the opening 28.
- the main conductor film 30 and the conductive barrier film 29 are polished until a top surface of the insulating film 27 is exposed by performing a CMP process.
- a CMP process By this CMP treatment, unnecessary conductive barrier film 29 and main conductor film 30 on insulating film 27 are removed, and conductive noria film 29 and main conductor film 30 are left in opening 28, whereby wiring (first (Layer wiring, embedded copper wiring) 31 is formed in the opening 28.
- the formed wiring 30 is electrically connected to the n + type semiconductor region 11 for the source or drain of the n channel MISFET 13, the gate electrode 8, and the like through the plug 24.
- an interlayer insulating film, an upper wiring layer, and the like are further formed on the insulating film 27 including the upper surface of the wiring 31, but illustration and description thereof are omitted here.
- the manufacturing process of the semiconductor device includes various CMP processes.
- a CMP process for forming the element isolation region 2 a CMP process for flattening an interlayer insulating film (for example, the insulating film 22) formed on the semiconductor wafer, a through hole formed on the interlayer insulating film (for example, There is a CMP process for forming a plug (for example, plug 24) by embedding a conductive material in the contact hole 23) or a CMP process for forming a buried wiring (for example, wiring 31) by the damascene method.
- FIG. 10 is an explanatory diagram showing a processing sequence (flow) of the CMP process.
- 11 and 12 are explanatory diagrams (plan views) showing a schematic configuration of a CMP apparatus 51 used in the CMP process performed in the present embodiment.
- FIG. 13 is an explanatory view (side view) showing a state in which the semiconductor wafer 1 is subjected to the CMP process with one platen 53 of the plurality of platens 53 constituting the CMP apparatus 51.
- FIG. 12 shows a state in which the multi-head holding portion 55 is seen through in the CMP apparatus 51 of FIG.
- the CMP apparatus 51 used in the CMP process performed in the present embodiment is a multi-platen multihead CMP apparatus.
- a multi-platen 'multi-head type CMP apparatus 51 to perform single wafer processing on a semiconductor wafer, the throughput of CMP processing can be improved.
- a CMP apparatus 51 shown in FIGS. 11, 12, and 13 includes a load cup 52 for loading and unloading a semiconductor wafer, and a plurality of rotatable platens (polishing platens) 53, for example, 3 It has two platens (polishing surface plates) 53a, 53b, 53c and a plurality of polishing heads (wafer holding unit, wafer holding head, wafer carrier) 54 capable of holding a semiconductor wafer, for example, four polishing heads 54 . These four polishing heads 54 are supported by a multi-head holding unit 55, and each polishing head 54 is configured to be rotatable while holding a semiconductor wafer.
- a polishing pad (polishing cloth) 58 is attached to the upper surface of each platen 53.
- polishing heads 54 Of the four polishing heads 54, three polishing heads 54 on the platens 53a, 53b, 53c hold the semiconductor wafer and press the semiconductor wafer against the polishing pad 58 on the upper surface of the platens 53a, 53b, 53c.
- One of the polishing heads 54 on the load cup 52 is configured to receive a semiconductor wafer from the load cup 52 and to send the semiconductor wafer to the load cup 52.
- a polishing pad mainly composed of foamed polyurethane can be used as the polishing pad attached to the upper surface of each of the platens 53a, 53b, 53c.
- the CMP apparatus 51 further applies a dressing process to the polishing pad 58 on the upper surface of each of the platens 53a, 53b, 53c (the surface of the polishing pad 58 smoothed by the sharpening process, abrasion, etc. of the polishing pad 58) Conditioner (dresser, dressing member) 56 for repairing or repairing using a turret (orre) etc., and on each platen 53a, 53b, 53c And a nozzle 57 for supplying a liquid 59 such as polishing liquid (slurry, chemical liquid) or water (pure water) to the surface polishing pad 58.
- the platens 53a, 53b, 53c, the polishing head 54, and the conditioner 56 are each configured to be rotatable by a motor or the like.
- the polishing head 54 can hold the semiconductor wafer by chucking it.
- the nozzle 57a supplies polishing liquid (slurry, chemical) to the polishing pad 58 on the upper surface of the platen 53a
- the nozzle 57b supplies polishing liquid (slurry, chemical) to the polishing pad 58 on the upper surface of the platen 53b
- the nozzle 57c supplies water (pure water) to the polishing pad 58 on the upper surface of the platen 53c.
- the platen 53a and the platen 53b are polishing plates that mainly perform polishing using a polishing slurry
- the platen 53c is not a polishing slurry but water (pure water).
- This is a puff platen mainly for cleaning with water.
- a diamond grindstone abrasive grain
- the conditioner 56 the surface that contacts the polishing pad 58 in the dressing process.
- a material film to be subjected to CMP treatment for example, the insulating film 4, the insulating film 22, the noria film 24a and the tungsten film 24b, or the conductive barrier film 29 and the main conductor film 30.
- a film forming apparatus for example, a CVD apparatus
- the polishing head 54 is held on the polishing head 54 (step S2).
- the semiconductor wafer 1 held (supported) by the polishing head 54 is polished (CMP process) while the three heads 53a, 53b, and 53c are sequentially moved as the multi-head holding unit 55 rotates.
- the polishing head 54 on each of the platens 53a, 53b, 53c and the load cup 52 moves to the next platen 53 or load cup 52.
- the polishing head 54 holding the semiconductor wafer 1 with the load cup 52 moves onto the platen 53a as the multi-head holding unit 55 rotates.
- the polishing pad 58 on the upper surface of the rotating platen 53a the surface of the rotating semiconductor wafer 1 held (supported) by the polishing head 54 (a material film to be subjected to CMP processing was formed).
- Semiconductor wafer 1 is pressed against the polishing pad with a predetermined pressure.
- the polishing liquid is supplied as the liquid 59 from the nozzle 57a to the polishing node 58 on the upper surface of the platen 53a. While supplying the polishing liquid onto the polishing pad 58, the surface of the semiconductor wafer 1 and the polishing pad on the upper surface of the platen 53a are rubbed by their rotation, and the surface of the semiconductor wafer 1 is chemically mechanically polished (Chemical Mechanical Polishing). : CMP) (step S3). As a result, the material film force SCMP (chemical mechanical polishing) process to be CMP-processed formed on the surface of the semiconductor wafer 1 is performed.
- SCMP chemical mechanical polishing
- the condition of the polishing pad 58 can be maintained by dressing the surface of the polishing pad 58 by pressing the conditioner 56 against the polishing pad 58 on the upper surface of the platen 53a with a predetermined pressure.
- a retainer ring 60 made of a resin material is screwed to the polishing head 54 from below, and this retainer ring 60 prevents the semiconductor wafer 1 from being displaced from the polishing head 54 during polishing. To prevent. That is, the semiconductor wafer 1 can be mechanically polished with the retainer ring 60 while the semiconductor wafer 1 (outer edge) is held (supported) by the polishing head 54.
- the retainer ring 60 has an annular (ring-shaped) shape surrounding the semiconductor wafer 1.
- FIG. 13 shows a cross section of the retainer ring 60.
- the multi-head holding part 55 rotates, so that the polishing head 54 on each of the platens 53a, 53b, 53c and the load cup 52 becomes the next platen 53 or load. Move onto cup 52.
- the polishing head 54 on the platen 53a moves onto the platen 53b as the multi-head holding part 55 rotates.
- the surface of the rotating semiconductor wafer 1 held (supported) by the polishing head 54 contacts the polishing pad 58 on the upper surface of the rotating platen 53b, and the semiconductor wafer is pressed at a predetermined pressure. 1 is pressed against the polishing pad 58.
- polishing liquid is supplied to the polishing pad 58 on the upper surface of the platen 53b as the force of the nozzle 57b is also the liquid 59.
- polishing CMP
- step S4 the material film formed on the surface of the semiconductor wafer 1 and to be subjected to the CMP process is further subjected to the CMP (chemical mechanical polishing) process.
- the conditioner 56 is pressed against the polishing pad 58 on the upper surface of the platen 53b with a predetermined pressure, and the surface of the polishing pad 58 is dressed. The polishing conditions of the polishing pad can be maintained.
- the retainer ring 60 prevents the semiconductor wafer 1 from being detached from the polishing head 54 during polishing.
- the multi-head holding part 55 rotates, so that the polishing head 54 on each of the platens 53a, 53b, 53c and the load cup 52 becomes the next platen. Move to 53 or load cup 52. At this time, the polishing head 54 on the platen 53b moves onto the platen 53c as the multi-head holding unit 55 rotates. Then, as shown in FIG. 13, the surface of the rotating semiconductor wafer 1 held (supported) by the polishing head 54 contacts the polishing pad 58 on the upper surface of the rotating platen 53b, and the semiconductor wafer is pressed at a predetermined pressure. 1 is pressed against the polishing pad 58.
- Step S5 pure water (rinse liquid) is supplied to the polishing pad 58 on the upper surface of the platen 53c as the force of the nozzle 57c as the liquid 59.
- the surface of the semiconductor wafer 1 and the polishing pad 58 on the upper surface of the platen 53c are rubbed by their rotation, and the surface of the semiconductor wafer 1 is cleaned (washed with water) (Ste S5).
- the conditioner 56 is pressed against the polishing pad 58 on the upper surface of the platen 53c with a predetermined pressure, and the surface of the polishing pad 58 is dressed.
- the retainer ring 60 prevents the semiconductor wafer 1 from being detached from the polishing head 54.
- the multi-head holding unit 55 rotates, so that the polishing heads 54 on the platens 53a, 53b, 53c and the load cup 52 are Move onto platen 53 or load cup 52.
- the polishing head 54 on the platen 53c moves onto the load cup 52 and is removed from the polishing head 54 by the load cup 52 (step S6).
- the removed semiconductor wafer 1 is sent to a cleaning device.
- the cleaning device the cleaning process of the semiconductor wafer 1 after the CMP process
- the front surface and the back surface of the semiconductor wafer 1 are brush cleaned (step S7). Then, for example, APM (APM).
- the semiconductor wafer 1 is wet-cleaned by using Ammonia-Hydrogen Peroxide Mixture ((), DHF (Diluted Hydrofluoric acid) ⁇ or HPM (Hydrochloric acid-Hydrogen Peroxide Mixture) (step S8). Further, after cleaning the semiconductor wafer 1 with pure water (step S9), the semiconductor wafer 1 is rotated and dried (spin drying) while blowing, for example, nitrogen gas (step S10). . CMP process followed by C The post-MP cleaning process is performed consistently.
- Ammonia-Hydrogen Peroxide Mixture ((), DHF (Diluted Hydrofluoric acid) ⁇ or HPM (Hydrochloric acid-Hydrogen Peroxide Mixture)
- polishing head of the CMP apparatus 51 used in the CMP process performed in the present embodiment is the polishing head of the CMP apparatus 51 used in the CMP process performed in the present embodiment.
- FIG. 14 is a cross-sectional view of the main part of the polishing head 54 of the CMP apparatus 51
- FIG. 15 is a cross-sectional view of the main part in the vicinity of the retainer ring 60 of the polishing head 54.
- FIG. 14 shows a cross-sectional view of the left half of the polishing head 54.
- the rotation indicated by the two-dot chain line is shown in FIG.
- a cross-sectional structure symmetrical to the left side may be described on the right side of the axis 110.
- the polishing head 54 of the present embodiment includes a head main body (node, waving member) 101, a carrier plate (base member, barrel) 102, a carrier (wafer backing assembly) 103, and a retainer ring 60. have.
- the head main body 101 is formed in a substantially disk shape, and its central upper part is connected to a rotating shaft (not shown) driven by a motor so as to be rotatable around the rotating shaft 110. It is made.
- the carrier plate 102 is positioned below the head main body 101 and has a substantially annular shape.
- the carrier plate 102 can be formed of a material having rigidity such as stainless steel.
- the carrier portion 103 has a substantially disk shape, and holds the one surface of the semiconductor wafer 1 to be CMP-processed on its lower surface.
- the carrier portion 103 includes a support plate 111 made of a disk-like member (a perforated disc body) having a plurality of holes 11 la and an annular (ring-like) first fixed connected to the outer peripheral portion of the upper surface of the support plate 111.
- the support plate 111, the first fixing ring 112, and the second fixing ring 114 are fixed by screwing (screwing).
- the diaphragm 113 has an annular (ring shape) shape. Diaphragm 113 is flexible and elastic, and is formed by an elastic film (elastic film) such as rubber. Can be made. The inner edge of the diaphragm 113 is sandwiched and fixed (clamped) between the first fixing ring 112 and the second fixing ring 114. The outer edge of the diaphragm 113 is sandwiched and fixed (clamped) between a carrier plate 102 and a diaphragm fixing ring (diaphragm fixing member, flexor fixing ring, clamp ring, metal member) 120.
- a diaphragm fixing member diaphragm fixing member, flexor fixing ring, clamp ring, metal member
- the diaphragm 113 can function to seal a space (a space 151 described later) between the lower surface of the carrier plate 102 and the carrier portion 103.
- the diaphragm fixing ring 120 has an annular (ring shape) shape.
- the diaphragm fixing ring 120 is made of a material having higher mechanical strength than the retainer ring 60 made of a resin material, that is, a metal material.
- the diaphragm fixing ring 120 is formed of a material having high rigidity such as stainless steel.
- the diaphragm fixing ring 120 is disposed on the outer peripheral portion of the lower surface of the carrier plate 102, and the carrier plate 102 and the diaphragm fixing ring 120 are fixed by being screwed with screws 121 from the upper surface side of the carrier plate 102.
- the membrane 115 has a circular thin film shape.
- the membrane 115 is flexible and elastic, and can be formed of an elastic film (elastic film) such as rubber, for example.
- the membrane 115 is a force extending below the support plate 111.
- the outer periphery of the membrane 115 extends on the side wall of the support plate 111 to the upper surface end of the support plate 111, and the support plate 111 and the first fixing ring. It is sandwiched between 112 and fixed (clamped)!
- the carrier plate 102 is connected to the ring member 131 by, for example, screwing, and the ring member 131 is connected to the cylindrical rod 132 by, for example, screwing.
- the rod 132 is inserted into an inner hole 133a of a cylindrical bush (bush) 133 fixed to the head body 101, and can move smoothly along the inner hole 133a. Accordingly, the carrier plate 102 can be moved in the vertical direction (vertical direction) with respect to the head main body 101, and the horizontal movement (lateral direction) of the carrier plate 102 with respect to the head main body 101 can be prevented.
- annular (ring-shaped) diaphragm 141 made of a flexible elastic film is fixed (clamped) to the head main body 101 by a fixing ring (inner clamp ring) 142, and the die is fixed.
- the outer edge of the diaphragm 141 is fixed (clamped) to the carrier plate 102 by a fixing ring (outer clamp ring) 163.
- the diaphragm 141 can function to seal a space (a space 152 to be described later) between the lower surface of the head main body 101 and the upper surface of the carrier plate 102.
- Membrane 115 support plate 111, first fixing ring 112, second fixing ring 114, diaphragm 113, carrier plate 102 (lower surface), ring member 131 (lower surface) and rod 13 2 (inner wall)
- the pressure in the space 151 (sealed) between them is configured to be controllable!
- a pump (not shown) or the like is fluidly connected to the space 151 via the inner hole 133a of the bush 133 and the inner hole 132a of the rod 132 so that the pressure in the space 151 can be controlled to a desired pressure. It is summer.
- the downward force of the membrane 115 (the force or pressure with which the membrane 115 presses the semiconductor wafer 1 against the polishing pad 58) can be controlled.
- the membrane 115 By increasing the pressure in the space 151 by introducing pressurized gas into the space 151, the membrane 115 is expanded, and the force (pressure) that the membrane 115 presses the semiconductor wafer 1 against the polishing pad 58 can be increased.
- the membrane 115 By reducing the pressure in the space 151, the membrane 115 can be contracted, and the force (pressure) by which the membrane 115 presses the semiconductor wafer 1 against the polishing pad 58 can be reduced.
- the pressure in the space 152 sealed (sealed) between the head body 101 (the lower surface), the diaphragm 141, the carrier plate 102 (the upper surface) and the rod 132 (the outer wall) can be controlled.
- a pump (not shown) or the like is fluidly connected to the space 152 via a path (hole) 153 so that the pressure in the space 152 can be controlled to a desired pressure.
- the carrier plate 102 By adjusting the pressure in the space 152, the carrier plate 102 can be pushed down, and the pressure at which the retainer ring 60 pushes the polishing pad 58 can be controlled.
- the carrier plate 102 is caused to act downward, and the pressure that the retainer ring 60 presses the polishing pad 58 is increased. Reducing the pressure in the space 152 causes the carrier plate 102 to move upward, reducing the pressure at which the retainer ring 60 presses the polishing pad 58. Can. By adjusting the pressure of the space 152 in this way, it becomes possible to mainly control the polishing rate at the wafer edge of the semiconductor wafer 1.
- an inner tube 161 having a force such as a flexible elastic membrane (elastic membrane) is attached to the lower surface of the carrier plate 102.
- the pressure of the space 162 sealed (sealed) by the control is configured to be controllable.
- a path connected to a pump is fluidly connected to the space 162 so that the pressure in the space 162 can be controlled to a desired pressure.
- the inner tube 161 is inflated to cause downward pressure to act on the second fixing ring 114 with which the inner tube 161 is in contact, and the carrier portion 103 causes the semiconductor wafer 1 to be applied to the polishing pad 58.
- the pressing force pressure
- the pressing force can be increased.
- the entire back surface of the semiconductor wafer 1 (generally, mechanical pressure is generally applied to the peripheral portion) via the membrane 115 (or a flexible thin film) is static gas.
- the semiconductor wafer 1 is mechanically polished with pressure (or compressible fluid pressure) or quasi-static gas pressure.
- the semiconductor wafer 1 is held on the polishing head 54 (wafer holding portion) by a retainer ring 60 having a grease material force screwed to the polishing head 54 (wafer holding portion) from below.
- the diaphragm fixing ring 120 is configured such that the outer edge of the diaphragm 113 is sandwiched between the upper surface of the diaphragm fixing ring 120 and the lower surface of the carrier plate 102, and the carrier plate is screwed from the upper surface side of the carrier plate 102 with the screw 121. Screwed to 102 and fixed.
- the portion of the upper surface of the diaphragm fixing ring 120 that comes into contact with the diaphragm 113 is provided with an uneven portion 120a.
- the uneven portion 120a can be used to clamp the diaphragm 113 made of an elastic film with a strong force. Yes.
- the lower surface 120b of the diaphragm fixing ring 120 is attached with 60 forces!
- Jetnering 60 It has an annular (ring-like) shape and is made of a resin material.
- the retainer ring 60 is screwed to the diaphragm fixing ring 120 with screws 170 from the bottom surface 60b side of the retainer ring 60 so that the upper surface 60a of the retaining ring 60 faces the lower surface 120b of the diaphragm fixing ring 120 (screw fixing). And fixed (clamped).
- two positioning pins (corresponding to positioning pins 182 to be described later) are provided as a measure for preventing displacement of the diaphragm fixing ring 120 and the retainer ring 60.
- the diaphragm fixing ring 120 and the retainer ring 60 have a concentric annular shape, and the lower surface 120b of the diaphragm fixing ring 120 and the upper surface 60a of the retainer ring 60 that contacts the diaphragm fixing ring 120 have the same shape.
- the upper surface 60a of the retainer ring 60 can be securely fixed to the lower surface 120b of the fixing ring 120.
- a fluid for example, gas
- Ring 60 can be pushed downward to load the polishing pad 58.
- the inner side surface (inner peripheral side surface) 60c of the retainer ring 60 and the surface 115a of the membrane 115 form a recess (recessed portion, recess) that accommodates the semiconductor wafer 1, and the retainer ring 60 is formed from the recess into the semiconductor wafer. 1 can be prevented from coming off. That is, the semiconductor wafer 1 can be mechanically polished by the retainer ring 60 while the semiconductor wafer 1 is held (supported) on the polishing head 54.
- FIG. 16 is a plan view (bottom view) of the diaphragm fixing ring 120 used in the present embodiment.
- FIG. 17 is a plan view (bottom view) showing a state in which the retainer ring 60 is attached to the diaphragm fixing ring 120 (with screws), and FIGS. 18, 19 and 20 are cross-sectional views of the main parts thereof.
- . 17 corresponds to FIG. 18, the BB line of FIG. 17 corresponds to FIG. 19, and the CC line of FIG. 17 corresponds to FIG. 16 and 17 are bottom views, and FIGS. 18 and 19 are cross-sectional views with the bottom side facing upward.
- a plurality of grooves 180 are formed on the lower surface 60b of the retainer ring 60 (the surface on the side in contact with the polishing pad 58).
- Each groove 180 is formed to connect the lower end of the inner side surface (inner peripheral side surface) 60c of the retainer ring 60 and the lower end of the outer side surface (outer peripheral side surface) 60d.
- the polishing liquid (slurry) supplied onto the polishing pad 58 is polished from the outside of the retainer ring 60 through the groove 180 of the retainer ring 60 to polish the semiconductor wafer 1 in the retainer ring 60.
- the supply to the surface can be facilitated.
- the groove 180 in the retainer ring 60 it becomes possible to supply the polishing liquid (slurry) evenly to the main surface (polishing surface) of the semiconductor wafer 1 during the CMP process. Therefore, it is possible to suppress or prevent the occurrence of uneven polishing of the semiconductor wafer.
- the polishing head 54 rotates together with the retainer ring 60 and the semiconductor wafer 1 to perform the CMP process by bringing the semiconductor wafer 1 and 1 into contact with the polishing pad 58 at a predetermined pressure.
- the lower surface 60b of the rotating retainer ring 60 rotates.
- the groove 1 80 is inclined with respect to the normal direction of the inner periphery (inner side surface 60c) or outer periphery (outer side surface 60d) of the lower surface 60b of the annular retainer ring 60 so that the polishing liquid etc. can easily pass through the groove 180 of It is formed in the direction to be.
- a screw hole (screw hole) 181 is formed in the groove 180 of the lower surface 60b of the retainer ring 60.
- the screw hole 181 is provided in a concave portion (first hole portion) 181a for accommodating the head portion 170a of the screw 170 and a bottom portion of the concave portion 181a.
- a screw hole (second hole, recess) 181b is formed in the groove 180 of the lower surface 60b of the retainer ring 60.
- the screw hole 181 is provided in a concave portion (first hole portion) 181a for accommodating the head portion 170a of the screw 170 and a bottom portion of the concave portion 181a.
- a screw hole (second hole, recess) 181b The depth D of the recess 181a of the screw hole 181 is larger than the height H of the head 170a of the screw 170 (D> H).
- the upper surface 170b of the head 170a of the screw 170 screwed with the screw hole 181 does not protrude from the force of the lower surface 60b of the cartainer ring 60! /.
- the head 170a of the screw 170 screwed in the screw hole 181 The upper surface 170a of the force retainer ring
- the lower surface 60b of the force retainer ring 60 If the force protrudes from the head 60a of the screw 170 on the polishing pad 1S
- the upper surface of the head 170a of the screw 170 screwed into the screw hole 181 is in contact with the lower surface 60b of the retainer ring 60.
- the head 170a of the screw 170 can be prevented from coming into contact with the polishing pad. Further, the depth D of the recess 181a of the screw hole 181 is deeper than the depth D of the groove 180 (D> D;).
- the screw hole 181c is also formed on the lower surface 120b (the surface on which the retainer ring 60 is attached) of the diaphragm fixing ring 120 at a position aligned with 18 lb of the screw hole of the retainer ring 60. Yes. Screw holes 181c are threaded on the side wall (screws (female threads) are formed). O Screws 170 (threads, male threads) are formed on the side wall. 60 threaded hole 181b is inserted into the diaphragm fixing ring 120 threaded hole 181c (screwed and screwed), and the retainer ring 60 is screwed to the diaphragm fixing ring 120 and fixed. is doing.
- two positioning pins 182 are provided.
- two holes (recesses) 182a for inserting the positioning pin 182 are provided in the lower surface 120b of the diaphragm fixing ring 120, and the positioning pin 182 is also inserted into the upper surface 60a of the retainer ring 60 at a position corresponding to the hole 182a.
- the hole (concave portion) 182b is provided.
- one end of the positioning pin 182 is inserted into one of the holes 182a and 182b, for example, the hole 182a of the lower surface 120b of the diaphragm fixing ring 120. Then, the other end of the positioning pin 182 inserted into the hole 182a of the diaphragm fixing ring 120 is the upper surface of the retainer ring 60 so that the other end of the positioning pin 182 is inserted into the other of the holes 182a and 182b.
- the retainer ring 60 is positioned on the diaphragm fixing ring 120 so as to be inserted into the hole 182b of the 60a. Then, the retainer ring 60 is screwed and fixed to the diaphragm fixing ring 120 with the screws 170.
- a groove 180 is formed on the lower surface 60 b of the retainer ring 60, and a screw hole 181 is formed in the groove 180. That is, a groove 180 is formed so as to pass through the recess 181a of the screw hole 181.
- liquid for example, liquid 59
- Slurry can be prevented from solidifying.
- pure water is supplied from the nozzle 57c at the platen 53c during operation, and from the load cup 52 during standby, so this pure water flows through the groove 180, and the polishing liquid (slurry) etc. at the recess 18la of the screw hole 181. Can be prevented from solidifying.
- the polishing liquid collected in the recess 181a of the screw hole 1 81 is solidified, and the solid material formed thereby Is removed from the recess 181a of the screw hole 181 during the CMP process of the semiconductor wafer. There is a possibility of adversely affecting polishing.
- the liquid passing through the groove 180 also passes through the recess 181a of the screw hole 181.
- the polishing liquid (slurry) Since the recess 181a of the screw hole 181 is always wet during the CMP process, it is possible to prevent the polishing liquid (slurry) from solidifying in the recess 181a of the screw hole 181 and the solidified polishing liquid polishes the semiconductor wafer. Can be adversely affected.
- the lower surface 120b of the diaphragm fixing ring 120 has a flatness (flatness) of 30 m or less.
- the diaphragm 113 is clamped between the diaphragm fixing ring 120 and the carrier plate 102, and the diaphragm fixing ring 120 and the carrier plate 102 are screwed from the upper surface side of the carrier plate 102. Fasten the retainer ring 60 to the diaphragm fixing ring 120 downward (the lower surface 60a side of the retainer ring 60) with the screw 170 and fix it!
- FIG. 21 is a cross-sectional view of a principal part showing a polishing head 254 of a first comparative example examined by the present inventors.
- FIG. 21 shows a region corresponding to FIG.
- the diaphragm fixing ring 120 is not used, and the diaphragm 11 3 between the annular retainer ring 260 (the retainer ring 260 of the first comparative example) that also has a grease material force and the carrier plate 102 is used.
- the outer edge is clamped.
- the retainer ring 260 is fixed to the carrier plate 102 by screwing the upper surface side force of the carrier plate 102 with screws 221.
- the other configuration is almost the same as that of the polishing head 54 of the present embodiment, and the description thereof is omitted here.
- a diaphragm 113 having elastic body force such as a rubber material is directly provided between the retainer ring 260 made of a resin material and the carrier plate 102. It is pinched and fixed. For this reason, the surface state of the retainer ring 260 may occur due to the neglected state, affecting the polishing rate of the edge portion of the semiconductor wafer, and the uniformity of the polishing amount of the semiconductor wafer may not be stable.
- the lower surface 260b force of the retainer ring 260 is deformed so as to face the outside due to the influence of the diaphragm 113, which also has an elastic body force such as rubber, and the retainer ring 260 is deformed by the pressure from the polishing pad 58 when starting CMP processing.
- the bottom surface 260b is deformed so that it faces inward.
- the surface state of the retainer ring 260 is not stable.
- the surface state of the retainer ring 260 (for example, relative to the surface of the polishing pad)
- the tilt angle of the lower surface 260b of the retainer ring 260 may fluctuate, affecting the polishing rate of the edge portion of the semiconductor wafer, and the uniformity of the polishing amount of the semiconductor wafer may not be stable. This lowers the manufacturing yield of the semiconductor device and increases the manufacturing cost of the semiconductor device.
- FIG. 22 is a cross-sectional view of a principal part showing a polishing head 354 of a second comparative example examined by the present inventors.
- FIG. 22 shows a region corresponding to FIG.
- the diaphragm fixing ring 120 is not used, and the first portion 360a made of a material having rigidity such as stainless steel and the second portion 360a bonded to the first portion 360a also has a grease material force.
- the outer edge of the diaphragm 113 is placed between the first portion 360a of the retainer ring 360 and the carrier plate 102, using an annular retainer ring 360 (second retainer ring 360 of the second comparative example) composed of a portion 360b. Clamping.
- the retainer ring 360 is fixed to the carrier plate 102 with screws 321 from the upper surface side of the carrier plate 102.
- the other configuration is almost the same as that of the polishing head 54 of the present embodiment, and the description thereof is omitted here.
- the first portion 360a having a force such as stainless steel and the second portion 360b having a resin material force are bonded together by an adhesive.
- a trapezoidal retainer ring 360 is formed, and the retainer ring 360 is screwed to the carrier plate 102.
- the retainer ring 360 is fixed by sandwiching a diaphragm 113 having an elastic force such as rubber material between the first portion 360a having a force such as stainless steel and the carrier plate 102.
- the clamp state of the diaphragm 1 13 is less likely to fluctuate.
- the surface condition of the retainer ring 360 e.g., the retainer ring 360 The inclination of the lower surface 360c of the portion 360b of 2) is less likely to fluctuate, and the uniformity of the polishing amount of the semiconductor wafer can be stabilized.
- the retainer ring 360 when the second portion 360b, which also has the grease material force of the retainer ring 360, is worn by performing the CMP process on a plurality of semiconductor wafers, the retainer ring 360 is replaced. Required force The first part 360a and the second part 360b are bonded and integrated with an adhesive material. Therefore, the retainer ring 360 made up of the first part 360a and the second part 360b It is necessary to replace the whole. Each time the retainer ring 360 is replaced, the sandwiching degree of the diaphragm 113 between the first apportioning 360a of the retainer ring 360 and the carrier plate 102 changes, which may affect the polishing rate of the edge portion of the semiconductor wafer. is there.
- the condition of the retainer ring 360 is adjusted, etc. It is necessary to adjust or check the edge polishing rate. This reduces the operating rate of the CMP device and increases the manufacturing cost of the semiconductor device.
- the second portion 360b which also has a grease material strength, wears out, it is necessary to replace the entire retainer ring 360 composed of the first portion 360a and the second portion 360b. ) Will increase the cost of manufacturing semiconductor devices.
- diaphragm fixing ring 120 is clamped between diaphragm fixing ring 120 and carrier plate 102 made of a rigid material (metal material) such as stainless steel, and diaphragm fixing ring
- the carrier plate 102 and the carrier plate 102 are fastened with screws 121 from the upper surface side of the carrier plate 102 and fixed with force.
- the retainer ring 60 made of a resin material is moved downward (retainer ring 60) to the diaphragm fixing ring 120.
- the lower surface 60a side) is fastened with screws 170 and fixed with tension.
- Retainer ring 60 made of a resin material and diaphragm fixing ring 120 are not sandwiched between diaphragm 113 and are harder than retainer ring 60 (having higher mechanical strength). Diaphragm between diaphragm fixing ring 120 and carrier plate 102 113 is clamped, and the retainer ring 60 is fixed directly on the lower surface 120b of the diaphragm fixing ring 120 with good flatness, so that the retainer ring 60 is stable and stable on the diaphragm fixing ring 120 and the carrier plate 102. Can be fixed. For this reason, the resin surface (polishing pad contact portion) of the retainer ring 60 is not deformed, and the uniformity of the polishing amount of the semiconductor wafer can be stabilized.
- the surface state of the retainer ring 60 (for example, the angle of inclination of the lower surface 60b of the retainer ring 60 with respect to the surface of the polishing pad 58) between the standby state (before the start) and the CMP process start, when the clamp state of the diaphragm 113 is difficult to change ) Does not change, and the surface state of the retainer ring 60 can be stabilized, so that the uniformity of the polishing amount of the semiconductor wafer can be stabilized even when the standby state and the start state are repeated. Thereby, the manufacturing yield of the semiconductor device can be improved and the manufacturing cost of the semiconductor device can be reduced.
- the retainer ring 60 can be removed and replaced by removing the screws 170, it is not necessary to remove the diaphragm fixing ring 120 when replacing the retainer ring 60. For this reason, even if the retainer ring 60 is replaced, the sandwiching state of the diaphragm 113 by the diaphragm fixing ring 120 and the carrier plate 102 does not change. Therefore, even if the retainer ring 60 is replaced, the surface state of the retainer ring 60 does not fluctuate. Therefore, after the retainer ring 60 is replaced, CMP processing can be started immediately, and the uniformity of the polishing amount of the semiconductor wafer can be stabilized. Can be made.
- the operating rate of the CMP apparatus can be improved and the manufacturing cost of the semiconductor device can be reduced.
- the retainer ring 60 when the retainer ring 60 is worn, it is not necessary to replace the diaphragm fixing ring 120, which is a metal part, by replacing only the retainer ring 60, which also has a grease material strength. Therefore, replacement parts (retainer ring 60) The unit price can be reduced, which can also contribute to the reduction of the manufacturing cost of the semiconductor device.
- the groove 180 is formed on the lower surface 60b of the retainer ring 60, and the screw hole 181 is formed in the groove 180. That is, the groove 180 is formed so as to pass through the recess 181a of the screw hole 181.
- the recess of the screw hole 181 The body can be easily supplied to the portion 181a and the head 170a of the screw 170, and the recess (181a) of the screw hole 181 can prevent the polishing liquid (slurry) from solidifying. As a result, the solidified polishing liquid can be prevented from adversely affecting the polishing of the semiconductor wafer. Therefore, the manufacturing yield of the semiconductor device can be improved and the manufacturing cost of the semiconductor device can be reduced.
- FIG. 23 is an explanatory view (cross-sectional view) showing a wear model of the retainer ring 60 made of a resin material cover.
- the lower surface 60b of the retainer ring 60 is also polished and worn together.
- the lower surface 60b of the ring 60 is inclined.
- the CMP process of the semiconductor wafer 1 can be performed stably (corresponding to the stable state in FIG. 23).
- the flatness H of the lower surface 60b of the retainer ring 60 is
- FIG. 24 is a cross-sectional view (descriptive view) conceptually showing a state in which the polishing liquid 190 has entered between the diaphragm fixing ring 120 and the retainer ring 60.
- Figure 25 shows the retainer ring after many semiconductor wafers are subjected to CMP.
- FIG. 6 is a plan view (descriptive drawing) showing a lower surface 120b of the diaphragm fixing ring 120 when the groove 60 is removed.
- the polishing liquid supplied onto the polishing pad 58 from the nozzle 57 advances from the outside of the retainer ring 60 to the inside of the retainer ring 60 and is held inside the retainer ring 60 on the polishing surface of the semiconductor wafer 1. 24, as shown in FIG. 24, the retainer ring 60, the diaphragm fixing ring 120, and the outer peripheral side (outer side wall 60d side) of the retainer ring 60 are arranged closer to the outer peripheral side (outer side wall 60d side). It is easy for the polishing liquid 190 to enter the gap between the two.
- FIG. 26 is a plan view (bottom view) of the retainer ring 60 used in the present embodiment, and FIG. 27 is a schematic cross-sectional view thereof.
- FIG. 26 corresponds to FIG. 17 of the above embodiment.
- the groove 180 is not shown for easy understanding.
- a plurality of grooves 180 are formed on the lower surface 60b of the retainer ring 60 (the surface that contacts the polishing pad), and the screw hole 181 is formed near the center of each groove 180.
- a plurality of grooves 180 are formed on the lower surface 60b (the surface that contacts the polishing pad) of the retainer ring 60, and the outer peripheral side (outside, outer sidewall 60d side) of the center of each groove 180.
- a screw hole 181 is formed on the diaphragm fixing ring 120 with a screw 170 at the screw hole 181.
- Other configurations are substantially the same as those in the first embodiment, and thus description thereof is omitted here.
- a plurality of grooves 180 are formed on the lower surface 60b of the retainer ring 60, and screw holes 181 are formed closer to the outer periphery than the center of each groove 180. Since the screw is fixed to the diaphragm fixing ring 120 with the screw 170 at 181, a gap is formed between the retainer ring 60 and the diaphragm fixing ring 120 on the outer peripheral side of the retaining ring 60, and the polishing liquid is generated there. Intrusion can be prevented. For this reason, The retainer ring 60 can be prevented from warping, and the replacement life of the retainer ring 60 (the life that can be treated with CMP) can be extended.
- a member for screwing the retainer ring 60 here, the lower surface 120b of the diaphragm fixing ring 120 (the surface on the side where the retainer ring 60 is attached, the surface facing the retainer ring 60) is made of silicon or the like. A surface coating can also be applied. As a result, it is possible to more reliably prevent the polishing liquid from entering between the retainer ring 60 and the diaphragm fixing ring 120, and to extend the replacement life of the retainer ring 60 (the life that can be treated by CMP).
- the present invention is effective when applied to a manufacturing technique of a semiconductor device having a step of chemically mechanically polishing a semiconductor wafer.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/014356 WO2006038259A1 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
CNA2004800436439A CN101023511A (zh) | 2004-09-30 | 2004-09-30 | 半导体器件的制造方法 |
US11/576,267 US20080076253A1 (en) | 2004-09-30 | 2004-09-30 | Adhesive Sheet,Semiconductor Device,and Process for Producing Semiconductor Device |
JP2006539090A JPWO2006038259A1 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/014356 WO2006038259A1 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
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WO2006038259A1 true WO2006038259A1 (ja) | 2006-04-13 |
Family
ID=36142350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/014356 WO2006038259A1 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20080076253A1 (ja) |
JP (1) | JPWO2006038259A1 (ja) |
CN (1) | CN101023511A (ja) |
WO (1) | WO2006038259A1 (ja) |
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JP2008147646A (ja) * | 2006-11-22 | 2008-06-26 | Applied Materials Inc | 保持リング及びキャリアリングを持つキャリアヘッド |
US8469776B2 (en) | 2006-11-22 | 2013-06-25 | Applied Materials, Inc. | Flexible membrane for carrier head |
WO2014185003A1 (ja) * | 2013-05-16 | 2014-11-20 | 信越半導体株式会社 | ワークの研磨装置 |
JP2016043473A (ja) * | 2014-08-26 | 2016-04-04 | 株式会社荏原製作所 | バフ処理モジュール、及び、処理装置 |
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US8469776B2 (en) | 2006-11-22 | 2013-06-25 | Applied Materials, Inc. | Flexible membrane for carrier head |
WO2014185003A1 (ja) * | 2013-05-16 | 2014-11-20 | 信越半導体株式会社 | ワークの研磨装置 |
JP2014223692A (ja) * | 2013-05-16 | 2014-12-04 | 信越半導体株式会社 | ワークの研磨装置 |
JP2016043473A (ja) * | 2014-08-26 | 2016-04-04 | 株式会社荏原製作所 | バフ処理モジュール、及び、処理装置 |
WO2019187814A1 (ja) * | 2018-03-27 | 2019-10-03 | 株式会社荏原製作所 | 基板保持装置およびドライブリングの製造方法 |
JP2019171492A (ja) * | 2018-03-27 | 2019-10-10 | 株式会社荏原製作所 | 基板保持装置およびドライブリングの製造方法 |
JP7219009B2 (ja) | 2018-03-27 | 2023-02-07 | 株式会社荏原製作所 | 基板保持装置およびドライブリングの製造方法 |
KR20230133402A (ko) * | 2021-03-17 | 2023-09-19 | 미크로 기켄 가부시키가이샤 | 연마 헤드 및 연마 처리 장치 |
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Also Published As
Publication number | Publication date |
---|---|
JPWO2006038259A1 (ja) | 2008-07-31 |
CN101023511A (zh) | 2007-08-22 |
US20080076253A1 (en) | 2008-03-27 |
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