WO2006033357A1 - 試験シミュレータ、試験シミュレーションプログラム、及び記録媒体 - Google Patents
試験シミュレータ、試験シミュレーションプログラム、及び記録媒体 Download PDFInfo
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- WO2006033357A1 WO2006033357A1 PCT/JP2005/017396 JP2005017396W WO2006033357A1 WO 2006033357 A1 WO2006033357 A1 WO 2006033357A1 JP 2005017396 W JP2005017396 W JP 2005017396W WO 2006033357 A1 WO2006033357 A1 WO 2006033357A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
- G01R31/318357—Simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Definitions
- Test simulator test simulator program, test simulation program, and recording medium
- the present invention relates to a test simulator, a test simulation program, and a recording medium.
- the present invention relates to a test simulator for simulating a test of a semiconductor device, a test simulation program, and a recording medium.
- HDL hardware description language
- Verilog—HDL or VHDL a computer in hardware description language
- Verilog—HDL / VHDL simulator a device simulator
- Verification is made as to whether or not the intended function is fulfilled.
- a technique for verifying the design of a semiconductor device by simulating a semiconductor device test by a semiconductor test apparatus using a simulator based on HDL is disclosed (for example, see Patent Document 1).
- Patent Document 1 JP 2002-215712 A
- the operation speed of the semiconductor device simulated by the device simulator is very slow compared with the operation speed of the actual semiconductor device. Therefore, a test of a semiconductor device simulated using a device simulator requires a much longer time than a test using an actual semiconductor test apparatus and a semiconductor device. For this reason, automation in semiconductor device design is performed with sufficiently high efficiency. There was a long-awaited test simulator that more efficiently simulates the test.
- an object of the present invention is to provide a test simulator, a test simulation program, and a recording medium that can solve the above-described problems.
- This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- a first embodiment of the present invention is a test simulator for simulating a test of a semiconductor device, and holds an existing test pattern to be given to the semiconductor device Generates test pattern holding means, device output holding means for holding in advance the output to be obtained from the semiconductor device when the existing test pattern is given to the semiconductor device, and a new test pattern to be given to the semiconductor device.
- the test pattern generation means the test pattern judgment means for judging whether the new test pattern is the same as the existing test pattern, and the new test pattern are the same as the existing test pattern
- the device output holding means force output without giving a new test pattern to the semiconductor device By the output of the semiconductor device force against the pattern, and a simulation skipping means for skipping at least a portion of the simulation test.
- the test simulator gives a new test pattern to the device simulation means for simulating the operation of the semiconductor device and performs device simulation.
- Device output generation means for generating an output from the semiconductor device by operating the device means may be further provided.
- the test simulator may further include device simulation means.
- the test pattern holding means has a test pattern storing means for storing a new test pattern generated by the test pattern generating means, and the device output holding means is generated by the device simulating means according to the new test pattern. You may have device output storage means to store the output of semiconductor device power!
- the test pattern holding means further holds the value of the internal register of the semiconductor device when starting to give an existing test pattern.
- the value of the internal register of the semiconductor device is the same as the value of the internal register held in the test pattern holding means. You may skip.
- the test pattern holding means has a start register value storing means for receiving and storing the value of the internal register of the semiconductor device when starting to give a new test pattern to the device simulating means. May be.
- the test pattern holding means holds a plurality of combinations of the value of the internal register of the semiconductor device and the existing test pattern when starting to give the existing test pattern to the device simulating means.
- the output holding means holds the output from which the semiconductor device power should be obtained when the existing test pattern is given in association with each of a plurality of existing test patterns. Combining force between the internal register value of the semiconductor device and the new test pattern at the start of giving the test pattern When the combination held in the test pattern holding means is the same as at least one of the simulation tests Part may be skipped
- the end register value holding means for holding the value of the internal register of the semiconductor device after the application of the existing test pattern and the simulation skip means.
- a register value setting means for setting the value of the internal register held by the end register value holding means in the internal register of the semiconductor device in the case where the end register value holding means is set, and the test pattern generation means is skipped by the simulation skip means.
- a new test pattern may be generated to resume the simulated simulation.
- the end register value holding means receives and stores the value of the internal register of the semiconductor device after the new test pattern has been given to the device simulation means. You may have.
- a test simulation program for causing a computer to function as a test simulator for simulating a test of a semiconductor device, which retains an existing test pattern to be given to the semiconductor device Test pattern retention Means, device output holding means for holding in advance the output to be obtained from the semiconductor device when an existing test pattern is given to the semiconductor device, and test pattern generation for generating a new test pattern to be given to the semiconductor device And a test pattern judging means for judging whether the new test pattern is the same as the existing test pattern, and a semiconductor device when the new test pattern is the same as the existing test pattern.
- Device skipping at least part of the simulation test by reading the device output holding means force output without giving a new test pattern to the device and using it as the output from the semiconductor device for the new test pattern
- the computer functions as a test simulator comprising means.
- the test simulator gives a new test pattern to the device simulation means for simulating the operation of the semiconductor device, and the device simulation means
- the device may further include device output generation means for generating an output of the semiconductor device force by operating
- the test simulator may further include device simulation means.
- the test pattern holding means has a test pattern storage means for storing a new test pattern generated by the test pattern generation means, and the device output holding means is generated by the device simulation means according to the new test pattern.
- the test pattern holding means further holds the value of the internal register of the semiconductor device when starting to give an existing test pattern, and the simulation skip means when starting to give a new test pattern to the semiconductor device. Further, at least a part of the simulation test may be skipped on condition that the value of the internal register of the semiconductor device is the same as the value of the internal register held in the test pattern holding means.
- the test pattern holding means has a start register value storing means for receiving and storing the value of the internal register of the semiconductor device when starting to give a new test pattern to the device simulating means. May be.
- the test pattern holding means is a combination of the value of the internal register of the semiconductor device and the existing test pattern when starting to give the existing test pattern to the device simulation means.
- the device output holding means holds the output from which the semiconductor device power should be obtained when the existing test pattern is given in association with each of the plurality of existing test patterns.
- the simulation skip means is the same as any of the combinations held in the test pattern holding means when the new register is used for the value of the internal register of the semiconductor device when starting to give a new test pattern. If at least part of the simulation test may be skipped
- the test simulator skips at least a part of the simulation test by the end register value holding means for holding the value of the internal register of the semiconductor device after the application of the existing test pattern and the simulation skip means.
- Register value setting means for setting the internal register value held by the end register value holding means in the case of the internal register of the semiconductor device, and the test pattern generation means is configured by the simulation skip means.
- a new test pattern may be generated to restart the skipped simulation test.
- the end register value holding means has end register value storage means for receiving and storing the value of the internal register of the semiconductor device after the new test pattern has been given to the device simulation means. Hey.
- a recording medium in which the test simulation program is recorded is provided.
- FIG. 1 is a block diagram showing an example of a functional configuration of a test simulation system 10 according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an example of a test pattern database 316 according to the embodiment of the present invention.
- FIG. 3 is a diagram showing an example of a device output database 344 according to the embodiment of the present invention.
- FIG. 4 is a diagram showing an example of an end register value database 364 according to the embodiment of the present invention.
- FIG. 5 is a flowchart showing an example of a process flow in the test simulator 30 according to the embodiment of the present invention.
- FIG. 6 is a block diagram showing an example of a hardware configuration of a computer 1500 according to the embodiment of the present invention.
- test simulation system 20 test simulator control means, 30 test simulator, 40 device simulation means, 300 test pattern generation means, 310 test pattern holding means, 312 test pattern storage means, 314 start register value storage means 31 6 Test pattern database, 320 Test pattern judgment means, 330 Device output generation means, 340 Device output holding means, 342 Device output storage means, 344 Device output database, 350 Simulation skip means, 360 End register value holding means, 362 end register value storage means, 364 end register value database, 370 register value setting means, 380 expected value holding means, 390 logic comparison means
- FIG. 1 is a block diagram showing an example of a functional configuration of a test simulation system 10 according to the embodiment of the present invention.
- the test simulation system 10 includes a test simulator control means 20, a test simulator 30, and a device simulation means 40.
- the test simulation system 10 uses a semiconductor test apparatus to test the semiconductor device, and instead of judging whether the semiconductor device is good or bad, The quality of the semiconductor device is determined by simulating the test of the semiconductor device using the test simulator 30 that simulates the semiconductor device and the device simulation means 40 that simulates the semiconductor device by software. .
- the test simulation system 10 in this example gives a test pattern to the semiconductor device, and compares the output signal output from the semiconductor device force in accordance with the test pattern with an expected value, thereby determining the quality of the semiconductor device. List the function tests to be judged.
- the test simulator 30 provides a device simulation if the test pattern force applied to the device simulation means 40 is the same as an existing test pattern such as a test pattern used before. The purpose of this is to reduce the time required for the simulation test by skipping the process of generating the output of the semiconductor device in the test means 40.
- the test simulator control means 20 controls the test simulator 30 to cause the device simulation means 40 to execute a simulation test.
- the test simulator control means 20 includes the procedure and method of the test to be performed on the semiconductor device created by the user corresponding to the semiconductor device whose operation is simulated by the device simulation means 40.
- the test simulator 30 may be controlled based on the written test program.
- the test program includes, for example, a test pattern supplied to the device simulation means 40 and the device simulation means 40 when the test simulator 30 performs a simulated function test on the device simulation means 40. Including the expected value of the output of the semiconductor device generated according to the test pattern and timing information indicating the timing for comparing the output with the expected value.
- test simulator 30 simulates the test of the semiconductor device by performing a simulated test on the device simulation means 40 that simulates the operation of the semiconductor device.
- Test simulator 30 includes test pattern generation means 300, test pattern holding means 310, test pattern judgment means 320, device output generation means 330, device output holding means, simulation skip means, end register value holding means 360, register value setting. Means 370, expected value holding means 380, and logic comparison means 390 are provided. Book In the configuration shown in the figure, the test simulator 30 does not include the device simulation means 40, but in other configurations, the test simulator 30 may include the device simulator 40.
- the test pattern generation means 300 Based on the control of the test simulator control means 20, the test pattern generation means 300 generates a new test pattern to be given to the semiconductor device simulated by the device simulation means 40, and generates the generated test pattern. Output to the test pattern holding means 310 and the test pattern judgment means 320.
- the test pattern holding unit 310 includes a test pattern storage unit 312, a start register value storage unit 314, and a test pattern database 316.
- the test pattern storage unit 312 stores the new test pattern generated by the test pattern generation unit 300 in the test pattern database 316.
- the start register value storage means 314 stores the value of the internal register of the semiconductor device simulated by the device simulation means 40 when starting to give a new test pattern to the device simulation means 40.
- the test pattern database 316 holds existing test patterns to be applied to the semiconductor device simulated by the device simulation means 40.
- the existing test pattern may be, for example, a test pattern previously applied to a semiconductor device simulated by the device simulating means 40, or a predetermined test pattern such as a typical test pattern. It may be a test pattern.
- the test pattern database 316 holds the value of the internal register of the semiconductor device when starting to give the existing test pattern being held.
- the test pattern determination unit 320 determines whether or not the new test pattern force received from the test pattern generation unit 300 is the same as the existing test pattern held in the test pattern database 316.
- the test pattern judging means 320 receives the value of the internal register of the semiconductor device simulated by the device simulating means 40 when starting to give a new test pattern from the device simulating means 40 and receives it. Further, it is possible to further determine whether or not the value of the internal register is the same as the value of the internal register held in the test pattern database 316 when the existing test pattern is given. In this case, the test pattern judging means 320 is a new test pattern.
- the test pattern determination unit 320 outputs the determination result to the device output generation unit 330, the simulation skip unit 350, and the register value setting unit 370, and determines that the new test pattern is not the same as the existing test pattern.
- the new test pattern received from the test pattern generation means 300 is further output to the device output generation means 330.
- the device output generation means 330 when the test pattern determination means 320 determines that the new test pattern force generated by the test pattern generation means 300 is not the same as the existing test pattern held in the test pattern database 316, The device simulation means 40 for simulating the operation of the semiconductor device is given the new test pattern received from the test pattern judgment means 320, and the device simulation means 40 is operated to operate the semiconductor device power. To produce output.
- the device output generation means 330 receives the output of the semiconductor device generated by the device simulation means 40 and outputs the received output to the device output holding means 340. Further, the device output generation means 330 acquires the value of the internal register of the semiconductor device when starting to give a new test pattern to the device simulation means 40 from the device simulation means 40.
- the device output generation means 330 outputs the acquired internal register value to the start register value storage means 314 and stores it in the test pattern database 316. Further, the device output generation means 330 outputs the acquired internal register value to the test pattern determination means 320, and the internal register value when starting to give an existing test pattern held in the test pattern database 316. To determine whether or not the force is the same. Further, the device output generating means 330 finishes giving a new test pattern to the device simulating means 40 and generates the output of the semiconductor device, and then the value of the internal register of the semiconductor device is calculated as the device simulating means. Get from 40. Then, the device output generation unit 330 outputs the acquired internal register value to the end register value holding unit 360.
- the device output holding unit 340 outputs the output of the semiconductor device generated by the device simulation unit 40 received from the device output generation unit 330 to the simulation skip unit 350.
- the device output holding means 340 includes a device output storage means 342 and a device output database 344.
- the device output storage means 342 receives the output from the semiconductor device generated by the device simulation means 40 according to the new test pattern generated by the test pattern generation means 300 from the device output generation means 330 and receives the device output. Store in database 344.
- the device output data base 344 holds in advance the output to be obtained by the semiconductor device force when an existing test pattern is given to the semiconductor device simulated by the device simulating means 40.
- the device output database 344 may hold predetermined outputs such as outputs according to typical test patterns in addition to the outputs stored by the device output storage means 342. .
- the simulation skip means 350 uses a new test pattern force generated by the test pattern generation means 300 as a test pattern to determine whether or not the test pattern database 316 has the same force as the existing test pattern. Receive from decision means 320. The simulation skip means 350 outputs the output of the semiconductor device corresponding to the new test pattern generated by the device simulation means 40 when the new test pattern force is not the same as the existing test pattern. Receive from device output holding means 340 and output to logic comparison means 390. On the other hand, the simulation skip unit 350 does not give the new test pattern to the semiconductor device simulated by the device simulation means 40 when the new test pattern is the same as the existing test pattern.
- the output from which the semiconductor device power should also be obtained is read from the device output database 344 and used as an output from the semiconductor device for the new test pattern. Skip at least some of the simulation tests. Then, when skipping at least a part of the simulation test, the simulation skip means 350 outputs the output of the semiconductor device corresponding to the existing test pattern read from the device output database 344 to the logical comparison means 390. Output. Simulation skip Means 350 determines the value of the internal register of the semiconductor device when starting to give a new test pattern to the semiconductor device. When received from the test pattern judging means 320, at least a part of the simulation test may be skipped on condition that the values of the internal registers are the same.
- the end register value holding unit 360 includes an end register value storage unit 362 and an end register value database 364.
- the end register value storage means 362 provides the device output generation means with the value of the internal register of the semiconductor device simulated by the device simulation means 40 after the new test pattern has been given to the device simulation means 40.
- the end register value database 364 holds the values of the internal registers of the semiconductor device simulated by the device simulation means 40 after the existing test pattern is given.
- the register value setting means 370 is determined by the test pattern determination means 320 that the new test pattern generated by the test pattern generation means 300 and the existing test pattern held in the test pattern database 316 are the same.
- the end register value database 364 holds the internal register of the semiconductor device after giving the existing test pattern. Read the value of.
- the register value setting unit 370 sets the read internal register value in the internal register of the semiconductor device simulated by the device simulation unit 40.
- the test pattern generation means 300 generates a new test pattern for restarting the simulation test skipped by the simulation skip means 350.
- the expected value holding unit 380 includes an expected value of the output of the semiconductor device generated by the device simulating unit 40 in accordance with the new test pattern generated by the test pattern generating unit 300, and the output and the expected value.
- the timing information indicating the timing for comparing is received from the test simulator control means 20 and held.
- the logic comparison unit 390 outputs the output of the semiconductor device generated by the device simulation unit 40 according to the new test pattern generated by the test pattern generation unit 300 or the new test pattern.
- the output read from the device output database 344 corresponding to the same existing test pattern is received from the simulation skip means 350.
- the logical comparison means 390 holds the output of the semiconductor device received from the simulation skip means 350 by the expected value holding means 380. Whether the semiconductor device simulated by the device simulating means 40 is good or bad is determined based on whether the force matches the expected value, and the determination result is output to the test simulator control means 20.
- a new test pattern to be given to the device simulating means 40 is an existing test pattern such as a previously given test pattern or a typical test pattern. If it is the same as the test pattern, the existing test stored in the device output database 344 in advance without causing the device simulating means 40 to generate the output of the semiconductor device based on the new test pattern.
- the output for the test pattern can be compared with the expected value as the output for the new test pattern. As a result, for example, when changing the expected value to be compared with the output of the semiconductor device, the timing to compare the output with the expected value, etc.
- the time required for the simulation test can be shortened by skipping at least a part of the time-consuming process in which the device simulation means 40 generates the output of the semiconductor device.
- the device simulation means 40 can actually be operated to generate the output of the semiconductor device. Regardless of the contents of the pattern, the time required for the simulation test can be reduced as much as possible.
- the semiconductor when the respective test patterns start to be given to the device simulation unit 40 You can skip at least some of the simulation tests only if the condition that the device internal register values are identical is met. As a result, the device simulation means 40 has the same test pattern. Even when the value of the internal register is not the same, it is possible to accurately determine whether or not the simulation test should be skipped even if a different output is generated.
- the device simulation means 40 does not operate based on the new test pattern.
- the internal register of the semiconductor device simulated by the device simulating means 40 does not change. In other words, in many cases, the value of the internal register is different when the simulation test is skipped and when it is not skipped. In this case, after skipping the simulation test, the simulation test cannot be resumed using the next new test pattern. For this reason, for example, immediately after initializing the internal register, such as the entire test sequence, the simulation test is skipped except for a very long period, such as the period from when the internal register is next initialized. Can't effectively reduce the time required for simulation testing.
- the test simulator 30 when it is determined that the new test pattern is the same as the existing test pattern and the simulation test is skipped, the value of the internal register of the semiconductor device can be read from the end register value data base 364 and set in the device simulation means 40. Therefore, the value of the internal register can be made the same when the simulation test is skipped and when it is not skipped, so that the simulation test can be resumed after skipping. As a result, the period during which the simulation test can be skipped, that is, the length of the test pattern when judging whether or not the new test pattern and the existing test pattern are the same, can be made shorter. Therefore, in many cases, the simulation test can be skipped. That is, according to the test simulator 30, the time required for the test simulation can be efficiently reduced.
- FIG. 2 shows an example of the test pattern database 316 according to the embodiment of the present invention.
- the test pattern database 316 stores the existing test pattern and the internal register of the semiconductor device when the existing test pattern starts to be given to the device simulation means 40. Holds multiple combinations with the value of.
- the test pattern database 316 has a different index for each existing test pattern, the existing test pattern, and the internal register of the semiconductor device when the existing test pattern starts to be given to the device simulation means 40.
- a value may be stored in association with each other.
- the index may be generated as a unique value for the new test pattern.
- Each of the existing test patterns may include, for example, a plurality of combinations of event types such as signal rising and falling and the timing of occurrence of the event.
- the event occurrence timing may be, for example, the elapsed time of the force at the start of the test cycle in the semiconductor device test, or may be the elapsed time of the force at the occurrence of the immediately preceding event.
- the internal register values include the values of multiple internal registers! /, Teyo! /, Etc.
- FIG. 3 shows an example of the device output database 344 according to the embodiment of the present invention.
- the device output database 344 stores the output to be obtained by associating each of a plurality of existing test patterns with the semiconductor device force simulated by the device simulation means 40 when the existing test pattern is given. is doing.
- the device output database 344 may hold an index that differs for each existing test pattern and an output from the device simulating means 40 when the existing test pattern is given.
- the index is generated as a unique value by the new test pattern as shown in FIG. It may be the same as the index in the test pattern database 316.
- FIG. 4 shows an example of the end register value database 364 according to the embodiment of the present invention.
- the end register value database 364 corresponds to each of the plurality of existing test patterns, and after the application of the existing test pattern, the value of the internal register of the semiconductor device simulated by the device simulation means 40 is stored. Holding.
- the end register value database 364 holds an index that is different for each existing test pattern and an internal register value when the existing test pattern is given in association with each other. It's okay.
- the index is generated as a unique value for the new test pattern. It may be the same as the index in database 316.
- the value of the internal register may include the value of each of the plurality of internal registers.
- the existing test pattern, the value of the internal register when starting to provide the existing test pattern, and the existing test pattern are provided.
- a plurality of combinations of the output of the semiconductor device and the value of the internal register when the existing test pattern is given can be held.
- FIG. 5 is a flowchart showing an example of a process flow in the test simulator 30 according to the embodiment of the present invention.
- the test pattern generation means 300 generates a new test pattern to be given to the semiconductor device simulated by the device simulation means 40 (S1000).
- the device output generation means 330 acquires the value of the internal register of the semiconductor device simulated by the device simulation means 40 from the device simulation means 40 (S1010).
- the test pattern judging means 320 is a semiconductor device which is simulated by the device simulating means 40 when starting to give a new test pattern generated by the test pattern generating means 300 and the new test pattern.
- the test pattern determination unit 320 determines that the combination is the same as any of the above-described combinations in each of the plurality of existing test patterns held in the test pattern database 316. If it is determined (S1020: Yes), the simulation skip means 350 performs device simulation. When the existing test pattern is given to the semiconductor device without giving the new test pattern to the semiconductor device simulated by means 40, an output that should also obtain a semiconductor device force is output to the device. At least a part of the simulation test is skipped by reading from the database 344 and outputting the semiconductor device power for the new test pattern (S1030).
- the register value setting unit 370 simulates the device simulation unit 40 after providing the device test unit 40 with the existing test pattern determined to be the same as the new test pattern.
- the value of the internal register of the semiconductor device to be read is read from the end register value database 364 and set in the internal register of the semiconductor device (S1040).
- the test pattern determination unit 320 determines that none of the above-described combinations in each of the plurality of existing test patterns held in the test pattern database 316 is the same.
- the device output generation means 330 gives a new test pattern to the device simulation means 40 and operates the device simulation means 40, thereby operating the semiconductor device power.
- a thing output is generated (S1050).
- the device output storage means 342 stores the output of the semiconductor device generated by the device simulation means 40 in accordance with the new test pattern in the device output database 344 (S1060).
- the test pattern holding means 310 receives the new test pattern and the semiconductor device simulated by the device simulation means 40 when the new test pattern starts to be given to the device simulation means 40.
- the value of the internal register is stored in the test pattern database 316 (S1070).
- the end register value storage means 362 gives the value of the internal register of the semiconductor device simulated by the device simulation means 40 after giving a new test pattern to the device simulation means 40.
- the logic comparison unit 390 outputs the output corresponding to the existing test pattern read from the device output database 344, and If the simulation test is not skipped, the device output generation means 330 By comparing the output generated to 0 with the expected value, the device simulation means 40 determines the quality of the semiconductor device to be simulated (S 1090). Note that the test simulator 30 may repeat the above processing as necessary.
- the existing test pattern and the existing test If the combination with the value of the internal register at the start of giving a pattern is not the same, the new test pattern, the value of the internal register at the start of giving the new test pattern, and the new test pattern
- the combination of the output of the semiconductor device generated accordingly and the value of the internal register after the output of the semiconductor device is generated can be stored as one of the combinations in the existing test pattern.
- the simulation test for the test pattern can be skipped. In other words, even if the above-described combination in the test pattern is not held in advance, the simulation test can be skipped more efficiently and the time required for the simulation test can be shortened as the simulation test is executed.
- the test pattern judging means 320 judges whether the value of the internal register at the start of giving a new test pattern is the same, the device simulating means 40 is not necessarily used.
- the same output is obtained by giving the same test pattern in the test simulated by the test simulator 30 that does not need to determine whether all the registers in the semiconductor device to be simulated are the same.
- the type of internal register power that should be matched the test simulator 30 combines the new test pattern with the value of the internal register when the new test pattern starts to be given, and the internal register when the existing test pattern and the existing test pattern start to give. After the simulation test is skipped and the new test pattern matches the existing test pattern, the value of the internal register when starting to give the test pattern is determined.
- Simulation tests may be skipped without determining whether or not are identical to each other. Further, the test simulator 30 determines that the combination of the test pattern and the value of the internal register at the start of giving the test pattern is the same, and skips the simulation test. If the test pattern and the existing test pattern further match, it is not necessary to set the value of the internal register after the output of the semiconductor device is generated.
- FIG. 6 is a block diagram showing an example of a hardware configuration of the computer 1500 according to the embodiment of the present invention.
- a computer 1500 according to an embodiment of the present invention includes a CPU peripheral unit having a CPU 1505, a RAM 1520, a graphic controller 1575, and a display device 1580 connected to each other by a host controller 1582, and an input / output controller.
- 1584 Host / Communication interface 1530 connected to controller 1582, hard disk drive 1540, input / output unit with CD-ROM drive 1560, and input / output controller 1584 connected ROM 1510, flexible disk 'drive 1550 and a legacy input / output unit having an input / output chip 1570.
- the host controller 1582 connects the RAM 1520 to the CPU 1505 and the graphics controller 1575 that access the RAM 1520 at a high transfer rate.
- the CPU 1505 operates based on the programs stored in the ROM 1510 and the RAM 1520 and controls each part.
- the graphic 'controller 1575 acquires image data generated on the frame buffer provided by the CPU 1505 and the like in the RAM 1520 and displays it on the display device 1580.
- the graphic controller 1575 may include a frame notifier for storing image data generated by the CPU 1505 or the like.
- the input / output controller 1584 connects the host controller 1582 to the communication interface 1530, the hard disk drive 1540, and the CD-ROM drive 1560, which are relatively high-speed input / output devices.
- the communication interface 1530 communicates with other devices via a network.
- the hard disk drive 1540 stores programs and data used by the CPU 1505 in the computer 1500.
- CD-ROM drive 1560 reads CD-ROM 15 95 programs or data and provides them to hard disk drive 1540 via RAM 1520.
- I / O controller 1584, ROM1510, flexible disk 'drive 1550 and the relatively low-speed input / output device of the input / output chip 1570 are connected.
- the ROM 1510 stores a boot program executed when the computer 1500 is started up, a program depending on the hardware of the computer 1500, and the like.
- the flexible disk drive 1550 reads a program or data from the flexible disk 1590 and provides it to the hard disk drive 1540 via the RA M1520.
- the input / output chip 1570 connects various input / output devices via a flexible disk 'drive 1550' and, for example, a parallel 'port, a serial' port, a keyboard 'port, a mouse' port, and the like.
- the test simulation program provided to the hard disk drive 1540 via the RAM 1520 is stored in a recording medium such as a flexible disk 1590, a CD-ROM 1595, or an IC card and provided by the user.
- the test simulation program is read from the recording medium, installed in the hard disk drive 1540 in the computer 1500 via the RAM 1520, and executed by the CPU 1505.
- the test simulation program installed and executed on the computer 1500 works on the CPU 1505 or the like to cause the computer 1500 to function as the test simulator 30 described with reference to FIGS.
- the programs described above may be stored in an external recording medium.
- recording media flexible disk 1590, CD-ROM 1595, optical recording media such as DVD and PD, magneto-optical recording media such as MD, tape media, semiconductor memory such as IC cards, etc.
- a storage device such as a node disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 1500 via the network.
- a device simulation having an operation speed slower than that of an actual semiconductor device.
- simulating a semiconductor device test using a modulator it is possible to provide a test simulator that efficiently simulates the test and reduces the time required for the simulation test.
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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CN2005800322729A CN101027566B (zh) | 2004-09-24 | 2005-09-21 | 测试模拟器及测试模拟方法 |
EP05785167A EP1801603B1 (en) | 2004-09-24 | 2005-09-21 | Test simulator, test simulation program and recording medium |
DE602005020168T DE602005020168D1 (de) | 2004-09-24 | 2005-09-21 | Testsimulator, testsimulationsprogramm und aufzeichnungsmedium |
US11/240,811 US7502724B2 (en) | 2004-09-24 | 2005-09-30 | Test simulator, test simulation program and recording medium |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-278582 | 2004-09-24 | ||
JP2004278582A JP4580722B2 (ja) | 2004-09-24 | 2004-09-24 | 試験シミュレータ及び試験シミュレーションプログラム |
Related Child Applications (1)
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US11/240,811 Continuation US7502724B2 (en) | 2004-09-24 | 2005-09-30 | Test simulator, test simulation program and recording medium |
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WO2006033357A1 true WO2006033357A1 (ja) | 2006-03-30 |
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PCT/JP2005/017396 WO2006033357A1 (ja) | 2004-09-24 | 2005-09-21 | 試験シミュレータ、試験シミュレーションプログラム、及び記録媒体 |
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US (1) | US7502724B2 (ja) |
EP (1) | EP1801603B1 (ja) |
JP (1) | JP4580722B2 (ja) |
KR (1) | KR20070065884A (ja) |
CN (1) | CN101027566B (ja) |
DE (1) | DE602005020168D1 (ja) |
TW (1) | TWI353515B (ja) |
WO (1) | WO2006033357A1 (ja) |
Families Citing this family (8)
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JP4684183B2 (ja) * | 2006-08-09 | 2011-05-18 | 株式会社日立ハイテクエンジニアリングサービス | 半導体試験装置のテストプログラム生成システム |
US8037357B2 (en) * | 2009-03-24 | 2011-10-11 | Visa U.S.A. Inc. | System and method for generating test job control language files |
KR20110003182A (ko) | 2009-07-03 | 2011-01-11 | 삼성전자주식회사 | 인쇄 회로 기판 설계 방법 및 인쇄 회로 기판을 포함하는 패키지 테스트 디바이스 |
US9404743B2 (en) * | 2012-11-01 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for validating measurement data |
US10539609B2 (en) | 2014-12-08 | 2020-01-21 | Nxp Usa, Inc. | Method of converting high-level test specification language to low-level test implementation language |
US10755014B2 (en) * | 2018-03-14 | 2020-08-25 | Montana Systems Inc. | Event-driven design simulation |
TWI700584B (zh) * | 2018-07-06 | 2020-08-01 | 華邦電子股份有限公司 | 測試系統及適應性測試程式產生方法 |
CN112069015B (zh) * | 2020-11-10 | 2021-02-23 | 鹏城实验室 | 指令模拟器指令执行方法、装置、终端设备以及存储介质 |
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JPH0769392B2 (ja) * | 1987-03-20 | 1995-07-31 | 富士通株式会社 | 論理回路の故障箇所推定方法 |
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JP3247937B2 (ja) * | 1992-09-24 | 2002-01-21 | 株式会社日立製作所 | 論理集積回路 |
US5913022A (en) * | 1995-08-31 | 1999-06-15 | Schlumberger Technologies, Inc. | Loading hardware pattern memory in automatic test equipment for testing circuits |
US6167545A (en) * | 1998-03-19 | 2000-12-26 | Xilinx, Inc. | Self-adaptive test program |
US6249891B1 (en) * | 1998-07-02 | 2001-06-19 | Advantest Corp. | High speed test pattern evaluation apparatus |
US6308292B1 (en) * | 1998-12-08 | 2001-10-23 | Lsi Logic Corporation | File driven mask insertion for automatic test equipment test pattern generation |
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US6973633B2 (en) * | 2002-07-24 | 2005-12-06 | George Lippincott | Caching of lithography and etch simulation results |
CN1318965C (zh) * | 2002-09-10 | 2007-05-30 | 华邦电子股份有限公司 | 测试式样产生方法与其装置 |
JP3833982B2 (ja) * | 2002-10-03 | 2006-10-18 | 株式会社東芝 | テストパターン選択装置、テストパターン選択方法、及びテストパターン選択プログラム |
-
2004
- 2004-09-24 JP JP2004278582A patent/JP4580722B2/ja not_active Expired - Fee Related
-
2005
- 2005-09-21 WO PCT/JP2005/017396 patent/WO2006033357A1/ja active Application Filing
- 2005-09-21 KR KR1020077008599A patent/KR20070065884A/ko not_active Application Discontinuation
- 2005-09-21 CN CN2005800322729A patent/CN101027566B/zh active Active
- 2005-09-21 EP EP05785167A patent/EP1801603B1/en not_active Expired - Fee Related
- 2005-09-21 DE DE602005020168T patent/DE602005020168D1/de active Active
- 2005-09-23 TW TW094133063A patent/TWI353515B/zh not_active IP Right Cessation
- 2005-09-30 US US11/240,811 patent/US7502724B2/en not_active Expired - Fee Related
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JPH0361871A (ja) * | 1989-07-31 | 1991-03-18 | Hitachi Ltd | シミュレーシヨン処理装置 |
JP2003315419A (ja) * | 2002-04-24 | 2003-11-06 | Ando Electric Co Ltd | シミュレート領域範囲設定機能を有するマイクロプログラムシミュレータ |
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Also Published As
Publication number | Publication date |
---|---|
TWI353515B (en) | 2011-12-01 |
EP1801603A1 (en) | 2007-06-27 |
CN101027566B (zh) | 2010-10-27 |
KR20070065884A (ko) | 2007-06-25 |
DE602005020168D1 (de) | 2010-05-06 |
US20060085682A1 (en) | 2006-04-20 |
EP1801603B1 (en) | 2010-03-24 |
JP2006090905A (ja) | 2006-04-06 |
US7502724B2 (en) | 2009-03-10 |
EP1801603A4 (en) | 2008-07-23 |
TW200611118A (en) | 2006-04-01 |
CN101027566A (zh) | 2007-08-29 |
JP4580722B2 (ja) | 2010-11-17 |
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