WO2006019073A1 - 情報再生装置 - Google Patents
情報再生装置 Download PDFInfo
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- WO2006019073A1 WO2006019073A1 PCT/JP2005/014907 JP2005014907W WO2006019073A1 WO 2006019073 A1 WO2006019073 A1 WO 2006019073A1 JP 2005014907 W JP2005014907 W JP 2005014907W WO 2006019073 A1 WO2006019073 A1 WO 2006019073A1
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- information
- clock
- timing
- expected value
- reproducing apparatus
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
- G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
- G11B20/10166—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom partial response PR(3,4,4,3)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
- G11B2020/1863—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information wherein the Viterbi algorithm is used for decoding the error correcting code
Definitions
- the present invention relates to an information reproducing apparatus, and more particularly to an information reproducing apparatus that reproduces data and timing from an analog signal having data information and timing information.
- an information reproducing device for example, a read channel LSI core
- an analog signal for example, an output signal of an optical pickup of a DVD
- non-patent literature 1 and Patent Document 1 non-patent literature 1 and Patent Document 1 and the like.
- an analog signal read from an information recording medium is digitally input by a clock that is not necessarily synchronized with the timing included in the analog signal, and then interpolated. It is the composition which recovers timing by.
- FIG. 13 is a diagram for explaining a conventional information reproducing apparatus.
- a conventional information reproducing apparatus 1300 reproduces data and timing from an analog signal recorded on a medium 1301, such as a DVD, which also has data information and timing information power.
- ALPF Analog Low Pass Filter
- ADC AZD converter
- ADC Analog Equalizer
- interpolator 1305 DEQ (Digital Equalizer) 1306, TR (timing recovery logic) circuit 1307, controller 1308, FIR ( (Finite Impulse Response) circuit 1309 and Viterbi decoder 1310.
- the ADC 1303 converts an analog signal read from the medium 1301 into a digital signal and outputs the digital signal to the interpolator 1305.
- the frequency synthesizer 1304 supplies a clock having a predetermined frequency to the ADC 1303, the interpolator 1305, and the controller 1308.
- the interpolator 1305 generates a clock that is pseudo-synchronized with the timing of data recording on the medium 1301, and supplies the clock to the controller 1308, the FIR 1309, and the Viterbi decoder 1310.
- the DEQ 1306 equalizes a predetermined frequency component of the output signal of the interpolator 1305.
- the FIR circuit 1309 equalizes the output of the DEQ 1306 so that the output of the DEQ 1306 becomes a signal suitable for the targeted PR method.
- the Viterbi decoder 1310 reproduces the data recorded on the medium 1301 based on the output signal of the FIR circuit 1 309.
- Data and timing recorded on a medium 1301 such as a DVD are read by an optical pickup (not shown) and reproduced as an analog signal.
- Analog data was amplified and offset adjusted by the Variable Gain Amplifier (VGA) (not shown) and offset controller (not shown) provided in front of the ALPF1302 to match the input range of the ADC1303. After that, it is input to the ALPF 1302 and its high frequency component is removed.
- the analog signal output from the ALPF1302 is converted into a digital signal by the ADC1303.
- the sampling clock is supplied from the frequency synthesizer 1304. This clock is not necessarily synchronized with the timing clock recorded on the DVD medium, and is generally a clock having a faster frequency than the timing clock.
- the output clock of the frequency synthesizer 1304 is also input to the interpolator 1305 and the controller 1308.
- the digital signal output from ADC 1303 is not synchronized with the timing of data recorded on medium 1301.
- the interpolator 1305 synchronizes this by interpolation processing. That is, the interpolator 1305 synchronizes by receiving information corresponding to the phase difference between the sampling clock and the timing from the controller 1308 and interpolating according to the phase difference.
- the interpolator 1305 generates a clock that is pseudo-synchronized with the timing by thinning the sampling clock.
- the DEQ 1306 equalizes the output signal of the interpolator 1305.
- high frequency component For DVD, high frequency component
- DEQ 1306 Since the amplitude of (for example, 3T + 3T pattern) tends to be small, DEQ 1306 amplifies such components.
- the TR circuit 1307 performs timing recovery using the output of the DEQ 1306. In the case of a DVD, as shown in FIG. 14, since 14T + 4T sync marks appear at 1488T intervals, the TR circuit 1307 detects the frequency error by detecting the interval between the sync marks. The TR circuit 1307 detects the phase error based on the zero cross point value. . These frequency error and phase error are input to the controller 1308.
- the controller 1308 obtains a deviation from the timing recorded with the sampling clock based on the frequency error and the phase error.
- the interpolator 1305, the DEQ 1306, the TR circuit 1307, and the controller 1308 form a time delay circuit, and timing recovery is performed.
- the output of DEQ 1306 is further equalized so that the output of 1306 is a signal suitable for the target PR method (eg PR (3, 4, 4, 3)).
- the target PR method eg PR (3, 4, 4, 3)
- Viterbi decoder 1310 corrects the error of the output of FIR circuit 1309 by maximum likelihood decoding based on the Viterbi algorithm, whereby data recorded on medium 1301 is reproduced.
- FIG. 15 shows a conventional information reproducing apparatus that is different from the information reproducing apparatus 1300 in the configuration of the timing liquor loop.
- FIG. 15 shows a second conventional information reproducing apparatus.
- the information recovery device 1300 shown in FIG. 13 has a different timing recovery loop configuration.
- the ADC 1303, DEQ 1306, TR circuit 1307, and D / A converter ⁇ (DAC) 1502 And a VCO (Voltage Controlled Oscillator) 1 503 form a timing recovery loop.
- the DAC 1502 converts frequency information output from the TR circuit 1307 into an analog voltage.
- the VCO 1503 outputs a clock having a frequency based on the voltage value output from the DAC 1502.
- the output of ADC 1303 is equalized by DEQ 1306 and output to TR circuit 1307.
- the TR circuit 1307 calculates frequency information composed of a frequency error and a phase error based on the output signal of the DEQ 1306.
- the DAC 1502 converts the frequency information output from the TR circuit 1307 into an analog voltage.
- the VCO 1503 generates a clock having a frequency based on the output voltage of the DAC 1502.
- the clock output from the VCO1503 is supplied to the ADC1303, DAC1502, DEQ1306, and TR circuit 1307.
- the frequency of the clock output by 03 is synchronized with the recording timing of data on the medium 1301.
- Patent Document 1 Japanese Patent Laid-Open No. 9-204622
- Non-Patent Document 1 Floyd M. Gardner, “Interpolation in Digital Modes—Part I: Fundamentals” Ii 1 Transac Syons on Communique ⁇ Syons (IEEE Transactions on ommunications), Vol.41, No. d, p. 501— 507, March 1993
- Maximum likelihood decoding detects the closest sequence to the actually read sequence from various possible sequences and decodes the data corresponding to that sequence.
- the analog signal is a signal that is temporally continuous, it is difficult to calculate the closeness (or likelihood) to the expected sequence if the analog signal remains as it is. Therefore, in the conventional information reproducing apparatus described above, the likelihood is easily calculated by sampling with a signal synchronized with the channel clock. In addition, it is difficult to calculate the likelihood even if the amplitude direction is continuous or the possible values are multivalued. Therefore, in the conventional information reproducing apparatus described above, a target PR method is defined and equalization processing is performed in accordance with it.
- the possible values when the medium 1301 is a DVD are ⁇ — 7, -4, It is very easy to calculate the likelihood because it falls within 5 values of 0, 4, 7 ⁇ . As a result, a compact Viterbi decoder can be realized.
- timing recovery and equalization processing are performed in order to bring the analog signal read from the medium closer to the expected sequence.
- the ability to realize a compact maximum-likelihood decoder requires a complicated timing recovery circuit and a large-scale equalization circuit, resulting in the following problems. ing.
- the interpolator 1305 has a problem that an interpolation error occurs when the digital signal sampled by the asynchronous clock is interpolated so as to be pseudo-synchronized with the recorded timing.
- interpolation error becomes large.
- the circuit scale will increase.
- various factors of noise may be mixed in the input analog signal itself of the ADC1303, so such signal power interpolation processing may cause erroneous interpolation due to noise or noise enhancement.
- noise enhancement There is also a possibility of producing.
- DEQ 1306 since DEQ 1306 amplifies high frequency components with a digital FIR filter, it may cause noise enhancement as well as interpolator 1305.
- D EQ 1306 since the D EQ 1306 has an FIR filter configuration, there is a latency. Since the latency in the timing recovery loop increases the loop delay, the stability of the timing recovery operation deteriorates.
- the output of the DEQ 1306 is equalized by a digital FIR filter so as to correspond to a target PR method (for example, PR (3, 4, 4, 3)). For this reason, again, there is a possibility of producing noise enhancement.
- the circuit scale of the Viterbi decoder 1310 in the subsequent stage can be reduced by the equalization by the FIR circuit 1309. On the contrary, the circuit scale of the FIR circuit 1309 is also increased.
- the VCO 1503 in the second conventional example needs to be vigorous in its frequency resolution so that it can follow even minute frequency fluctuations, and to cope with changes in the operating speed of the optical disc apparatus.
- the frequency band must be wide.
- VC01503 is an analog circuit, it has a problem that its area increases.
- the VCO1503 has the problem that the design man-hours are very large in order to design a circuit that can easily withstand the effects of voltage, temperature, and noise.
- the present invention has been made to solve the above-described problems.
- Information recovery that can prevent degradation of the quality of data and timing reproduced due to interpolation errors at the time of recovery, and avoid deterioration of system stability due to increased timing recovery loop delay
- the object is to obtain a device.
- the invention according to claim 1 of the present application provides a data reading unit that reads a first signal from an information recording medium, a clock generator that generates a fixed clock, and the first signal that includes the fixed clock. A data change to obtain a second signal by sampling with a second clock, and an arithmetic unit for calculating a branch metric for the second signal force at the timing of the fixed clock. .
- the invention according to claim 2 of the present application is the information reproducing apparatus according to claim 1, wherein the first signal is an analog signal including data information and timing information, and
- the present invention is characterized in that it is an analog digital transformation that converts the analog signal into a digital signal with a fixed clock.
- the invention according to claim 3 of the present application is the information reproducing apparatus according to claim 2, wherein timing error information between data recording timing to the information recording medium and the fixed clock is output, and the data Based on the timing detector that outputs a second clock that is pseudo-synchronized with the recording timing and the timing error information!
- An expected value generator for outputting a plurality of expected values, wherein the arithmetic unit outputs an output sequence of the analog-digital converter among the plurality of expected value sequences output as the expected value generator force.
- the invention according to claim 4 of the present application is the information reproducing apparatus according to claim 1, wherein the frequency of the fixed clock is higher than the frequency of data recording timing on the information recording medium. It is what.
- the invention according to claim 5 of the present application is the information reproducing apparatus according to claim 1, wherein the frequency of the fixed clock is lower than the frequency of data recording timing on the information recording medium. It is what.
- the invention according to claim 6 of the present application is the information reproducing apparatus according to claim 3, wherein The imming detector controls the clock generator based on the timing error information so that the frequency power of the clock output from the clock generator is always higher than the frequency of the data recording timing. To do.
- the invention according to claim 7 of the present application is the information reproducing device according to claim 3, wherein the timing detector is based on a frequency force of a clock output from the clock generator, and a frequency of the data recording timing.
- the clock generator is controlled based on the timing error information so as to be always low.
- the invention according to claim 8 of the present application is the information reproducing apparatus according to claim 3, further comprising a DC component detector that detects a DC component of the information reproducing apparatus, wherein the expected value generator includes The expected value is corrected based on the DC component output from the DC component detector.
- the invention according to claim 9 of the present application is the information reproducing apparatus according to claim 3, wherein the expected value generator includes an expected value of a synchronization point synchronized with the data recording timing, and the timing error The expected value of the synchronization point is generated by interpolating the expected value of the synchronization point based on the information to synchronize with the fixed clock.
- the invention according to claim 10 of the present application is the information reproducing apparatus according to claim 3, wherein the expected value generator divides a plurality of synchronization points synchronized with the data recording timing in a time axis direction. An expected value of the division point is provided, and a medium specific expected value of the expected value of the division point is selected based on timing error information output from the timing detector.
- the invention according to claim 11 of the present application is the information reproducing apparatus according to claim 3, wherein the expected value generator adaptively generates an expected value to be generated based on the reproduced data output from the arithmetic unit. It is characterized by controlling to.
- the invention according to claim 12 of the present application is the information reproducing apparatus according to claim 3, wherein the calculation unit is configured to branch from the analog-digital conversion output and its expected value based on the fixed clock.
- the invention according to claim 13 of the present application is the information reproducing apparatus according to claim 12, wherein the branch metric calculator has a plurality of edges of the fixed clock between edges of the second clock. Is characterized in that a branch metric is calculated from the analog digital transformation output corresponding to each edge of the fixed clock and its expected value.
- the invention according to claim 14 of the present application is the information reproducing device according to claim 12, wherein the branch metric calculator has a plurality of edges of the fixed clock between edges of the second clock. Is characterized in that a branch metric is calculated from the analog-digital conversion output corresponding to the edge of the fixed clock closest to the edge of the second clock and its expected value.
- the invention according to claim 15 of the present application is the information reproducing apparatus according to claim 1, further comprising a disk drive that reads an analog signal recorded on the optical disk from the optical disk that is the information recording medium. It is characterized by.
- the invention according to claim 16 of the present application is the information reproducing apparatus according to claim 1, wherein the information recording medium is a DVD disc.
- the invention according to claim 17 of the present application is the information reproducing apparatus according to claim 1, wherein the information recording medium is a Blu-ray disc.
- the invention according to claim 18 of the present application is the information reproducing apparatus according to claim 1, wherein the information reproducing apparatus is used for both reproduction of a DVD disc and reproduction of a Blu-ray disc. It is characterized by.
- the invention according to claim 19 of the present application is the information reproducing apparatus according to claim 1, wherein the information recording medium is an HD-DVD disc.
- the invention according to claim 20 of the present application is the data reading step for reading the first signal as well as the information recording medium power, the clock generation step for generating a fixed clock, and the first signal is sampled with the fixed clock. And a data conversion step for obtaining a second signal, and an operation step for calculating a branch metric for the second signal power at the timing of the fixed clock.
- the invention according to claim 21 of the present application is the information reproduction method according to claim 20,
- the first signal is an analog signal including data information and timing information
- the data conversion step converts the analog signal into a digital signal using the fixed clock.
- the invention according to claim 22 of the present application is the information reproducing method according to claim 21, wherein timing error information between the data recording timing to the information recording medium and the fixed clock is output, and the data recording timing is A timing detection step of outputting a second clock that is pseudo-synchronized with each other, and an expected value generation step of outputting a plurality of expected values based on the timing error information, wherein the calculating step includes the step of generating the expected value.
- the calculating step includes the step of generating the expected value.
- the data corresponding to the sequence having the highest likelihood with the output sequence of the signal output in the data conversion step is output. It is characterized by doing.
- the invention according to claim 23 of the present application is the information reproducing method according to claim 20, characterized in that the frequency of the fixed clock is higher than the frequency of the data recording timing.
- the invention according to claim 24 of the present application is the information reproduction method according to claim 20, characterized in that the frequency of the fixed clock is lower than the frequency of the data recording timing.
- the invention according to claim 25 of the present application is the information reproduction method according to claim 22, wherein the clock generation step is always higher than the frequency power of the fixed clock and the frequency of the data recording timing. Based on the timing error information, the fixed clock frequency is switched and output.
- the invention according to claim 26 of the present application is the information reproducing method according to claim 22, wherein the clock generation step is always lower than the frequency force of the fixed clock and the frequency of the data recording timing. Based on the timing error information, the fixed clock frequency is switched and output.
- the invention according to claim 27 of the present application is the information reproduction method according to claim 22, further comprising a DC component detection step of detecting a DC component of the second signal, wherein the expected value generation step includes , Based on the DC component detected in the DC component detection step The expected value is corrected.
- the invention according to claim 28 of the present application is the information reproduction method according to claim 22, wherein the expected value generation step reads an expected value of a synchronization point synchronized with the data recording timing, and the timing error information The expected value of the synchronization point synchronized with the fixed clock is generated by interpolating the expected value of the synchronization point based on the above.
- the invention according to claim 29 of the present application is the information reproduction method according to claim 22, wherein the expected value generation step is a division in which a plurality of synchronization points synchronized with the data recording timing are divided in a time axis direction. An expected value of the point is read out, and a specific expected value is selected from the expected values of the divided points based on the timing error information.
- the invention according to claim 30 of the present application is the information reproduction method according to claim 22, wherein the expected value generation step generates an expected value to be generated based on the reproduction data output in the calculation step. It is characterized by adaptive control.
- the invention according to claim 31 of the present application is the information reproduction method according to claim 22, wherein the calculation step is based on the output of the data conversion step and the expected value based on the fixed clock.
- the invention according to claim 32 of the present application is the information reproduction method according to claim 31, wherein the branch metric calculation step includes a plurality of fixed clock edges between edges of the second clock. In this case, a branch metric is calculated from the value of the second signal corresponding to each edge of the fixed clock and its expected value.
- the invention according to claim 33 of the present application is the information reproduction method according to claim 31, wherein the branch metric calculation step includes a plurality of fixed clock edges between edges of the second clock.
- the branch metric is calculated from the value of the second signal corresponding to the edge of the fixed clock closest to the edge of the second clock and the expected value thereof. It is characterized by calculating.
- the invention according to claim 34 of the present application is the information reproducing method according to claim 20, wherein the information recording medium is a DVD disc.
- the invention according to claim 35 of the present application is the information reproducing method according to claim 20, wherein the information recording medium is a Blu-ray disc.
- the invention according to claim 36 of the present application is the information reproducing method according to claim 20, wherein the information recording medium is an HD-DVD disc.
- a data reading unit that reads a first signal from an information recording medium, a clock generator that generates a fixed clock, and the first signal that is the fixed clock
- Data sampling to obtain the second signal by sampling and the arithmetic unit for calculating the branch metric also for the second signal power at the timing of the fixed clock.
- the recording medium force read out the first signal includes data information and timing information. It is an analog signal, and the data converter is an analog-digital converter that converts the analog signal to a digital signal with the fixed clock. The influence of noise can be avoided, and data can be reproduced with high accuracy.
- the timing error information between the data recording timing to the information recording medium and the fixed clock is output.
- a timing detector that outputs a second clock that is pseudo-synchronized with the data recording timing, and based on the timing error information! Expected value generator that outputs multiple expected values
- the arithmetic unit further includes data corresponding to a sequence having the highest likelihood with the output sequence of the analog-digital converter among the plurality of expected value sequences output as the expected value generator force, Since the output is performed at the timing of the second clock, it is not necessary to provide an FIR filter having a large circuit scale, and the circuit scale of the information reproducing apparatus as a whole can be reduced.
- the frequency of the fixed clock is higher than the frequency of data recording timing on the information recording medium. This eliminates the need for a VCO to generate a clock that is synchronized with the data recording timing, simplifies the clock generator configuration, and reduces the clock generator area and design man-hours. can do.
- the frequency of the fixed clock is lower than the frequency of data recording timing on the information recording medium. This eliminates the need for a VCO to generate a clock that is synchronized with the data recording timing, simplifies the clock generator configuration, and reduces the clock generator area and design man-hours. can do.
- the timing detector includes a frequency force of a clock output from the clock generator, and the data recording timing. Since the clock generator is controlled based on the timing error information so as to always be higher than the frequency of the data, the data reading speed changes between the inner and outer peripheral portions of the medium. Even so, it is possible to always perform a stable data reproduction operation.
- the timing detector includes the frequency force of the clock output from the clock generator and the data recording timing. Since the clock generator is controlled based on the timing error information so as to be always lower than the frequency of the data, the data reading speed changes between the inner and outer peripheral portions of the medium. Even so, it is possible to perform stable data reproduction operations.
- the information A DC component detector for detecting a DC component of the information reproducing apparatus, and the expected value generator corrects the expected value based on the DC component output from the DC component detector.
- the expected value generator includes an expected value of a synchronization point synchronized with the data recording timing, Since the expected value of the synchronization point is interpolated based on the timing error information and the expected value of the synchronization point synchronized with the fixed clock is generated, the interpolation error caused by the interpolation process for timing recovery can be reduced. The influence of noise can be avoided, and highly accurate data reproduction can be performed. In addition, since it is not necessary to install an FIR filter with a large circuit scale, it is possible to reduce the circuit scale of the information reproducing apparatus as a whole.
- the expected value generator divides a plurality of synchronization points synchronized with the data recording timing in the time axis direction. Since the expected value of the division point is provided and the intermediate specific expected value of the expected value of the division point is selected based on the timing error information output from the timing detector, the expected value interpolation process is performed. It is possible to simplify the circuit operation that does not need to be performed.
- the expected value generator is an expected value to be generated based on the reproduced data output by the arithmetic unit. Therefore, even if the signal waveform read from the medium is extremely distorted, it is possible to accurately reproduce the recorded data.
- the arithmetic unit based on the fixed clock, generates a branch from the analog-digital conversion output and its expected value. Since it has a branch metric calculator for calculating a metric and a path metric calculator for calculating a path metric using the branch metric based on the second clock, it is sampled with an asynchronous clock. Analog reproduction wave From the shape, data synchronized with the data recording timing can be reproduced by maximum likelihood decoding.
- the branch metric calculator has a plurality of fixed clock edges between the edges of the second clock. Since the branch metric is calculated from the analog digital transformation output corresponding to each edge of the fixed clock and its expected value, the data is obtained from the analog reproduction waveform sampled by the asynchronous clock. Data synchronized with the recording / writing timing can be reproduced by maximum likelihood decoding.
- the branch metric calculator includes a plurality of edges of the first clock between edges of the second clock. If there is a branch metric, the branch metric is calculated from the analog-digital conversion output corresponding to the edge of the first clock closest to the edge of the second clock and the expected value thereof. There is no need to perform accumulation, and the branch metric calculation process can be simplified.
- the information reproducing apparatus further includes a disk drive that reads an analog signal recorded on the optical disk from the optical disk that is the recording medium.
- a disk drive that reads an analog signal recorded on the optical disk from the optical disk that is the recording medium.
- the recording medium is a DVD disc in the information reproducing apparatus of claim 1, data written on the DVD is It becomes possible to reproduce accurately.
- the recording medium is a Blu-ray disc. It is possible to reproduce the recorded data with high accuracy.
- the information reproducing apparatus of claim 1 in the information reproducing apparatus of claim 1, the information reproducing apparatus is used for both reproduction of a DVD disc and reproduction of a Blu-ray disc. Therefore, it is possible to perform highly accurate data reproduction in both DVD reproduction and Blu-ray Disc reproduction.
- the recording medium is an HD-DVD disc, data written to the HD-DVD disc is used. Can be reproduced with high accuracy.
- a data read step for reading the first signal from the information recording medium, a clock generation step for generating a fixed clock, and the first signal are sampled with the fixed clock.
- the data conversion step for obtaining the second signal and the calculation step for calculating the branch metric at the timing of the fixed clock are also included.
- the clock generator configuration can be simplified, and the clock generator area and design man-hours can be reduced.
- the first signal read out of the recording medium force includes data information and timing information. Since the data conversion step converts the analog signal into a digital signal with the fixed clock, it is possible to avoid the effects of interpolation errors and noise caused by interpolation processing for timing recovery. In addition, data reproduction can be performed with high accuracy.
- the timing error information between the data recording timing to the information recording medium and the fixed clock is output, A timing detection step of outputting a second clock that is pseudo-synchronized with the data recording timing, and an expected value generation step of outputting a plurality of expected values based on the timing error information, wherein the calculation step comprises the expected value Of the plurality of expected value sequences output in the generation step, data corresponding to the sequence having the highest likelihood with the output sequence of the signal output in the data conversion step is the second clock timing. Since the output is performed by imming, it is not necessary to provide a large circuit scale FIR filter, and the circuit scale of the information reproducing apparatus as a whole is reduced.
- the frequency of the fixed clock is higher than the frequency of the data recording timing.
- the configuration of the clock generator can be simplified, and the area of the clock generator and the design man-hours can be reduced. it can.
- the clock generation step is always higher in frequency power of the fixed clock than the frequency of the data recording timing.
- the fixed clock frequency is switched and output based on the timing error information, the data reading speed varies between the inner and outer peripheral portions of the medium. Even in such a case, it is possible to always perform a stable data reproduction operation.
- the frequency of the fixed clock is always lower than the frequency of the data recording timing. Since the fixed clock frequency is switched and output, stable data reproduction can be performed even when the data reading speed varies between the inner and outer periphery of the medium. It becomes.
- the expected value generation Since the generation step corrects the expected value based on the DC component detected in the DC component detection step, the output of the AZD variation can be directly input to the maximum likelihood sequence detector.
- maximum likelihood decoding can be performed using information in the amplitude direction, and data reproduction can be performed with high accuracy.
- the expected value generation step reads the expected value of the synchronization point synchronized with the data recording timing, and interpolates the expected value of the synchronization point based on the timing error information, thereby expecting the expected synchronization point synchronized with the fixed clock. Timing of value generation Interpolation errors and noise caused by interpolation processing for recovery can be avoided, and highly accurate data reproduction can be performed. In addition, since it is not necessary to provide an FIR filter with a large circuit scale, it is possible to reduce the circuit scale of the information reproducing apparatus as a whole.
- the expected value generation step includes a plurality of synchronization points synchronized with the data recording timing in the time axis direction.
- the expected value of the divided division point is read out, and based on the timing error information, the specific expected value is selected from the expected value of the divided point. This makes it possible to simplify the circuit operation.
- the expected value generation step should be generated based on the reproduction data output in the calculation step. Since the expected value is adaptively controlled, it is possible to accurately reproduce the recorded data even when the signal waveform read out by the medium force is extremely distorted.
- the calculation step is based on the second signal and its expected value based on the fixed clock.
- the branch metric calculation step includes a plurality of fixed clocks between edges of the second clock. If there is an edge, the edge corresponding to each edge of the fixed clock Since the branch metric is calculated from the value of the second signal and its expected value, the data synchronized with the data recording / writing timing is obtained from the analog reproduction waveform sampled with the asynchronous clock by the maximum likelihood decoding. It can be played back.
- the branch metric calculation step includes a plurality of the fixed clocks between the edges of the second clock. If there is an edge, the branch metric is calculated from the value of the second signal corresponding to the edge of the fixed clock closest to the edge of the second clock and the expected value thereof. There is no need to accumulate metrics, and the branch metric calculation process can be simplified.
- the information recording medium is a DVD disc according to the information reproducing method of claim 20
- the data written on the DVD is high. It becomes possible to reproduce accurately.
- the information recording medium is a Blu-ray disc according to the information reproducing method of claim 20
- the information is recorded on the Blu-ray disc.
- the reproduced data can be reproduced with high accuracy.
- FIG. 1 (a) is a diagram showing a configuration of an information reproducing apparatus according to Embodiment 1 of the present invention.
- FIG. 1 (b) is a diagram for explaining the operation of the information reproducing apparatus according to the first embodiment of the present invention.
- FIG. 2 is a diagram showing a configuration of a timing detector.
- FIG. 3 is a schematic diagram for explaining the operation of the NCO circuit.
- FIG. 4 is a diagram for explaining the operation of the expected value generator.
- FIG. 5 is a diagram showing a configuration of a maximum likelihood decoder.
- FIG. 6 is a timing chart for explaining the operation of the maximum likelihood decoder.
- FIG. 7 is a diagram showing a configuration of an information reproducing apparatus according to Embodiment 2 of the present invention.
- FIG. 8 is a diagram for explaining the operation of the baseline control circuit.
- FIG. 9 is a diagram showing a configuration of the information reproducing apparatus according to the third embodiment of the present invention.
- FIG. 10 is a diagram showing a modification of the configuration of the information reproducing apparatus according to the third embodiment of the present invention.
- FIG. 11 is a diagram showing a configuration of an information reproducing apparatus according to Embodiment 4 of the present invention.
- FIG. 12 is a diagram showing an analog signal waveform read out by the medium force.
- FIG. 13 is a diagram showing a configuration of a conventional information reproducing apparatus.
- FIG. 14 is a diagram for explaining sync marks.
- FIG. 15 is a diagram showing a configuration of a conventional information reproducing apparatus.
- the basic principle of the present invention is to bring the expected sequence closer to the analog signal as opposed to bringing the analog signal from which the medium force is read out closer to the expected sequence. .
- FIG. 1 (a) is a diagram for explaining an information reproducing apparatus according to Embodiment 1 of the present invention.
- the information reproducing apparatus 100 according to the first embodiment reproduces data and timing from an analog signal having data information and timing information recorded on a medium 101 such as a DVD.
- ALPF Analog Low Pass Filter
- ADC AZD conversion
- clock generator 104 clock generator 104
- timing detector 105 expected value generator 106
- maximum likelihood decoder 107 maximum likelihood decoder
- ALPF 102 and ADC 103 are the same as those in conventional information reproducing apparatus 1300 shown in FIG.
- the clock generator 104 generates a fixed-frequency clock CLK1, and the generated clock is converted to the ADC 103, the timing detector 105, the expected value generator 106, and the maximum value. This is supplied to the likelihood decoder 107.
- the frequency of the clock generated by the clock generator 104 is not necessarily required to be synchronized with the timing of data recording on the medium 101, that is, synchronized with the channel clock.
- Asynchronous fixed frequency oversample clock hereinafter referred to as “asynchronous clock” with a margin.
- the timing detector 105 generates a pseudo-synchronized clock CLK2 that is pseudo-synchronized with the channel clock and creates parameters for interpolating the expected value.
- the expected value generator 106 is the maximum likelihood.
- An expected value used in the decoder 107 is generated.
- the maximum likelihood decoder 107 generates reproduction data based on the expected value and the output S1 of the ADC 103.
- FIG. 1B is a diagram for explaining the operation of the information reproducing apparatus 100.
- the data information recorded on the DVD medium 101 and the timing information power are read out as an analog signal by the optical pickup (step 101), and the clock generator 104 Asynchronous clock CLK1 is generated (step 102).
- the analog signal read from the medium 101 is adjusted in amplitude and offset by a VGA and an offset adjuster (both not shown), and then the high-frequency component is removed by the ALPF 102. It is converted into a digital signal (step 103).
- the ADC output S1 and the asynchronous clock CLK1 are respectively input to the timing detector 105.
- the pseudo synchronous clock CLK2 that is pseudo-synchronized with the channel clock and the parameter for interpolating the expected value Is generated (step 104).
- Expected value generator 106 interpolates a preset default expected value based on parameter ⁇ , generates an expected value of maximum likelihood decoder 107, and outputs the expected value to maximum likelihood decoder 107. (Step 105).
- the maximum likelihood decoder 107 performs ADC output S1 at the timing of the asynchronous clock CLK1. Then, the branch metric is calculated from the expected value of the ADC output SI output from the expected value generator 106, and the path metric is calculated using the branch metric at the timing of the pseudo synchronous clock CLK2. Data to be reproduced is calculated and output (step 106).
- timing detector 105 the expected value generator 106, and the maximum likelihood decoder 107, and details of the steps 104 to 106 executed by each of these components will be described.
- FIG. 2 is a block diagram showing a detailed configuration of the timing detector 105.
- the timing detector 105 includes a sync mark detector 201, a counter 202, an operation value holding unit 203, a divider 204, a phase comparator 205, an NCO control value calculator 206, and an NCO circuit 207.
- a pseudo-synchronous clock generator 208 is included in the timing detector 105.
- the sync mark detector 201 detects a sync mark from the ADC output S1.
- the counter 202 counts the sync mark interval with the asynchronous clock CLK1 and outputs a count value Y.
- the calculation value holding unit 203 stores a reference calculation value X for determining the ratio between the channel clock and the asynchronous clock CLK 1.
- the reference calculation value X is a value unique to the medium 101. For example, when the medium 101 is a DVD, the value of X is 1488, which is the sync mark interval.
- the divider 204 calculates a ratio XZY between the channel clock and the asynchronous clock CLK1.
- the phase comparator 205 obtains a phase error between the ADC output S1 and the asynchronous clock LK1.
- the NCO control value calculator 206 calculates NCword (NCO Control word) which is a control value for controlling the NCO circuit 207.
- the pseudo-synchronous clock generator 208 generates the pseudo-synchronous clock C K2 that is pseudo-synchronized with the channel clock.
- step 104 executed by the timing detector 105.
- the sync mark detector 201 also detects the sync mark by the output power of the ADC 103. If the medium 101 is a DVD, as described above, the channel clock is detected by detecting the sync mark. The frequency of the lock can be extracted. As shown in FIG. 14, the sync mark is a specific pattern having 14T period force and 4T period force. Here, T represents the channel period. Sync marks are recorded on the medium so that they appear at 1488T intervals.
- the counter 202 counts the sync mark interval with the asynchronous clock CLK 1 and outputs it to the divider 204.
- the divider 204 divides the calculated value X stored in the calculated value holding unit 203 by the counter value Y, which is the output of the counter 202, to determine the ratio between the channel clock and the asynchronous clock CLK1, and to calculate the NCO control value.
- Output to the calculator 206 For example, if the channel clock is 27 MHz and the synthesizer clock is 54 MHz, the output value of the divider 204 is 0.5.
- the phase comparator 205 obtains a phase error between the ADC output S1 and the asynchronous clock CLK1 based on the output of the ADC 103 and the asynchronous clock CLK1, and outputs the phase error to the NCO control value calculator 206.
- the NCO control value calculator 206 corrects the output value of the divider 204 based on the output of the phase comparator 205 and calculates NCword.
- the NCO circuit 207 subtracts the NCword value from the initial value 1 for each clock of the asynchronous clock CLK1, and subtracts the value between 1 and 0 while controlling so that the value does not become 0 or less. Repeat.
- FIG. 3 is a diagram for explaining the operation of the NCO circuit 207.
- tl to t5 represent asynchronous clock CLK1 timing
- N1 to N5 represent NCword values from tl to t5
- nl to n5 represent subtraction values from tl to t5
- 12 and 14 represent nl Represents the surplus value when ⁇ n5 is 0 or less.
- the overflow flag F indicates the output timing of the overflow flag F! /.
- N1 is subtracted from initial value 1 to calculate nl.
- N2 from nl at t2 to calculate n2.
- the NCO circuit 207 outputs the overflow flag F and raises 12 which is 0 or less.
- the (1-12) force also subtracts N3 to calculate n3. Since n3 is greater than or equal to 0, the overflow flag F will not be output and the subtraction value will not be raised.
- n4 is subtracted from n3 to calculate n4. At this time, the value is 0 or less as with t2, so the overflow flag F is output and 14 is raised.
- the above calculation can be expressed by the following equation (2).
- the NCO circuit 207 outputs the overflow flag F to the pseudo synchronous clock generator 208 by the above operation.
- the NCO circuit 207 is expressed by the following formula (3)
- the parameter value which is the timing error between the channel clock and the asynchronous clock CLK 1, is calculated and output to the expected value generator 106.
- Pseudo synchronous clock generator 208 is an asynchronous clock CL output from clock generator 104.
- step 105 executed by the expected value generator 106 .
- FIG. 4 is a diagram for explaining the operation of the expected value generator 106.
- the data recorded on the medium 101 is ⁇ 011110001 ⁇ .
- the sample point is synchronized with the channel clock, and PR (3, 4, 4, 3) Therefore, the expected value sequence is ⁇ 4, 0, 4, 7, 4, 0, -4, -4, 0, 4 ⁇ , as shown in Fig. 4 (a).
- the expected value is five values of ⁇ —7, -4, 0, 4, 7 ⁇ and cannot be obtained.
- the sample point is not synchronized with the channel clock. Do not fit.
- the NCword value calculated by the NCO control value calculator 206 of the timing detector 105 is The norm value output from the NCO circuit 207 is (0, 0. 75, 0. 5, 0. 25, 0, 0. 75, 0. 5, 0. 25, 0, 0. 75, 0. 5, 0. 25, 0 ⁇ and! /, ⁇ ⁇ ⁇ IJ.
- the expected value generator 106 a default expected value that is set in advance by the value of this parameter, for example, ⁇ -7, -4, 0, 4, 7 ⁇ in the present embodiment 1 is set.
- the expected value of ADC output S1 is generated by interpolation.
- the Figure 4 (b) shows the expected value sequence generated by the expected value generator 106.
- the first expected value is the following equation (4)
- the value is -4 because it is ⁇ force ⁇ .
- the next expected value can also be obtained from the above equation (4). However, since is 0.75, the value is one.
- the expected value generator 106 outputs the expected value as shown in FIG. 4 (b), thereby completing the above-described step 105.
- Maximum likelihood decoder 107 generates reproduction data based on the expected value output from expected value generator 106 and ADC output S1. Since the ADC output S1 is sampled by the asynchronous clock CLK1, its sample point is not necessarily synchronized with the channel clock synchronization point, and there are two sample points between the channel clock edges. There may be cases. Since the maximum likelihood decoder 107 switches such asynchronous data to synchronous data, the branch metric is calculated with the asynchronous clock CLK1, and the branch metric is added, compared, and selected with the pseudo synchronous clock CLK2, and the path metric is calculated. Is to be calculated.
- FIG. 5 is a block diagram showing the configuration of maximum likelihood decoder 107.
- the maximum likelihood decoder 107 includes arithmetic units 5al to 5an, an ACS (Add-Compare-Select) circuit 502, and a surviving path management circuit 503.
- the computing units 5al to 5an calculate branch metrics from the ADC output S1 and the expected value using the asynchronous clock CLK1.
- the ACS circuit 502 adds, compares, and selects the branch metrics output from the arithmetic units 5al to 5an and 5al to 5an, and stores the metric value with the highest likelihood as the path metric value.
- the surviving path management unit 503 receives the output of the ACS circuit 502 and the output of the clock generator 208, and outputs final reproduction data. Note that the ACS circuit 502 and the surviving path management unit 503 operate from the pseudo synchronous clock CLK2. Next, details of step 106 executed by the maximum likelihood decoder 107 will be described.
- FIG. 6 is a timing chart showing the operation of maximum likelihood decoder 107.
- (a) represents recording data recorded on the medium 101.
- (B) represents a clock synchronized with data, that is, a channel clock.
- (C) represents an analog reproduction signal read from the medium 101.
- (D) represents the asynchronous clock CLK1 output from the clock generator 104.
- (e) represents the pseudo-synchronous clock CLK2 output from the pseudo-synchronous clock generator 208.
- (F) represents the output of the ADC103.
- (G) represents the branch metric calculated by the calculators 5al to 5an.
- (h) represents the output of the ACS 502 path selection signal.
- tl to tn represent channel clock synchronization points
- 1 to n represent pseudo synchronization points.
- each of the arithmetic units 5al to 5an obtains branch metrics gl to gl from the ADC output fl and the expected value generated by the expected value generator 106. In Figure 6, they are collectively referred to as gl. Since each arithmetic unit 5al to 5an receives the next ADC output f2 before ACS502 receives the pseudo-synchronous clock CLK2, 2 calculates the branch metric g2 from the ADC output f2 and its expected value, and calculates gl and g2. Accumulate.
- ACS502 When ACS502 receives pseudo-synchronous clock CLK2 at t'2, arithmetic units 5al to 5an output branch metrics to ACS502 and reset the arithmetic values (cumulative values).
- the ACS circuit 502 adds, compares, and selects the branch metrics output from the arithmetic units 5al to 5an, stores the metric value with the highest likelihood as the path metric value, and indicates which path has been selected. Outputs the path selection signal hi.
- the branch metric g3 is calculated from the ADC output f3 and its expected value, and the ADC output f4 and its period After calculating g4 from the waiting value, these are accumulated.
- ACS circuit 502 receives pseudo-synchronization clock CLK2 at 3, arithmetic units 5al to 5an output branch metrics and reset the arithmetic values.
- the ACS circuit 502 stores a path metric value and outputs a path selection signal h2.
- the calculators 5al to 5an receive the ADC output f5 and calculate the branch metric g5.
- the ACS circuit 502 receives the pseudo synchronous clock CLK2. Since ADC output d is not received until 4, branch metric g5 is output at 3 and the value is reset.
- the ACS circuit 502 stores a path metric value and outputs a path selection signal h3. The operation described above is also performed for 4 and later.
- the surviving path management circuit 503 generates final reproduction data based on the path selection signal output from the ACS circuit 502, and the reproduction data is output. As a result, the reproducing operation of the data recorded on the medium 101 by the information reproducing apparatus 100 of the first embodiment is completed.
- timing recovery is performed by interpolating expected values that can be presumed by analogy and that is not affected by noise, so performance degradation due to interpolation error is minimized.
- the accuracy of data reproduction and timing recovery can be improved.
- the feedforward type timing recovery method since the feedforward type timing recovery method is used, there is an effect that the stability of the system is not deteriorated due to an increase in loop delay.
- the expected value generator 106 interpolates the expected value of the synchronization point that is synchronized with the channel clock timing that has been preliminarily set.
- the arithmetic units 5al to 5an of the maximum likelihood decoder 107 have a plurality of sample points when there are a plurality of sample points sampled with an asynchronous clock between the synchronous clocks. Force to add branch metrics calculated for each point Cumulative addition of branch clock from ADC output S1 corresponding to edge of asynchronous clock CLK1 closest to the edge of channel clock and its expected value It may be output to the circuit 502. In this case, it is possible to simplify the circuit operation without having to accumulate branch metrics.
- the frequency of the clock output from the clock generator 104 is switched under the control of the timing detector 105. It is a thing.
- the rotation control method of the DVD-ROM is usually the CLV (Constant Linear Velocity) method. It is difficult to control the rotation of the spindle motor during high-speed playback. Therefore, the CAV (Constant Angular Velocity) method is sometimes used.
- the CAV method since the recording frequency is higher at the outer peripheral portion than at the inner peripheral portion of the medium 101, even if the frequency of the clock output from the clock generator 104 is higher than the recording frequency at the inner peripheral portion of the medium 101, The relationship may be reversed at the outer periphery of the medium 101.
- the circuit configuration can be simplified if the frequency of the asynchronous clock output from the clock generator 104 is higher. Therefore, in the second embodiment, the clock generator is based on the timing detection signal output from the timing detector 105. It is assumed that the frequency of the clock output by 104 is switched.
- FIG. 7 is a block diagram showing a configuration of information reproducing apparatus 700 according to Embodiment 2 of the present invention.
- the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
- the difference between the second embodiment and the first embodiment is that the timing detector 105 switches the frequency of the asynchronous clock CLK1 output from the clock generator 104 to the clock generator 104.
- the control signal S2 to be instructed is output, and the clock generator 104 is configured to be able to switch and output several stages of frequencies.
- the timing detector 105 receives the output of the ADC 103 and the output of the clock generator 104, and the divider 204 provided therein provides the ratio XZY between the channel clock and the asynchronous clock CLK1 output from the clock generator 104. Ask. Asynchronous clock CLK1 is faster than channel clock, so X ⁇ Y.
- the control signal generation circuit detects the ratio ⁇ and outputs the control signal S2 to the clock generator 104 when the ratio ⁇ ⁇ is likely to reverse.
- the clock generator 104 receives the control signal S2 and switches the asynchronous clock CLK1 to be output to a clock having a frequency that is a predetermined multiple of the basic frequency. For example, by dividing the generated frequency, a clock with a fundamental frequency of 2 times, 4 times, or 8 times is output.
- the timing detector 105 controls the frequency of the clock output from the clock generator 104 based on the ratio between the channel clock and the asynchronous clock CLK1 output from the clock generator 104. Therefore, the clock frequency output from the clock generator 104 can always be controlled to be higher than the channel clock, so that the outer peripheral portion of the medium 101 has a higher recording frequency than the inner peripheral portion. Even in such a case, stable data reproduction operation can be performed.
- the expected value generator 106 is based on the output of the baseline controller (BC) that detects the DC component and adjusts the level in the information reproducing apparatus according to the first embodiment. The expected value to be output is corrected.
- BC baseline controller
- FIG. 9 is a configuration diagram showing an information reproducing device 900 according to the third embodiment.
- reference numeral 901 denotes a baseline control circuit (BC) that detects a direct current component in the information reproducing apparatus 900 and performs control so that the value becomes an optimum level.
- BC baseline control circuit
- the analog data when analog data is read from the medium 101, the analog data is subjected to AZD conversion by the ADC 103 and then output to the phase comparator 205 in the timing detector 105. Is done. Further, the clock generator 104 generates an asynchronous clock CLK 1 and outputs it to the phase comparator 205.
- phase comparator 205 The output signal of phase comparator 205 is output to NCO control value calculator 206 and output to BC 901 as in the first embodiment.
- BC 901 receives the output of phase comparator 205 and detects the DC component by detecting the rising point and falling point of the output signal waveform. Based on the detected DC component, a baseline error, that is, a correction amount is obtained, and a control signal representing the correction amount is output to the expected value generator 106.
- Expected value generator 106 corrects the generated expected value according to the control signal output from BC901. For example, the generated expected value force baseline error is reduced and the entire expected value sequence is raised. [0160] Then, in the maximum likelihood decoder 107, the reproduction data is calculated based on the expected value after correction and the ADC output S1, as in the first embodiment.
- Fig. 8 (a) shows the waveform after analog reproduction with asymmetry is digitized by an AZD converter with 7-bit resolution.
- the maximum value of the waveform is controlled to 63 and the minimum value is 64 so that the range of the AZD converter can be fully utilized.
- the data written to the DVD is encoded so that the number of 1's and 0's are the same if the reference value is 0.
- FIG. 8 (a) it is necessary to correct the reference value. There is.
- the baseline control circuit detects the DC component by counting the number of 1s and 0s, then sets a reference value so that the number of 1s and 0s is the same, and raises the entire waveform upward to correct the baseline. Do.
- the output of the baseline control circuit is shown in Fig. 8 (b). As shown in Fig. 8 (b), the baseline control circuit forcibly saturates to 63 if the value exceeds 63 when raising the whole waveform upward. Therefore, if a baseline control circuit is placed immediately after the AZD converter and baseline correction is performed, the signal waveform will be distorted.
- the ADC output S1 is directly input to the maximum likelihood decoder 107, and the DC component is corrected by correcting the expected value generated by the expected value generator 106. Therefore, it is possible to avoid the distortion of the signal that occurs when correcting the ADC output S1, and this makes it possible to perform maximum likelihood decoding by making full use of the information in the amplitude direction. Playback can be performed.
- a BC901 is placed immediately after the ADC103, and the BC output signal is sent to the timing detector. 105 and the expected value generator 106 may be supplied to this embodiment. The same effect as in Mode 3 can be obtained.
- Embodiment 3 a baseline controller (BC) that detects a DC component and adjusts the level thereof is provided, and the expected value generator 106 outputs based on the output of BC901. Since the expected value is corrected, it is possible to input the output of the AZD variation directly to the maximum likelihood sequence detector, which makes it possible to perform maximum likelihood decoding that fully utilizes the information in the amplitude direction. Data reproduction can be performed with high accuracy.
- BC baseline controller
- the fourth embodiment adaptively controls the expected value generated by the expected value generator 106 based on the reproduction data output from the maximum likelihood decoding circuit 107 in the information reproducing apparatus according to the first embodiment. Is.
- the expected value set in advance by the expected value generator 106 is, for example, PR (3, 4 , 4, 3), it is sufficient to use the five values ⁇ — 7, -4, 0, 4, 7 ⁇ .
- the analog playback signal waveform of the medium 101 is a symmetrical waveform with the lower waveform collapsed as shown in Fig. 12 (a), it will be set in advance! Cannot be obtained.
- the value of the expected value generated by the expected value generator 106 is adaptively controlled based on the reproduction data output from the maximum likelihood decoding circuit 107.
- FIG. 11 is a diagram showing an information reproducing apparatus according to the fourth embodiment.
- the output signal of maximum likelihood decoder 107 is input to expected value generator 106.
- the expected value generator 106 detects a distortion amount for detecting the distortion amount of the analog reproduction signal waveform of the medium 101 from the decoded data S3 output from the maximum likelihood decoder 107.
- a detection circuit and a control circuit for adaptively controlling the expected value according to the amount of distortion are provided.
- analog data read from the medium 101 undergoes AZD conversion by the ADC 103 and is input to the maximum likelihood decoder 107.
- the maximum likelihood decoder 107 uses the ADC output S1 and the expected value output from the expected value generator 106 to determine the final value. The correct playback data.
- the expected value generator 106 When the expected value generator 106 receives the reproduction data S3 output from the maximum likelihood decoder 107, the expected value generator 106 obtains the distortion amount of the analog reproduction signal waveform of the data carrier medium 101, and defaults according to the detected amount. Select the expected value of. For example, as shown in Fig. 12 (b), if the lower side of the waveform is distorted, select –1 instead of –4 and –3 instead of –7 as the expected value. Then, the newly selected expected value is interpolated according to the parameter output from the timing detector 105 as in the first embodiment, and the value is output to the maximum likelihood decoder 107.
- Maximum likelihood decoder 107 outputs reproduction data based on the expected value after correction and ADC output S1.
- Embodiment 4 since the expected value output from expected value generator 106 is adaptively controlled based on the reproduction data output from maximum likelihood decoder 107, medium 10 Even when the signal waveform read from 1 is extremely distorted, it is possible to accurately reproduce the recorded data.
- the information reproducing apparatus has an expected value generator that interpolates and generates an expected value, can perform data reproduction with fewer errors, and is useful as a reproducing apparatus for an optical disc such as a DVD.
- the present invention can be applied to information reproducing applications other than optical disks.
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- 2005-08-15 WO PCT/JP2005/014907 patent/WO2006019073A1/ja active Application Filing
- 2005-08-15 CN CNA2005800281165A patent/CN101027727A/zh active Pending
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2007141928A1 (ja) * | 2006-06-02 | 2007-12-13 | Panasonic Corporation | 情報再生装置 |
US8059510B2 (en) | 2006-06-02 | 2011-11-15 | Panasonic Corporation | Information reproducing device |
JP4754630B2 (ja) * | 2006-06-02 | 2011-08-24 | パナソニック株式会社 | 情報再生装置 |
WO2008065768A1 (fr) * | 2006-11-29 | 2008-06-05 | Panasonic Corporation | Appareil de traitement de signal reproduit et appareil d'affichage vidéo |
JPWO2008065768A1 (ja) * | 2006-11-29 | 2010-03-04 | パナソニック株式会社 | 再生信号処理装置及び映像表示装置 |
JP4528834B2 (ja) * | 2006-11-29 | 2010-08-25 | パナソニック株式会社 | 再生信号処理装置及び映像表示装置 |
JP4679640B2 (ja) * | 2007-02-21 | 2011-04-27 | パナソニック株式会社 | 最尤復号装置及び情報再生装置 |
WO2008102475A1 (ja) * | 2007-02-21 | 2008-08-28 | Panasonic Corporation | 最尤復号装置及び情報再生装置 |
JPWO2008102475A1 (ja) * | 2007-02-21 | 2010-05-27 | パナソニック株式会社 | 最尤復号装置及び情報再生装置 |
WO2008146421A1 (ja) * | 2007-05-30 | 2008-12-04 | Panasonic Corporation | 情報再生装置及び映像表示装置 |
JPWO2008146421A1 (ja) * | 2007-05-30 | 2010-08-19 | パナソニック株式会社 | 情報再生装置及び映像表示装置 |
JP2011014223A (ja) * | 2009-07-02 | 2011-01-20 | Lsi Corp | リード・チャネルにおけるフォーマット効率の高いタイミング回復のためのシステムおよび方法 |
JP2015138566A (ja) * | 2014-01-22 | 2015-07-30 | ソニー株式会社 | データ処理装置、データ処理方法、および再生装置 |
US9654278B2 (en) | 2014-01-22 | 2017-05-16 | Sony Corporation | Data processing device, data processing method, and recovery device |
Also Published As
Publication number | Publication date |
---|---|
US20070279784A1 (en) | 2007-12-06 |
JP4157145B2 (ja) | 2008-09-24 |
CN101027727A (zh) | 2007-08-29 |
JPWO2006019073A1 (ja) | 2008-05-08 |
US7616395B2 (en) | 2009-11-10 |
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