WO2005104536A1 - Dispositif de formation d’images a solide - Google Patents

Dispositif de formation d’images a solide Download PDF

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Publication number
WO2005104536A1
WO2005104536A1 PCT/JP2005/007338 JP2005007338W WO2005104536A1 WO 2005104536 A1 WO2005104536 A1 WO 2005104536A1 JP 2005007338 W JP2005007338 W JP 2005007338W WO 2005104536 A1 WO2005104536 A1 WO 2005104536A1
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WO
WIPO (PCT)
Prior art keywords
voltage
circuit
output
imaging device
switch
Prior art date
Application number
PCT/JP2005/007338
Other languages
English (en)
Japanese (ja)
Inventor
Seiichiro Mizuno
Haruhiro Funakoshi
Tetsuya Taka
Original Assignee
Hamamatsu Photonics K.K.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics K.K. filed Critical Hamamatsu Photonics K.K.
Publication of WO2005104536A1 publication Critical patent/WO2005104536A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling

Definitions

  • the present invention relates to a solid-state imaging device.
  • a solid-state imaging device As a solid-state imaging device, there is known a solid-state imaging device that logarithmically compresses a current signal generated by a photodiode in accordance with the amount of incident light and outputs it as a voltage signal (see, for example, Patent Document 1 and Patent Document 2). .
  • This solid-state imaging device has an advantage that a dynamic range for detecting the amount of incident light is large.
  • Patent document 1 JP-A-11 155105
  • Patent Document 2 JP-A-5-219443
  • the solid-state imaging device employing the above-described logarithmic compression method has a problem that the logarithmic compression characteristic (that is, the incident light amount detection characteristic) greatly changes depending on the temperature. I have.
  • the present invention has been made to solve the above problems, and has as its object to provide a solid-state imaging device having a large dynamic range for detecting the amount of incident light and having small temperature dependency.
  • the solid-state imaging device includes: (1) N photodiodes PD to PD that generate an amount of electric charge according to the amount of incident light; and (2) each photodiode PD is connected via a switch SW.
  • N is an integer of 2 or more
  • n is any integer of 1 or more and N or less.
  • each period ⁇ the switch SW is closed in each of the first accumulation period and the second accumulation period, and the other switch SW (m ⁇ n) remains open.
  • Each photodiode PD is connected to the integration circuit by closing the corresponding switch SW in each of the first accumulation period and the second accumulation period in the corresponding period T.
  • the switch SW In the first accumulation period, if the switch SW is closed, the light incident on the photodiode PD for a relatively long time after the time when the switch SW was last opened in the period T of the previous cycle is not affected.
  • the electric charge generated by the photodiode PD and accumulated in the junction capacitance is input to the integration circuit via the switch SW and accumulated in the capacitance, and the first voltage corresponding to the amount of the accumulated electric charge is generated. Integral circuit power is output.
  • the comparing circuit compares the magnitude of the first voltage output from the integrating circuit with the reference voltage, and outputs a comparison signal representing the result of the comparison. Then, based on the comparison signal, the holding circuit holds the first voltage if the first voltage is smaller than the reference voltage, and otherwise holds the second voltage.
  • the held voltage (the first voltage or the second voltage) is output from the holding circuit.
  • the comparison signal output from the comparison circuit indicates the magnitude relationship between the first voltage and the reference voltage (that is, the level of the amount of light incident on the photodiode PD). Further, since the amount of charge stored in the second storage period is smaller than the amount of charge stored in the first storage period, the second voltage is smaller than the first voltage.
  • the amount of light incident on the photodiode PD when the amount of light incident on the photodiode PD is relatively small, the amount of light incident on the photodiode PD can be detected based on the first voltage output from the holding circuit. On the other hand, when the amount of light incident on the photodiode PD is relatively large, the amount of light incident on the photodiode PD can be detected based on the second voltage that also outputs the holding circuit power.
  • this solid-state imaging device can increase the dynamic range of incident light amount detection for each pixel.
  • the charge generated by the photodiode PD is accumulated in the capacitor of the integration circuit, and a voltage corresponding to the amount of the accumulated charge is also output as the integration circuit power, the temperature dependency of the incident light amount detection is small.
  • the capacitance value of the capacitance portion of the integration circuit is variable, and the capacitance value of the capacitance portion in the second accumulation period is larger than the capacitance value of the capacitance portion in the first accumulation period. Is preferred. In this case, the dynamic range of light detection can be further increased.
  • the solid-state imaging device is provided between the integration circuit and the holding circuit, receives the voltage output from the integration circuit, and inputs the voltage at the start and end of the second accumulation period. It is preferable to further include a CDS circuit that outputs a voltage corresponding to the voltage difference to the holding circuit. Further, it is preferable to further include an AZD conversion circuit that inputs a voltage output from the holding circuit card, converts the input voltage into a digital value, and outputs the digital value. Further, the digital value output from the AZD conversion circuit is input, and the comparison signal output from the comparison circuit is input, and the bit of the digital value is shifted based on the comparison signal. It is preferable to further include a bit shift circuit that outputs the shifted digital value.
  • the solid-state imaging device has a large dynamic range for detecting the amount of incident light and has low temperature dependence.
  • FIG. 1 is a schematic configuration diagram of a solid-state imaging device 1 according to the present embodiment.
  • FIG. 2 is a circuit diagram of an integration circuit 10, a CDS circuit 20, a holding circuit 30, and a comparison circuit 40 of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 3 is a timing chart illustrating opening / closing timing of each switch SW of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 4 is a timing chart illustrating an operation in a period T of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 5 is a timing chart illustrating an operation in a period T of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 1 is a schematic configuration diagram of a solid-state imaging device 1 according to the present embodiment.
  • the solid-state imaging device 1 shown in this figure includes N photodiodes PD to PD, and N switches SW to SW.
  • N is an integer of 2 or more.
  • n used below is any integer of 1 or more and N or less.
  • Each photodiode PD has an anode terminal grounded and a force source terminal connected to a switch SW. It is connected to the integrating circuit 10 through the circuit. An input terminal of the integration circuit 10 is connected to one end of each of the N switches to the SW by a common wiring.
  • the input charge is stored in the capacitor unit, and a voltage V corresponding to the amount of the stored charge is output.
  • a CDS (Correlated Double Sampling) circuit 20 receives the voltage V output from the integrator 10 and inputs the voltage V at the first time and the second time.
  • the holding circuit 30 outputs voltage V output from the CDS circuit 20.
  • the comparison circuit 40 receives the voltage V output from the integration circuit 10 and receives the input voltage V
  • the input voltage at a predetermined time to the holding circuit 30 based on the comparison signal S is
  • the AZD conversion circuit 50 receives the voltage V output from the holding circuit 30 and
  • the voltage is converted to a digital value and this digital value D is output.
  • the bit shift circuit 60
  • the comparison signal S output from the controller is input and the bit of the digital value is
  • FIG. 2 is a circuit diagram of the integration circuit 10, the CDS circuit 20, the holding circuit 30, and the comparison circuit 40 of the solid-state imaging device 1 according to the present embodiment.
  • the integrating circuit 10 includes an amplifier A, a capacitor C, a capacitor C, a switch SW, and a switch SW.
  • the reference potential V is input to the non-inverting input terminal of the amplifier A.
  • the inverting input terminal of amplifier A is connected to photodiode PD via switch SW.
  • a switch SW and a capacitor are connected between the inverting input terminal and output terminal of amplifier A.
  • Capacitor C, capacitor C and switch SW constitute a variable capacitance part.
  • the variable capacitance section has capacitance values C and C as shown in the following equation (1).
  • One of the capacitance values is selectively set. That is, the switch SW is open
  • the capacitance value C of the variable capacitance section is equal to the capacitance value of the capacitor C. Also, switch S
  • the integration circuit 10 outputs the signal from the photodiode PD when the switch SW is open.
  • the charge stored in 10 11 10 c is discharged, and the output voltage is initialized.
  • the CDS circuit 20 includes an amplifier A, a capacitor C, and a switch SW.
  • Amplifier A is an amplifier A, a capacitor C, and a switch SW.
  • Input terminal is connected to the output terminal of amplifier A of integrating circuit 10 via capacitor C.
  • the holding circuit 30 includes an amplifier A, a capacitor C, and a switch SW.
  • This holding circuit 30 is connected to the ground potential via the capacitor C. This holding circuit 30
  • the comparison circuit 40 includes a comparator 41 and a D flip-flop 42.
  • the comparator 41 inputs the voltage V output from the integration circuit 10 and also inputs the reference voltage V.
  • Output level is high when voltage V is greater than reference voltage V, otherwise
  • the Clr signal input to the CLR input terminal is at a high level
  • the output level of the D flip-flop 42 from the Q output terminal is at a low level.
  • the D flip-flop 42 inputs the output voltage from the comparator 41 to the clock input terminal, and when this voltage also changes to a high level, the signal level previously input to the D input terminal is changed to the low level.
  • output from the Q output terminal A high-level signal is input to the D input terminal.
  • the signal output from the Q output terminal of the D flip-flop 42 becomes the comparison signal S.
  • the intensity of light incident on each of the N photodiodes PD to PD is generally
  • FIG. 3 is a timing chart illustrating opening / closing timing of each switch SW of the solid-state imaging device 1 according to the present embodiment. As shown in this figure, the operation of the solid-state imaging device 1 is sequentially repeated with N periods T to T as one cycle. Each period ⁇
  • the switch SW is closed for two partial periods (ie, the first accumulation period and the second accumulation period), and the other switch SW (m ⁇ n) remains open.
  • Each photodiode PD is connected to the integration circuit 10 by closing the corresponding switch SW in each of the first accumulation period and the second accumulation period in the corresponding period T.
  • Each period T is a fixed time, and the switching timing of the switch SW in each period T is constant.
  • FIGS. 4 and 5 are timing charts illustrating the operation of the solid-state imaging device 1 according to the present embodiment in the period T.
  • FIG. 4 illustrates the operation of each of the integration circuit 10, CDS circuit 20, holding circuit 30, and comparison circuit 40 when the amount of light incident on the photodiode PD is relatively small.
  • FIG. 5 illustrates the operation of each of the integration circuit 10, CDS circuit 20, holding circuit 30, and comparison circuit 40 when the amount of light incident on the photodiode PD is relatively large.
  • the switch SW 10 is open during the period from time t to time t.
  • the Clr signal goes high during the period from time t to time t.
  • the switch SW of the CDS circuit 20 has a period from time t to time t and a time t
  • the switch SW provided corresponding to the photodiode PD is turned on in the n n 3 4 period from time t to time t, and after a predetermined time in the period from time t to time t.
  • variable capacitance of the integrating circuit 10 In the period from the time t to the time t (first accumulation period), the variable capacitance of the integrating circuit 10
  • the capacitance value of the section is C (formula (la) above). If the switch SW is closed in the first accumulation period, the light is incident on the photodiode PD for a relatively long time after the last time the switch SW was opened in the period T of the previous cycle. The charge generated in the diode PD and stored in the junction capacitance is input to the integration circuit 10 via the switch SW and stored in the capacitor C, and the charge corresponding to the amount of the stored charge is calculated.
  • the first voltage is output from the integration circuit 10. Also, the voltage V output from the CDS circuit 20
  • the charge generated in the photodiode PD due to light incident on the photodiode PD for a relatively short period after the time t when the switch SW was last opened in the period T of the current cycle is:
  • the signal is input to the integration circuit 10 via the switch SW and stored in the capacitors C nn 10 and C, and the second voltage corresponding to the amount of the stored charges is integrated.
  • the voltage output from the integrating circuit 10 after the time t at which 202 2 opens is the fluctuation.
  • FIG. 4 shows the operation when the amount of light incident on the photodiode PD is relatively small.
  • the voltage V output from the integrating circuit 10 is smaller than the reference voltage V during a period of n3117 from the time t at which the switch SW closes to the time t at which the switch SW closes.
  • the output level of the comparator 41 of the comparison circuit 40 remains at the low level, and the comparison signal S output from the Q output terminal of the D flip-flop 42 remains at the low level.
  • the switch SW of the holding circuit 30 is closed at time t.
  • the holding circuit 30 holds the voltage, and thereafter, a voltage V corresponding to the held voltage is held by the holding circuit 3.
  • the time tt is based on a control signal output from a control circuit (not shown).
  • FIG. 5 shows the operation when the amount of light incident on the photodiode PD is relatively large.
  • the voltage V output from the integrating circuit 10 is higher than the reference voltage V during a period n3117 from the time t when the switch SW is closed to the time t when the switch SW is closed. Therefore,
  • the output level of the comparator 41 of the comparison circuit 40 changes from low level to high level, and the comparison signal S and the low level output from the Q output terminal of the D flip-flop 42 are both high level.
  • the voltage V output from the path 20 is held by the holding circuit 30, and thereafter, the held
  • Time t is a control circuit (not shown). It is determined based on a control signal output from the road.
  • the comparison signal S output from the comparison circuit 40 after time t is
  • the fact that the comparison signal S is at one level means that the variable capacitance section of the integration circuit 10 has a capacity.
  • the first voltage V output from the integration circuit 10 at the end of the storage period Is smaller than the reference voltage V, that is, the amount of light incident on the photodiode PD sat n
  • the high level of the comparison signal S indicates that the first voltage V output from the integration circuit 10 is high.
  • variable capacitance section of integration circuit 10 is set to capacitance value sat 2
  • the second voltage V output from the integration circuit 10 at the end of the accumulation period is smaller than the reference voltage V ref In other words, this indicates that the amount of light incident on the photodiode PD is relatively large.
  • This ratio can be set to, for example, 64: 1 by setting the switch to off and appropriately setting the opening / closing timing of the switch sw.
  • the digital value output from the AZD conversion circuit 50 is shifted by the required number of bits by the bit shift circuit 60.
  • the number of bits shifted at this time depends on the light receiving sensitivity ratio expressed by the above equation (3).
  • the solid-state imaging device 1 can increase the dynamic range of incident light amount detection for each pixel.
  • the charge generated by the photodiode PD is stored in the capacitor of the integration circuit 10 and a voltage corresponding to the amount of the stored charge is output from the integration circuit 10, the temperature dependency of the detection of the incident light amount is small.
  • the comparison circuit 40 is based on the voltage V output from the integration circuit 10 in the above embodiment.
  • the voltage V output from the CDS circuit 20 may be compared with the reference voltage V sat 20 sat.
  • the plurality of photodiodes may be arranged one-dimensionally or two-dimensionally. When a plurality of photodiodes are arranged two-dimensionally, an integrating circuit 10 or the like may be provided for each row of the arrangement. Also, as can be seen from the above equation (3), the dynamic range of photodetection can also be increased in this case in which the capacitance values of the capacitance sections of the integration circuit 10 can be equal to each other in the first accumulation period and the second accumulation period. Can be larger.
  • the present invention relates to a solid-state imaging device.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Il est prévu un dispositif de formation d’images à solide présentant une large plage dynamique de détection de la lumière incidente et une faible dépendance vis-à-vis de la température. Un circuit d’intégration (10) comporte une unité à capacité pour emmagasiner une charge électrique appliquée. Dans chaque période Tn de N périodes successivement répétées T1 à TN, le circuit d’intégration (10) applique une charge générée dans une photodiode PDn durant une première période d’emmagasinage, l’emmagasine dans l’unité à capacité et fournit une première tension en fonction de la charge électrique emmagasinée. Le circuit d’intégration (10) applique une charge électrique générée dans la photodiode PDn durant la deuxième période d’emmagasinage après la première période d’emmagasinage, l’emmagasine dans le circuit à capacité et fournit une deuxième tension en fonction de la charge électrique accumulée. Un circuit de maintien (30) maintient la première tension ou la deuxième tension fournie par le circuit d’intégration (10) et fournit la tension maintenue.
PCT/JP2005/007338 2004-04-19 2005-04-15 Dispositif de formation d’images a solide WO2005104536A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004123376A JP4429785B2 (ja) 2004-04-19 2004-04-19 固体撮像装置
JP2004-123376 2004-04-19

Publications (1)

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WO2005104536A1 true WO2005104536A1 (fr) 2005-11-03

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JP (1) JP4429785B2 (fr)
TW (1) TW200605653A (fr)
WO (1) WO2005104536A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2060887A1 (fr) * 2006-09-06 2009-05-20 Hamamatsu Photonics K.K. Photodétecteur

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4589030B2 (ja) * 2004-05-10 2010-12-01 浜松ホトニクス株式会社 光検出装置
WO2009022577A1 (fr) * 2007-08-10 2009-02-19 Sharp Kabushiki Kaisha Détecteur optique et dispositif d'affichage le comportant
TWI507934B (zh) * 2009-11-20 2015-11-11 Semiconductor Energy Lab 顯示裝置
JP6205763B2 (ja) * 2013-03-12 2017-10-04 株式会社リコー 光電変換装置及び画像生成装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522669A (ja) * 1991-07-09 1993-01-29 Sony Corp ビデオカメラ
JPH05176233A (ja) * 1991-12-20 1993-07-13 Minolta Camera Co Ltd 画像入力方法及び装置
JPH08265651A (ja) * 1995-03-24 1996-10-11 Sony Corp 撮像装置
JPH1188898A (ja) * 1997-09-11 1999-03-30 Fuji Photo Film Co Ltd 画像読取装置
JP2001141562A (ja) * 1999-11-15 2001-05-25 Hamamatsu Photonics Kk 光検出装置
WO2002012845A1 (fr) * 2000-08-03 2002-02-14 Hamamatsu Photonics K.K. Detecteur optique
JP2003004529A (ja) * 2001-06-18 2003-01-08 Hamamatsu Photonics Kk 光検出装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522669A (ja) * 1991-07-09 1993-01-29 Sony Corp ビデオカメラ
JPH05176233A (ja) * 1991-12-20 1993-07-13 Minolta Camera Co Ltd 画像入力方法及び装置
JPH08265651A (ja) * 1995-03-24 1996-10-11 Sony Corp 撮像装置
JPH1188898A (ja) * 1997-09-11 1999-03-30 Fuji Photo Film Co Ltd 画像読取装置
JP2001141562A (ja) * 1999-11-15 2001-05-25 Hamamatsu Photonics Kk 光検出装置
WO2002012845A1 (fr) * 2000-08-03 2002-02-14 Hamamatsu Photonics K.K. Detecteur optique
JP2003004529A (ja) * 2001-06-18 2003-01-08 Hamamatsu Photonics Kk 光検出装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2060887A1 (fr) * 2006-09-06 2009-05-20 Hamamatsu Photonics K.K. Photodétecteur
EP2060887A4 (fr) * 2006-09-06 2014-01-22 Hamamatsu Photonics Kk Photodétecteur

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JP4429785B2 (ja) 2010-03-10
JP2005311542A (ja) 2005-11-04
TW200605653A (en) 2006-02-01

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