WO2005086485A1 - 符号化データ復号装置 - Google Patents
符号化データ復号装置 Download PDFInfo
- Publication number
- WO2005086485A1 WO2005086485A1 PCT/JP2004/018261 JP2004018261W WO2005086485A1 WO 2005086485 A1 WO2005086485 A1 WO 2005086485A1 JP 2004018261 W JP2004018261 W JP 2004018261W WO 2005086485 A1 WO2005086485 A1 WO 2005086485A1
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- WO
- WIPO (PCT)
- Prior art keywords
- encoded data
- image
- program
- decoding
- decoding device
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
Definitions
- the present invention relates to a coded data decoding device for decoding coded data that has been compressed and coded, and more particularly to a method of using instruction memory of a processor that controls decoding of coded data. It is.
- the MPEG stream is composed of a sequence layer starting with a sequence header, a GOP layer starting with a GOP (Group Of Pictures) header, a picture layer starting with a picture header, a slice layer starting with a slice header, and a macroblock layer. It consists of a total of six layers, the minimum unit and the block layer.
- the sequence layer specifies a screen format and the like, and is a series of screen groups having the same attribute.
- the GOP layer is the minimum unit of a screen group that serves as a reference for random access.
- the picture layer has attributes common to one screen.
- This picture is composed of three types of pictures, I, P, and B.
- the I picture is an intra-frame coded image
- the P picture is an inter-frame forward predictive coding image
- the B picture is an inter-frame bi-directional predictive coding image.
- the function of decoding audio is realized by software using a processor, and the function of decoding an image is realized by dedicated hardware (image decoder).
- An external memory (frame memory) is often provided for storing image data for decoding.
- An external memory for storing a plurality of audio decoding programs and image data is provided so as to be compatible with a plurality of audio compression coding schemes, and audio is stored based on the audio decoding programs stored in the instruction memory.
- An image / audio decoding apparatus which includes a processor that decodes image data, an image decoder that decodes image data, and an arbitration circuit that arbitrates access between the processor and the image decoder to an external memory. According to this device, when decoding an image, When using the image decoding data in the external memory and switching the audio decoding program, the audio decoding program in the external memory is loaded into the instruction memory. As a result, even if the number of types of programs for decoding compression-encoded audio increases, audio decoding can be performed without increasing the size of the instruction memory and the number of terminals (see Patent Document 1).
- Patent Document 1 JP-A-2002-278599
- the instruction memory is not a RAM (Random Access Memory) but a ROM (Random Access Memory).
- An object of the present invention is to reduce the capacity of an instruction memory used by a processor that controls the decoding of encoded data when reproducing compressed encoded data.
- an encoded data decoding apparatus decodes encoded data while dynamically replacing a program in an instruction memory during reproduction. More specifically, a program for decoding image encoded data and Z or audio encoded data is divided into module units, and a predetermined instruction memory transfer is performed. The control is performed such that the program is stored in the internal instruction memory for each unit and the encoded data is decoded.
- the capacity of the internal instruction memory can be reduced, and the increase in cost as a system can be suppressed.
- FIG. 1 is a block diagram showing a configuration example of an image coded data decoding device according to the present invention.
- FIG. 2 is a diagram showing a configuration of a program executed by a processor in FIG. 1.
- FIG. 3 is a diagram showing a program module arrangement in an internal instruction memory in FIG. 1.
- FIG. 4 is a timing chart showing an operation example of the decoding device in FIG. 1.
- FIG. 5 is a control flow chart of program replacement in the decoding device in FIG.
- FIG. 6 is another control flow chart of program replacement in the decoding device of FIG.
- FIG. 7 is a block diagram showing a configuration example of an image and audio encoded data decoding apparatus according to the present invention.
- FIG. 8 is a diagram showing a configuration of a program executed by a processor in FIG. 7.
- FIG. 9 is a diagram showing a program module arrangement in an internal instruction memory in FIG. 7.
- FIG. 10 is a timing chart showing an operation example of the decoding device in FIG. 7.
- FIG. 11 is a timing chart showing another operation example of the decoding device in FIG. 7.
- FIG. 12 is a diagram showing another configuration of a program executed by the processor in FIG. 7
- FIG. 13 is a timing chart showing an operation example of the decoding device in FIG. 7 when the program configuration in FIG. 12 is adopted.
- FIG. 1 shows a configuration example of an image encoded data decoding device according to the present invention.
- This device decodes MPEG image coding data in real time.
- reference numeral 10 denotes an image decoder that decodes image encoded data
- 11 executes only control of the image decoder 10, or performs partial decoding of image encoded data and control of the image decoder 10.
- a processor that does both, 12 is an internal instruction memory for storing a part of the program of the processor 11, and 13 is all of the programs of the processor 11 (excluding programs stored in the ROM area of the internal instruction memory 12).
- 14 is a frame memory for storing decoded data output from the image decoder 10. It is preferable that the image decoder 10, the processor 11, and the internal instruction memory 12 be configured as one system LSI.
- FIG. 2 shows a configuration of a program executed by processor 11 in FIG. According to Figure 2, the program is divided into four functional modules. That is, the first and second image decoding modules (VD1 and VD2) that actually decode the image encoded data, the thread switching of the first and second image decoding modules (VD1 and VD2), and the internal instruction memory There are a total of four modules: a control module that exchanges 12 programs, and a common routine module that is commonly used by the first and second image decoding modules (VD1, VD2).
- the first image decoding module (VD1) is a program module that performs decoding below the slice layer (SL: Slice Layer)
- the second image decoding module (VD2) is decoding program above the picture layer (PL: Picture Layer).
- FIG. 3 shows a program module arrangement in the internal instruction memory 12 in FIG. .
- the first image decoding module (VD1) and the second image decoding module (VD2) shown in FIG. 2 are replaced while a part of the RAM area (RAM3—RAM7) of the internal instruction memory 12 is replaced.
- the control module is located in the non-swap area (resident area: RAMI-RAM2) in the RAM area, and does not swap during playback.
- the common routine module is located in the ROM area (ROM1 to ROM3) of the internal instruction memory 12.
- 10, II, 12 and 13 represent I pictures, respectively, and IDL represents the idling state of the processor 11.
- the program of the second image decoding module (VD2) necessary at the start of decoding is read into the RAM 3—RAM 7 of the internal instruction memory 12. .
- the program of the first image decoding module (VD1) is read into the RAM 3—RAM 5 of the internal instruction memory 12.
- the second image decoding module (VD2) is required to decode II (PL), so the program of the second image decoding module (VD2) is internally stored. Read into instruction memory 12.
- the second image decoding module (VD2) is required to decode II (SL) and then to decode 12 (PL), so the program of the second image decoding module (VD2) is needed. Is loaded into RAM3—RAM7 of the internal instruction memory 12. Thereafter, the same operation is repeated to perform decoding.
- FIG. 5 is a control flow chart of the program replacement in this case.
- S501 when the processing is started in S500, it is determined in S501 whether or not the internal instruction memory 12 needs to be replaced. If the internal instruction memory 12 does not need to be replaced, the process proceeds to S505. Ends the processing. If it is determined in S501 that the internal instruction memory 12 needs to be replaced, then in S502, it is determined whether or not the sub-modules of the functional modules that need to be read have already been read into the internal instruction memory 12.
- FIG. 6 is a control flow chart of program replacement when the look-ahead method shown in FIG. 4 is adopted.
- the steps except for S602 and S603 in S600-S608 in FIG. 6 correspond to S500-S505 in FIG.
- the program is in the idling state in S602
- whether the program is in the idling state and whether the program can be read ahead can be determined by looking at the current execution state of the program. For example, if the decoding is completely completed and the processor 11 is in the idling state, no exception processing will be performed! / As long as the next decoding starts after a certain time, the program can be read ahead. It is possible.
- FIG. 7 shows an example of the configuration of an image and audio encoded data decoding apparatus according to the present invention.
- This apparatus decodes MPEG image encoding data and audio encoding data in real time. It is the same as FIG. 1 except that the processor 11 receives the voice coded data.
- FIG. 8 shows a configuration of a program executed by the processor 11 in FIG. See Figure 8 Then, the program is divided into five functional modules. That is, the audio decoding module (AD1) for decoding the audio encoded data is added to the first and second image decoding modules (VDl, VD2), the control module, and the common routine module described in FIG. You.
- AD1 the audio decoding module
- VDl the first and second image decoding modules
- VD2 the control module
- common routine module described in FIG. You.
- FIG. 9 shows a program module arrangement in the internal instruction memory 12 in FIG.
- the processor 11 also serves as a DSP, and that the encoded audio data is decoded by the processor 11, and the second image decoding module (VD2) and the audio decoding module (AD1) shown in FIG. It is used while replacing part of the RAM area (RAM6—RAM10) in the internal instruction memory 12.
- the control module and the first image decoding module (VD1) are located in the non-swappable area (resident area: RAMI-RAM5) in the same RAM area, and are not swapped during playback.
- the common routine module is located in the ROM area (ROM1-ROM3) of the internal instruction memory 12.
- FIG. 10 shows an operation example of the video and audio coded data decoding device of FIG. According to FIG. 10, first, in order to start the decoding of 10 (PL), the program of the second image decoding module (VD2) necessary at the start of decoding is read into the RAM 6—RAM 10 of the internal instruction memory 12. After that, the decoding of 10 (PL) is completed and the decoding of 10 (SL) is started.
- the program of the first image decoding module (VD1) is resident in RAM3—RAM5 of the internal instruction memory 12. Therefore, the audio decoding module (AD1) for decoding the audio code data required during the decoding period of 10 (SL) is read into the RAM 6—RAM 10 of the internal instruction memory 12.
- the processor 11 While decoding the 10 (SL), while the image decoder 10 is decoding the image encoded data, the processor 11 is released from the processing of the image encoded data. Processing can be performed.
- the second image decoding module (VD2) is required to decode II (PL).
- RAM6 of memory 1 2 Read into RAM10. Since the program of the first image decoding module (VD1) is resident in RAM3 to RAM5 of the internal instruction memory 12, when decoding of II (PL) is completed, during the decoding period of the next II (SL),
- the voice decoding module (AD1) for decoding the required voice code data is stored in RAM 6—R of the internal instruction memory 12. Read in advance to AM10. Thereafter, decoding is performed by repeating the same operation.
- one of the power decoding programs in which the decoding programs for the image-encoded data and the audio-encoded data are both replaced is stored in the RAM resident area or the ROM area. It is also possible to arrange and perform decoding by exchanging only one of the decoding programs of the image encoded data and the audio encoded data.
- FIG. 11 shows another example of the operation of the video / audio coding apparatus shown in FIG. According to FIG. 11, even during the instruction exchange, the processor 11 accesses and decodes a portion of the internal instruction memory 12 other than the submodule for which the instruction is exchanged.
- the control 1-1, 1-1-2, audio decoding 1-1-1, 1-5, and image decoding 1-1-1, 1-1 from RAMI to RAM10 of the internal instruction memory 12 are performed.
- Each sub-module of —3 is stored.
- the first image decoding module (VD1) is switched to the second image decoding module (VD2) (see state (2) in FIG. 11).
- the instruction switching to the second image decoding module (VD2) is performed from RAM8 to RAM12, but the audio decoding module (AD1) is stored from RAM3 to RAM7. Therefore, "the blocks of the internal instruction memory 12 are arranged in a physically divided state, and the bus to the processor 11 and the bus to the external instruction memory 13 are separately secured.
- the internal instruction memory 12 satisfies the condition that one performs the instruction replacement while the other performs the normal access operation, as shown in FIG. It is possible to perform the audio decoding process in parallel during the replacement of the instruction to the second video decoding module (VD2). As a result, the processing performance of the processor 11 can be sufficiently exhibited.
- FIG. 12 shows another configuration of the program executed by the processor 11 in FIG. According to Figure 8, the program is divided into five functional modules. That is, the first and second image decoding modules (VD1, VD2) described in FIG. 2 and the control module are provided with a first audio decoding module (AD1 ), And a second audio decoding module (AD2) for decoding the second type of audio encoding data. Is added.
- the first audio decoding module (AD1) conforms to the first audio compression encoding standard
- the second audio decoding module (AD2) conforms to the second audio compression encoding standard.
- FIG. 13 shows an operation example of the video / audio coding data decoding apparatus of FIG. 7 when the program configuration of FIG. 12 is adopted.
- the state (1) in FIG. 13 is the same as the state (1) in FIG.
- the first audio decoding module (AD1) stored in RAM3 to RAM7 of the internal instruction memory 12 is switched to the second audio decoding module (AD2) (see state (3) in FIG. 13).
- the reproduction of the audio is first stopped (see the display (2) in FIG. 13), and then the processing is shifted to the image decoding, and then the program for the audio decoding is replaced.
- the division mode of the force program that has been described with reference to FIGS. 1 to 13 in the embodiment of the present invention is not limited to the examples shown in FIGS. 2, 8, and 12.
- the program replacement timing can also be arbitrarily selected in accordance with the decoding control method.
- the external instruction memory 13 and the frame memory 14 are described as separate memories. These may be physically used as a single memory.
- the present invention is not limited to ISOZIEC11172, 13818, and can be applied to any compression coding scheme such as ISOZIEC14496.
- the encoding / decoding data decoding device includes an internal instruction memory. Can be reduced, and is useful as a digital television or the like.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/592,109 US20070206870A1 (en) | 2004-03-09 | 2004-12-08 | Encoded Data Decoding Apparatus |
EP04821718A EP1732327A1 (en) | 2004-03-09 | 2004-12-08 | Encoded data decoding apparatus |
JP2006510614A JPWO2005086485A1 (ja) | 2004-03-09 | 2004-12-08 | 符号化データ復号装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004-066190 | 2004-03-09 | ||
JP2004066190 | 2004-03-09 |
Publications (1)
Publication Number | Publication Date |
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WO2005086485A1 true WO2005086485A1 (ja) | 2005-09-15 |
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ID=34918312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2004/018261 WO2005086485A1 (ja) | 2004-03-09 | 2004-12-08 | 符号化データ復号装置 |
Country Status (5)
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US (1) | US20070206870A1 (ja) |
EP (1) | EP1732327A1 (ja) |
JP (1) | JPWO2005086485A1 (ja) |
CN (1) | CN1926871A (ja) |
WO (1) | WO2005086485A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010525653A (ja) * | 2007-04-17 | 2010-07-22 | ヒューマクスカンパニーリミテッド | ビットストリーム復号化装置及び方法 |
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US20100063825A1 (en) * | 2008-09-05 | 2010-03-11 | Apple Inc. | Systems and Methods for Memory Management and Crossfading in an Electronic Device |
US20170188033A1 (en) * | 2015-12-23 | 2017-06-29 | Mediatek Inc. | Method and Apparatus of Bandwidth Estimation and Reduction for Video Coding |
Citations (10)
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JPS61169947A (ja) * | 1985-01-23 | 1986-07-31 | Fujitsu Ltd | ペ−ジ制御方式 |
JPH01112423A (ja) * | 1987-10-27 | 1989-05-01 | Fujitsu Ltd | オーバレイ制御方式 |
JPH0293829A (ja) * | 1988-09-30 | 1990-04-04 | Mitsubishi Electric Corp | データ処理装置 |
JPH03265932A (ja) * | 1990-03-15 | 1991-11-27 | Nec Corp | インストラクションメモリ制御方式 |
JPH10111792A (ja) * | 1996-10-03 | 1998-04-28 | Nec Corp | 画像処理装置 |
JPH10232783A (ja) * | 1997-02-20 | 1998-09-02 | Matsushita Electric Ind Co Ltd | 映像表示装置 |
JP2000184302A (ja) * | 1998-12-11 | 2000-06-30 | Sony Corp | 情報処理装置および方法、並びに提供媒体 |
JP2000235494A (ja) * | 1999-02-12 | 2000-08-29 | Kobe Steel Ltd | ディジタル信号処理装置 |
JP2002159006A (ja) * | 2000-11-16 | 2002-05-31 | Seiko Epson Corp | 演算補助回路 |
JP2002278599A (ja) * | 2001-03-22 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 映像音声復号装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW380358B (en) * | 1996-12-10 | 2000-01-21 | Whitaker Corp | Surface mount pad |
-
2004
- 2004-12-08 CN CNA2004800423640A patent/CN1926871A/zh active Pending
- 2004-12-08 US US10/592,109 patent/US20070206870A1/en not_active Abandoned
- 2004-12-08 EP EP04821718A patent/EP1732327A1/en not_active Withdrawn
- 2004-12-08 JP JP2006510614A patent/JPWO2005086485A1/ja not_active Withdrawn
- 2004-12-08 WO PCT/JP2004/018261 patent/WO2005086485A1/ja not_active Application Discontinuation
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61169947A (ja) * | 1985-01-23 | 1986-07-31 | Fujitsu Ltd | ペ−ジ制御方式 |
JPH01112423A (ja) * | 1987-10-27 | 1989-05-01 | Fujitsu Ltd | オーバレイ制御方式 |
JPH0293829A (ja) * | 1988-09-30 | 1990-04-04 | Mitsubishi Electric Corp | データ処理装置 |
JPH03265932A (ja) * | 1990-03-15 | 1991-11-27 | Nec Corp | インストラクションメモリ制御方式 |
JPH10111792A (ja) * | 1996-10-03 | 1998-04-28 | Nec Corp | 画像処理装置 |
JPH10232783A (ja) * | 1997-02-20 | 1998-09-02 | Matsushita Electric Ind Co Ltd | 映像表示装置 |
JP2000184302A (ja) * | 1998-12-11 | 2000-06-30 | Sony Corp | 情報処理装置および方法、並びに提供媒体 |
JP2000235494A (ja) * | 1999-02-12 | 2000-08-29 | Kobe Steel Ltd | ディジタル信号処理装置 |
JP2002159006A (ja) * | 2000-11-16 | 2002-05-31 | Seiko Epson Corp | 演算補助回路 |
JP2002278599A (ja) * | 2001-03-22 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 映像音声復号装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010525653A (ja) * | 2007-04-17 | 2010-07-22 | ヒューマクスカンパニーリミテッド | ビットストリーム復号化装置及び方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1926871A (zh) | 2007-03-07 |
JPWO2005086485A1 (ja) | 2008-01-24 |
US20070206870A1 (en) | 2007-09-06 |
EP1732327A1 (en) | 2006-12-13 |
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