WO2005074272A1 - エンコード中に抽出画像を外部に送信するビデオエンコーダ - Google Patents
エンコード中に抽出画像を外部に送信するビデオエンコーダ Download PDFInfo
- Publication number
- WO2005074272A1 WO2005074272A1 PCT/JP2004/000923 JP2004000923W WO2005074272A1 WO 2005074272 A1 WO2005074272 A1 WO 2005074272A1 JP 2004000923 W JP2004000923 W JP 2004000923W WO 2005074272 A1 WO2005074272 A1 WO 2005074272A1
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- WIPO (PCT)
- Prior art keywords
- bank
- video
- video encoder
- video data
- data
- Prior art date
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- 238000012545 processing Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 45
- 230000005540 biological transmission Effects 0.000 claims description 32
- 238000012546 transfer Methods 0.000 claims description 13
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 230000007704 transition Effects 0.000 description 9
- 102100021568 B-cell scaffold protein with ankyrin repeats Human genes 0.000 description 7
- 101000971155 Homo sapiens B-cell scaffold protein with ankyrin repeats Proteins 0.000 description 7
- 230000005236 sound signal Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101000969688 Homo sapiens Macrophage-expressed gene 1 protein Proteins 0.000 description 1
- 102100021285 Macrophage-expressed gene 1 protein Human genes 0.000 description 1
- 101100269836 Mus musculus Ank1 gene Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
- H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
- H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/78—Television signal recording using magnetic recording
- H04N5/781—Television signal recording using magnetic recording on disks or drums
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/82—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback the individual colour picture signal components being recorded simultaneously only
- H04N9/8205—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback the individual colour picture signal components being recorded simultaneously only involving the multiplexing of an additional signal and the colour video signal
Definitions
- Video encoder for transmitting an extracted image to an external device during encoding
- the present invention generally relates to a video encoder that encodes video data in real time, and more particularly, to a video encoder having an image extraction function of video data.
- the input analog NTSC video signal is MPEG-encoded, and the encoded video data is recorded on a hard disk or the like.
- the input analog NTSC video signal is first converted to the ITU-R656 format by the NTSC decoder, and the converted video data is supplied to an MPEG2 encoder.
- the supplied video data is written to a frame memory provided outside the MPEG2 encoder via a frame synchronizer in the MPEG2 encoder.
- a plurality of (for example, three) banks are provided in the frame memory, and new data is overwritten on the bank in which the oldest data is stored by specifying the write destination bank in order.
- the input analog audio signal is converted to the I2S format by an audio ADC (analog-to-digital converter), and the converted audio data is supplied to the MPEG2 encoder.
- an audio ADC analog-to-digital converter
- the oldest bank frame data is read from the frame memory by the MPEG2 encoder.
- the read frame data is transferred to the MPEG2 video encoding unit via the frame synchronizer in the MPEG2 encoder, and encoded into the MPEG2 video MP @ ML format.
- the audio data is encoded into MPEG 1 audio layer 2 format data.
- the multiplexed video stream and audio stream are multiplexed into the MPEG2 PS format by the system multiplexer in the MPEG2 encoder, and are multiplexed from the dedicated 8-bit port to the outside of the MPEG2 encoder as a multiplexed stream. Is output.
- the stream output from the MPEG2 encoder is recorded on the hard disk via IDE-I / F.
- thumbnail image may be used to manage these files. For example, when a list of files corresponding to each video content is displayed to the user, displaying the thumbnail image in association with the file allows the user to easily specify the file content.
- thumbnail image is generated by thinning out image data of 720 ⁇ 480 pixels, which is an effective image area of video data in the ITU-R 656 format, to 360 ⁇ 240 pixels.
- a microcomputer stored in a hard disk recorder or the like creates such thumbnail images for the purpose of managing file information, and
- thumbnail image is read from one of the three banks while writing and reading operations are being performed sequentially on the three banks for normal encoding processing. It is necessary to read out the image for creation separately from the encoding process.
- NTSC video data is 33 ms per frame, and the bank to read for thumbnails is written to the remaining two banks. If it is not read during 66 ms, it will be overwritten. Therefore, it is necessary to give priority to the process of reading the thumbnail image, which requires special control and affects the encoding operation.
- an object of the present invention is to provide an MPEG encoder capable of extracting image data from video data and transferring the image data to a microcomputer without affecting the encoding operation. Disclosure of the invention
- the video encoder temporarily stores externally supplied video data in a plurality of memory banks repeatedly selected in a predetermined order, and sequentially reads out video data from the plurality of memory banks repeatedly selected in a predetermined order.
- the frame data of one switched memory bank is overwritten by executing a bank switching process of switching one memory bank of the plurality of memory banks to a different memory bank from the plurality of memory banks. It is possible to keep without doing. Therefore, when the held image data is transferred by the subsequent data transmission processing, the data transmission processing is executed at a convenient timing so as not to affect the encoding processing.
- the data transmission process may be performed a plurality of times in units of data transfer. This makes it possible to extract image data from video data and transfer it outside without affecting the encoding operation.
- FIG. 1 is a block diagram showing a configuration of a hard disk recorder to which the present invention is applied.
- FIG. 2 is a block diagram showing a configuration of the MPEG2 encoder according to the present invention.
- FIG. 3 is a flowchart showing a process of securing and transmitting thumbnail data according to the present invention.
- FIG. 4 is a state transition diagram of the hard disk recorder.
- FIG. 5 is a diagram for explaining the bank switching process.
- FIG. 6 is a diagram for explaining the bank switching process.
- FIGS. 7A and 7B are diagrams showing the execution states of the encode processing and the thumbnail data transmission processing, respectively.
- FIG. 8 is a block diagram showing another configuration example of the hard disk recorder to which the present invention is applied.
- FIG. 1 is a block diagram showing a configuration of a hard disk recorder to which the present invention is applied.
- the present invention is not limited to a hard disk recorder, but may be, for example, a DV D recorder.
- the present invention can be generally applied to a device that encodes and records an analog video signal or digital video data supplied in real time.
- the MPEG 2 encoder 10 the microcomputer 12, the RAM 13, the ROM 14, the IDE-I / F 17, and the MPEG 2 decoder 19 are connected to each other via a bus 22, which is a parallel bus.
- FIG. 2 is a block diagram showing a configuration of the MPEG 2 encoder 10 according to the present invention.
- the MPEG 2 encoder 10 shown in FIG. 2 includes an SDRAM controller 31, a frame synchronizer 32, an MPEG 2 video encoding unit 33, a system multiplexer 34, a host IZF 35, and a CPU 36.
- the host I / F 35 is connected to the microcomputer 12 via a bus 22 (Fig. 1), which is a parallel bus. Connected to. As described below, in another embodiment, the host I ZF 35 may be connected to the microcomputer 12 via a serial IF (serial interface).
- serial IF serial interface
- the input analog NTSC video signal is first converted into the ITU-R656 format by the NTSC decoder 15, and the converted video data is supplied to the MPEG2 encoder 10.
- the supplied video data is written to the frame memory 11 provided outside the MPEG2 encoder via the frame synchronizer 32 and the SDRAM controller 31 in the MPEG2 encoder 10.
- a plurality of (for example, three) banks are provided in the frame memory 11, and a new data is overwritten on a bank in which the oldest data is stored by specifying a bank to be written in order. .
- the input analog audio signal is converted into the I2S format by the audio ADC 16, and the converted audio data is supplied to the MPEG2 encoder 10.
- the frame data of the oldest bank among the frame data written in the plurality of banks of the frame memory 11 is read from the frame memory 11 by the MPEG 2 encoder 10.
- the read frame data is transferred to the MPEG2 video encoder unit 33 via the SDRAM controller 31 and the frame synchronizer 32 in the MPEG2 encoder 10 and converted to the MPEG2 video MP @ ML format. Is executed.
- the audio data is encoded into MPEG 1 audio layer 2 format data.
- the video stream and audio stream thus obtained are multiplexed into the MPEG2PS format by the system multiplexer 34 in the MPEG2 encoder 10 and multiplexed from an 8-bit dedicated port.
- the stream is output to the outside of the MPEG 2 encoder 10.
- the operation of the MPEG2 encoder 10 is controlled by supplying an encoder open platform command ⁇ stop command and the like via the microcomputer 12 host IZF35. Also, multiple banks are provided in the frame memory 11 Thus, even if the frame rate of the video signal input is not synchronized with the frame rate of the encoding process by the MPEG2 video encoding unit 33, the difference in the frame rate can be absorbed by the frame synchronizer 32. Has become.
- the stream output from the MPEG2 encoder 10 is recorded on a hard disk drive (HDD) 18 via an IDE-I / F 17.
- the IDE I / F 17 DMA-transfers the stream output from the 8-bit port of the MPEG 2 encoder 10 to the hard disk drive (HDD) 18.
- a transfer start instruction, a stop instruction, an address designation, and the like are performed by register setting by the microcomputer 12.
- the IDE-I / F 17 is connected to the bus 22 so that the microcomputer 12 can access a predetermined address of the hard disk drive (HDD) 18 via the IDE-IZF 17.
- HDD hard disk drive
- the IDE-IZF 17 DMA-transfers the stream recorded on the hard disk drive (HDD) 18 to the MPEG 2 decoder 19.
- a transfer start instruction, a stop instruction, an address designation, and the like are performed by register setting by the microcomputer 12.
- the MPEG2 decoder 19 separates (demultiplexes) the supplied multiplexed stream, and generates a video stream (MPEG2MP @ ML) and an audio stream (MPEG1 layer 2).
- the MPEG2 decoder 19 further decodes the video stream and the audio stream, and outputs the video signal in the NTSC format and outputs the audio data in the I2S format.
- the video signal output from the MPEG2 decoder 19 is amplified by the video amplifier 20 and output as an analog NTSC video signal for reproduction.
- the audio data output from the MPEG 2 decoder 19 is converted by the audio DAC 21 and output as an analog audio signal for reproduction.
- FIG. 3 is a flowchart showing a process of securing and transmitting thumbnail data according to the present invention.
- the processing in Fig. 3 is mainly performed by the CPU 36 of the MPEG2 encoder 10. More executed. That is, the CPU 36 operates as a control unit that controls the process of securing and transmitting thumbnail data.
- step S1 of FIG. 3 an initialization process is performed.
- the frame synchronizer 32 includes a register for storing pointers pointing to a plurality of banks of the frame memory 11, respectively.
- the initialization processing includes processing for initializing the contents of the register.
- step S2 it is determined whether or not there is a state transition.
- the process proceeds to step S3. If there is no state transition, the process proceeds to step S4.
- FIG. 4 is a state transition diagram of the hard disk recorder.
- the hard disk recorder has a stopped state 41 and an encoding state 42, and the encoding state 42 further includes a state 43 during transmitting thumbnails and a thumbnail non-display state.
- State 4 4 and power S exist.
- the hard disk recorder is in the stopped state 41.
- a state transition is performed from the stopped state 41 to the encoding state 42 in step S3.
- step S4 it is determined whether or not the state is encoding state 42. If the state is the encod- ing state 42, the process proceeds to step S5. If the state is not encoding state 4 2, the process proceeds to step S 13.
- step S5 it is determined whether or not the power is the state 43 during thumbnail transmission. If the thumbnail is being transmitted 43, the process proceeds to step S9. If the thumbnail is not being transmitted 43, the process proceeds to step S6.
- step S6 it is determined whether or not there is a thumbnail transmission instruction.
- the thumbnail transmission instruction detects when the picture of the input video signal has changed greatly (scene change) within the MPEG 2 encoder 10 and uses this as a trigger.
- an instruction supplied from the microcomputer 12 to the host I / F 35 may be triggered.
- the MPEG2 encoder 10 may spontaneously generate a thumbnail command at regular intervals.
- step S7 If there is no thumbnail transmission instruction, the process proceeds to step S12.
- step S7 a state transition is instructed and the state transits to the state 43 during thumbnail transmission.
- step S8 a bank switching process is performed.
- FIG. 5 and FIG. 6 are diagrams for explaining the bank switching process.
- the frame synchronizer 32 is provided with a register storing pointers pointing to a plurality of banks of the frame memory 11. These registers are a BANK0 start address register, a BANK1 start address register, a BANK2 start address register, and a latest write bank register.
- the latest write bank register indicates a bank to which the most recent frame data is written among frame data that has been written to the frame memory 11 and has not yet been encoded.
- the head address of each bank is set to the following value.
- the CPU 36 stores 0X0839A400, which is the head address of the reserved bank, in the variable BANK-RESERVED.
- the CPU 36 reads the contents of the latest write bank register to detect the latest bank, and replaces the value of BANK—RESERVED with the value of the first address register of the latest write bank. .
- the thumbnail transmission instruction is issued when BANK0 is in the initial state shown in Fig. 5 and BANK0 is indicated in Fig. 5
- the start address of the bank stored in each register is set to a value as shown in FIG.
- step S12 in FIG. 3 a write process to the hard disk drive (HDD) 18 is executed.
- the encoded video data and audio data are recorded on the hard disk drive (HDD) 18 as a multiplexed stream.
- step S13 it is determined whether or not the power of the hard disk recorder is off. If the power is OFF, the process ends. If the power is not OFF, the process returns to step S2.
- step S9 thumbnail data transmission processing is executed.
- the frame data whose head address is the address specified in BANK-RES ERVED is transmitted to the microcomputer 12, for example, every four bytes.
- the processing in step S10 ends. After that, when the next thumbnail data transmission process is executed, the next 4 bytes of data are transmitted.
- step S10 it is determined whether or not the power has been completely transmitted. All data Is completed, the state is changed to a state 44 in which no thumbnail is being transmitted in step S11 according to a state transition instruction.
- the frame data of a certain bank is held by the bank switching process, and the held image data is transferred to the microcomputer 12 by a small data transfer unit that hardly affects the encoding process. Sequentially. This makes it possible to extract the image data from the video data and transfer it to the microcomputer 12 without affecting the encoding operation.
- the microcomputer 12 generates a thumbnail image by thinning out the received data and stores the thumbnail image in a memory such as the RAM 13. Also, instead of transmitting all the data of one image selected as described above from the MPEG 2 encoder 10 to the microcomputer 12, the image data is thinned out first and the thumbnail image is sent to the microphone computer 12. You may send it. Also, the data may be transmitted to the microcomputer 12 after performing some conversion processing such as filtering.
- FIG. 7A and 7B are diagrams showing the execution state of the encoding process and the thumbnail data transmission process, respectively.
- the encoding process by the CPU 36 and the MPEG 2 video encoder unit 33 occupies, for example, an average of 90% of the CPU processing time.
- the horizontal axis represents time, and the shaded portion indicated as “in process” occupies 90% of the entire time. Encoding processing needs to be performed so as to follow video data and audio data input in real time, and must be processed with priority over other processing.
- thumbnail data transmission processing must be completed within 66 ms (or shorter time) with the remaining 10% of the CPU processing excluding the hatched part during the encoding processing shown in FIG. 7A. Nanare. For example, if the thumbnail transmission process requires a CPU process of 15% X 66 ms, transmission is not possible in the processing state shown in Fig. 7A.
- the frame data of the bank is held by the bank switching process, and the held image data is sequentially transferred to the microcomputer in a small data transfer unit which hardly affects the encoding process. Therefore, after the bank switching process is executed, the time limit of 66 ms described above is eliminated, so that the occupation rate of the CPU process used for the thumbnail data transmission process can be reduced. For example, even if the thumbnail data transmission processing requires a total of 15% X 66 ms of CPU processing, the CPU processing of 1.5% X 660 ms is executed by dividing it into 10 transmission processings That's all we need to do.
- FIG. 8 is a block diagram showing another configuration example of the hard disk recorder to which the present invention is applied.
- a three-bank configuration is used in which writing and reading operations are sequentially performed on three banks for normal encoding processing, and one bank is used for thumbnail image transmission processing. ing.
- three banks are used for normal write and read operations for normal encoding processing.
- the read operation may be performed. Even with such a configuration, it becomes possible to extract image data from video data and transfer it to the microcomputer without affecting the encoding operation, as in the above embodiment.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Management Or Editing Of Information On Record Carriers (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004800392534A CN100562086C (zh) | 2004-01-30 | 2004-01-30 | 在编码器中向外部发送提取图像的视频编码器 |
JP2005517361A JP4250170B2 (ja) | 2004-01-30 | 2004-01-30 | エンコード中に抽出画像を外部に送信するビデオエンコーダ |
EP20040706874 EP1711010B1 (en) | 2004-01-30 | 2004-01-30 | Video encoder transmitting extracted image outside during encoding |
PCT/JP2004/000923 WO2005074272A1 (ja) | 2004-01-30 | 2004-01-30 | エンコード中に抽出画像を外部に送信するビデオエンコーダ |
DE200460030045 DE602004030045D1 (de) | 2004-01-30 | 2004-01-30 | Videocodierer, der während der codierung ein extrahiertes bild nach aussen sendet |
US11/446,147 US7577197B2 (en) | 2004-01-30 | 2006-06-05 | Video encoder transmitting extracted image to exterior during encoding process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/000923 WO2005074272A1 (ja) | 2004-01-30 | 2004-01-30 | エンコード中に抽出画像を外部に送信するビデオエンコーダ |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/446,147 Continuation US7577197B2 (en) | 2004-01-30 | 2006-06-05 | Video encoder transmitting extracted image to exterior during encoding process |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005074272A1 true WO2005074272A1 (ja) | 2005-08-11 |
Family
ID=34816578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/000923 WO2005074272A1 (ja) | 2004-01-30 | 2004-01-30 | エンコード中に抽出画像を外部に送信するビデオエンコーダ |
Country Status (6)
Country | Link |
---|---|
US (1) | US7577197B2 (ja) |
EP (1) | EP1711010B1 (ja) |
JP (1) | JP4250170B2 (ja) |
CN (1) | CN100562086C (ja) |
DE (1) | DE602004030045D1 (ja) |
WO (1) | WO2005074272A1 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537923A (ja) * | 1991-07-26 | 1993-02-12 | Fujitsu Ltd | 動き補償予測の2段階ブロツクマツチング探索におけるメモリの使用方法 |
JPH10210481A (ja) * | 1997-01-23 | 1998-08-07 | Sharp Corp | メモリ制御装置 |
JPH1198507A (ja) * | 1997-09-19 | 1999-04-09 | Toshiba Corp | 画像符号化装置 |
US6044206A (en) | 1997-10-14 | 2000-03-28 | C-Cube Microsystems | Out of order instruction processing using dual memory banks |
EP1107613A2 (en) | 1999-12-01 | 2001-06-13 | Sony Corporation | Picture recording apparatus and methods |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6148035A (en) * | 1994-12-29 | 2000-11-14 | Sony Corporation | Processing of redundant fields in a moving picture to achieve synchronized system operation |
JPH10257407A (ja) * | 1997-03-14 | 1998-09-25 | Toshiba Corp | 受信機 |
JP2002077803A (ja) * | 2000-08-24 | 2002-03-15 | Hitachi Ltd | 映像情報記録装置及び撮像装置 |
JP4541610B2 (ja) * | 2001-09-17 | 2010-09-08 | キヤノン株式会社 | 画像処理装置、画像処理方法、プログラム、記憶媒体 |
JP2003186740A (ja) | 2001-12-19 | 2003-07-04 | Matsushita Electric Ind Co Ltd | メモリ制御装置、及びメモリ制御方法 |
WO2005002224A1 (ja) * | 2003-06-27 | 2005-01-06 | Fujitsu Limited | 字幕等の情報を含むビデオ信号の処理回路 |
-
2004
- 2004-01-30 EP EP20040706874 patent/EP1711010B1/en not_active Expired - Fee Related
- 2004-01-30 CN CNB2004800392534A patent/CN100562086C/zh not_active Expired - Fee Related
- 2004-01-30 JP JP2005517361A patent/JP4250170B2/ja not_active Expired - Fee Related
- 2004-01-30 DE DE200460030045 patent/DE602004030045D1/de not_active Expired - Lifetime
- 2004-01-30 WO PCT/JP2004/000923 patent/WO2005074272A1/ja not_active Application Discontinuation
-
2006
- 2006-06-05 US US11/446,147 patent/US7577197B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0537923A (ja) * | 1991-07-26 | 1993-02-12 | Fujitsu Ltd | 動き補償予測の2段階ブロツクマツチング探索におけるメモリの使用方法 |
JPH10210481A (ja) * | 1997-01-23 | 1998-08-07 | Sharp Corp | メモリ制御装置 |
JPH1198507A (ja) * | 1997-09-19 | 1999-04-09 | Toshiba Corp | 画像符号化装置 |
US6044206A (en) | 1997-10-14 | 2000-03-28 | C-Cube Microsystems | Out of order instruction processing using dual memory banks |
EP1107613A2 (en) | 1999-12-01 | 2001-06-13 | Sony Corporation | Picture recording apparatus and methods |
Non-Patent Citations (1)
Title |
---|
See also references of EP1711010A4 |
Also Published As
Publication number | Publication date |
---|---|
DE602004030045D1 (de) | 2010-12-23 |
EP1711010A4 (en) | 2009-03-25 |
JP4250170B2 (ja) | 2009-04-08 |
CN1902924A (zh) | 2007-01-24 |
JPWO2005074272A1 (ja) | 2007-08-23 |
US7577197B2 (en) | 2009-08-18 |
US20060222082A1 (en) | 2006-10-05 |
EP1711010B1 (en) | 2010-11-10 |
EP1711010A1 (en) | 2006-10-11 |
CN100562086C (zh) | 2009-11-18 |
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