Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
  • G01R31/2836—Fault-finding or characterising
  • G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
  • G01R31/2841—Signal generators

Definitions

• This invention relates generally to circuitry for testing electrical components and circuits, and more particularly the invention relates to current pulse circuitry for use in such testing.
• the present invention is directed to facilitating fast current transition from 0 to A through DUT with transition time, tr, substantially shorter than the related pulse duration, t p , t n , and with an acceptable minimal overshoot.
• a charge boost circuit is provided to facilitate the rapid recharge of parasitic capacitance associated with a DUT when current is re-applied through the DUT. Short bursts of current are provided during the transitions of the shunt transistor from on state to off state, with the magnitude of the charging current being greater than the magnitude of the pulsed current.
• a current limiter prevents overcharging of the parasitic capacitance thereby avoiding unacceptable overshooting in the resulting current pulse waveform.
• Fig. 1 illustrates bipolar and unipolar current pulses for use in testing electronic devices.
• Fig. 2 illustrates a conventional pulse current generator for a DUT.
• FIG. 3 illustrates a pulsed current generator in accordance with the invention.
• Fig. 4 illustrates one embodiment of a pulse generator and charge booster circuit in accordance with the invention.
• Fig. 5 illustrates another embodiment of a pulse generator and charge booster circuit in accordance with the invention.
• FIG. 6 illustrates another embodiment of a charge booster circuit in accordance with the invention.
• Fig. 7 illustrates waveforms in the circuit of Fig. 5 with proper setting and improper setting, respectively, for charge boosting.
• Fig. 3 corresponds to the circuit of Fig. 2 with a booster circuit 10 in accordance with the invention for providing short bursts of current during the transitions from the on to off state of shunt transistor Qs.
• booster circuit 10 provides current through switch SI which facilitates the charging of parasitic capacitor Co. Since the booster current is much higher than the current Idc from the current source, recharging of the parasitic capacitor is facilitated.
• Booster circuit 10 and switch SI respond to control circuitry 12 and the control voltage at node P for shunt transistor Qs.
• Fig. 4 is a schematic of one embodiment of the pulsed current generator of Fig. 3 which further illustrates booster circuit 10 and control circuit 12.
• timing generator at terminal P is connected to the gate of the main shunt transistor Qs via two serially connected buffers 20, 22 with each buffer inverting its input signal while adding a small delay (td).
• the resulting waveforms at PI, P2 and timing generator signal at P are all shown in the figure.
• the coupling gate resistor Rx is not critical and is commonly added just to avoid direct coupling between the transistor gate and the driving signal.
• the rest of the circuit forms the booster shown at 10.
• the path of the current injected by the booster into the output node C comprises NMOS transistor Qn and PMOS transistor Qp, capacitor Cba and resistor Ry.
• Resistor Ry sets an upper bound to the boosting current to avoid overheating and large overshoots.
• Capacitor Cba is sufficiently large (about one ⁇ F or more) to assure constant (DC) voltage at the common source node S, even when strong boosting action is required.
• Proper operation of the booster is based on an unambiguous knowledge of the actual conditions at node C in real time and comparing to an intended target.
• the target is simply a resulting "high" voltage level at node C being the same as the resulting voltage level under similar DC operation.
• Idc is set to the required level and the resulting voltage at node C is measured and acquired.
• the timing generator is activated and the resulting voltage at C is measured, using a peak detector which acquires the highest level of the measured waveform (peak detector not shown).
• peak detector peak detector not shown
• Vtn is positive for enhancement devices and negative for depletion
• Vtp is negative for enhancement and positive for depletion.
• depletion NMOS transistor (Qn) and enhancement PMOS transistor (Qp) is selected and assuming that their absolute values are about the same (i.e.
• an extra "safety margin" of a few tenths of a volt may be added as part of circuit adjustment during production.
• Vxi VYI + ⁇ , where ⁇ is the pre-adjusted constant described above).
• Figs. 5 and 6 Two other embodiments, where the above is achieved with one adjustable voltage source and another fixed source, are shown in Figs. 5 and 6, respectively. Similar to capacitor Cba, capacitors Cbb and Cbc are sufficiently large to assure DC conditions at Yl and at XI, respectively. Resistors Rd are added to avoid loading the operational amplifiers with large capacitance.
• VY is connected only to the gate of Qn, where only negligible leakage current flows, VY is practically equal to VYI and resistor Re is not very significant.
• the situation is different at the gate of Qp (point X), where under pulsed operation the waveform differs significantly from Vxi and the specific values of Rf, Ct and even the intrinsic PMOS input capacitance Cip are important.
• Vxi - VYI Vb [Re (Rp - ⁇ )] / [Ra (Ra - ⁇ + Rp)] ⁇ ⁇
• VYI is Vbst, the variable voltage source, while any combination of two available fixed sources provides the required difference ⁇ .
• the difference can very between -
• Pre-setting the required value of ⁇ which assures no DC current flow through Qp the actual boosting can take place.
• the voltage at point C is then acquired from the peak detector and stored as reference (hereunder "Vcdc"). Since Vxi (and VYI respectively) are low enough to prevent boosting current, engaging SI and applying the timing generator at P will turn Qs and Qd on and off accordingly with no boosting current through Qp.
• the peak detector reading (Vcp) is acquired and compared to Vcdc.
• Vcp Vcdc (very unlikely) then SI should be disengaged.
• Vcp ⁇ Vcdc boosting is needed.
• Vbst is increased until the resulting Vcp exceeds Vcdc.
• Vcp is decreased and the process is repeated in a converging manner to the point where any further change has negligible effect. From here on, the required pulsing action is in effect. For sufficiently long pulses, the voltage at point C will gradually "converge" to the required level Vcdc even without boosting; however, as the related time constant is significantly longer than short pulses (typically for t ⁇ 500 nS), such "convergence" provides little help arid efficient boosting is necessary.
• the waveforms in Fig. 7 provide more details as to the waveforms at points PI, P2, X and C (refer to Fig. 5).
• the left hand side shows proper setting of ⁇ (Vxi - VYI), leading to the expected output waveform.
• the right hand side shows insufficient boosting and the resulting improper output waveform due to excessive magnitude of ⁇ .

Landscapes

• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Dc-Dc Converters (AREA)
• Testing Of Individual Semiconductor Devices (AREA)
• Tests Of Electronic Circuits (AREA)
• Generation Of Surge Voltage And Current (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=34653271

Family Applications (1)

Country Status (8)

Families Citing this family (10)

Citations (1)

Family Cites Families (14)

• 2003
  • 2003-12-10 US US10/734,002 patent/US7049713B2/en not_active Expired - Lifetime
• 2004
  • 2004-12-02 AT AT04812995T patent/ATE423324T1/de not_active IP Right Cessation
  • 2004-12-02 WO PCT/US2004/040591 patent/WO2005060568A2/en not_active Ceased
  • 2004-12-02 DE DE602004019562T patent/DE602004019562D1/de not_active Expired - Lifetime
  • 2004-12-02 JP JP2006543900A patent/JP4520998B2/ja not_active Expired - Lifetime
  • 2004-12-02 EP EP04812995A patent/EP1692056B1/en not_active Expired - Lifetime
  • 2004-12-02 CN CNB2004800413013A patent/CN100550624C/zh not_active Expired - Fee Related
  • 2004-12-07 TW TW093137793A patent/TWI342959B/zh not_active IP Right Cessation

Patent Citations (1)

Also Published As

Similar Documents

Legal Events