Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/394—Routing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Layout of the interconnection structure
  • H01L23/5286—Arrangements of power or ground buses
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to integrated circuit designs in general, and, in particular, to a method and apparatus for distributing power in an integrated circuit having voltage islands. Still more particularly, the present invention relates to a method and apparatus for performing power routing on a voltage island within an integrated circuit chip.
• VDD g chip-wide power source
• VDDj-VDD- n voltage island power sources
• VDDg and VDDj-VDD n can be switched on and off in accordance with the operational demands of the integrated circuit.
• VDD g and VDDj-VDD n are supplied to a voltage island from separate chip- wide power sources.
• a voltage island requires an isolated power supply grid structure from the remaining portion of a chip power grid.
• off-chip and on-chip power supply sources need to be routed accordingly.
• off-chip power supply sources for voltage islands originate at either C4 ball grid array locations or wirebond locations, and on-chip power supply sources for voltage islands originate at voltage regulator macro pins.
• the problems that need to be overcome include how not to require an overabundance of power wires to anticipate the power needs of unplaced voltage islands, how not to restrict placement of power service terminals contained within the voltage island circuits because of a locally sparse power grid, how to avoid electromigration and IR drop violations and how to avoid blocked pins and other wireability issues.
• the present disclosure provides an improved method for performing power routing on a voltage island within an integrated circuit chip.
• a first power grid is generated for a voltage island on metal levels 1 to N-1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.
• Figure 1 is a diagram of an integrated circuit chip having a voltage island on which a preferred embodiment of the present invention can be implemented;
• Figure 2 is a cross-sectional diagram of the integrated circuit chip from Figure 1, in accordance with a preferred embodiment of the present invention
• Figure 3 is a high-level logic flow diagram of a method for performing power routing on a voltage island within an integrated circuit chip, in accordance with a preferred embodiment of the present invention
• FIG. 4 is a high-level logic flow diagram of a ShapeRouter routine, in accordance with a preferred embodiment of the present invention.
• FIG. 5 is a block diagram of a data processing system for performing power outing on a voltage island within an integrated circuit chip, in accordance with a preferred embodiment of the present invention.
• an integrated circuit chip 10 includes a voltage island 5.
• Voltage island 5 includes a VDD g power network 11 supplied from a chip VDD g power grid 12, a GND power network 13 supplied from a chip GND power grid 14, VDDj-VDD n power networks 15 supplied from on-chip VDDj-VDD n power grids 16 and (optionally) GNDj-GND n power networks 17 supplied from on-chip GNDj-GND n power grids 18.
• Voltage island 5 also includes power service terminals (PSTs) 19 for supplying power to circuits and devices contained in voltage island 5. PSTs 19 must be connected to VDD g , VDDj- VDD n and GND.
• VDDg power network 11 GND power network 13 and VDDj-VDD n power networks 15 are shown as power rings in Figure 1, it is understood by those skilled in the art that other types of configurations, such as grids, is also possible as well.
• the power grids for voltage island 5 are preferably divided into two groups, namely, a first power grid 21 located from metal level 1 to metal level N-1 and a second power grid 22 located at metal level N and above.
• second power grid 22 can be in the form of a power segment.
• a power segment is defined as a power grid having only one level of metal lines.
• the relevant inputs and preconditions for second power grid 22 are:
• power grid source points such as a ball grid array pad, voltage regulator pins, and/or a wirebond pad 23 as shown in Figure 2;
• a first power grid for a voltage island is generated on metal level 1 to metal level N-1, as shown in block 31.
• the robust power grid generation is preferably performed using techniques similar to the chip power grid generation.
• a second power grid for voltage island is generated on metal levels N and above, as depicted in block 32.
• the second power grid can be in the form of a power segment (i.e., having only one metal layer).
• the number of power segments (S) to be routed on metal levels N and above is preferably determined by the product of the number of power sources and the number of connections to be made per power source.
• Each power source may be connected to the voltage island using multiple wires rather than a single wide wire. The width of the multiple wires can be adjusted in order to meet all electrical constraints.
• the bounding region of the second power grid is determined, as shown in block 33. If the second power grid is formed of power segments, then all the power segments (S) are routed on metal level N so that a robust second power grid is formed across the bounding region and the full length of the bounding region can be extended. Subsequently, a set of shortest distance connections are routed from various power sources to the second power grid (or to respective power segments on metal layer N), as depicted in block 34. The router builds an array having entries with start/end shapes for each connection. Such array is sorted by distance so that a router can guarantee the shortest distance connections from a power source to a specific power segment on metal level N.
• the step within block 33 of Figure 3 further includes the association of a keyword with a power source, and the voltage island identifies which power source should connect to the co ⁇ ect set of power grids on top of the voltage island, under multiple voltage island instances scenario.
• a shape router for performing the ShapeRouter routine is a point-to-point routing engine.
• an initialization procedure is performed, as shown in block 41.
• a working window is set, and gridless blockage shape maps are built.
• open tiles are constructed, as depicted in block 42.
• blockage maps are updated, if necessary.
• node lists for start and end points are built.
• node shapes are pre-processed to handle "skinny" pins. Guiding windows are built based on node lists and constraints. Subsequently, open- tiles are built based on guiding windows and existing blockages.
• Maze routing opens from start node list to end node list, as shown in block 43.
• a path is built from the open list by weight, as depicted in block 44.
• an open shape list is built by traversing opens by weight from end node list to start node list.
• a corner shape list is built from the open shape list.
• a detail path is built from the corner shape list.
• Path ends are processed to reach start and end points, as shown in block 45. The process then returns detail path, as depicted in block 46.
• the present invention provides a method and apparatus for performing power routing on a voltage island within an integrated circuit chip.
• power can be routed to voltage islands from either off-chip power sources (wirebond pads) or on-chip power sources (voltage regulator macro pins) to voltage island grids directly above the voltage islands.
• unique routes can be generated from power source to metal level segments over a voltage island with no intersecting or overlapping.
• the present invention describes power routing for on-chip drivers, it is understood by those skilled in the art that the present invention is also applicable to power routing from an off-chip driver circuit that requires off-chip power source.
• a general-purpose computer for performing power routing on a voltage island within an integrated circuit chip, in accordance with a preferred embodiment of the present invention.
• a computer system 40 includes a processor 41 interconnected to a random access memory (RAM) 42, a read-only memory (ROM) 43 via a system bus 50.
• RAM random access memory
• ROM read-only memory
• I/O Processor 41 is also interconnected to an input/output (I/O) adapter 44 for a connecting a removable storage device 46 and a mass storage device 45, a user interface adapter 47 for connecting a keyboard 49 and a mouse 48, a port adapter 51 for connecting a data port 52, and a display adapter 53 for connecting a display device 54.
• I/O input/output
• ROM 43 contains the basic operating system for computer system 40.
• removable storage device 46 include floppy drives, tape drives and CD ROM drives.
• mass storage device 45 include hard disk drives and non- olatile memory such as flash memory.
• keyboard 49 and mouse 48 other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may also be connected to user interface 47.
• display devices include cathode-ray tubes (CRTs) and liquid crystal displays (LCDs).
• signal bearing media include, without limitation, recordable type media such as floppy disks or CD ROMs and transmission type media such as analog or digital communications links.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Geometry (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• General Engineering & Computer Science (AREA)
• Evolutionary Computation (AREA)
• Computer Networks & Wireless Communication (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 2003
  • 2003-10-09 US US10/605,569 patent/US6861753B1/en not_active Expired - Fee Related
• 2004
  • 2004-10-08 WO PCT/US2004/033384 patent/WO2005036606A2/en not_active Ceased
  • 2004-10-08 EP EP04794665A patent/EP1671339A4/en not_active Withdrawn
  • 2004-10-08 KR KR1020067006462A patent/KR100850414B1/ko not_active Expired - Fee Related
  • 2004-10-08 CN CNB2004800290278A patent/CN100429664C/zh not_active Expired - Fee Related
  • 2004-10-08 JP JP2006534426A patent/JP4456606B2/ja not_active Expired - Fee Related
  • 2004-11-03 US US10/980,575 patent/US7234124B2/en not_active Expired - Fee Related

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