WO2005013350A1 - Methode de fabrication d'un dispositif semi-conducteur avec un transistor bipolaire et dispositif avec un transistor bipolaire - Google Patents

Methode de fabrication d'un dispositif semi-conducteur avec un transistor bipolaire et dispositif avec un transistor bipolaire Download PDF

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Publication number
WO2005013350A1
WO2005013350A1 PCT/IB2004/051292 IB2004051292W WO2005013350A1 WO 2005013350 A1 WO2005013350 A1 WO 2005013350A1 IB 2004051292 W IB2004051292 W IB 2004051292W WO 2005013350 A1 WO2005013350 A1 WO 2005013350A1
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WO
WIPO (PCT)
Prior art keywords
region
layer
semiconductor
semiconductor layer
silicon
Prior art date
Application number
PCT/IB2004/051292
Other languages
English (en)
Inventor
Francois I. Neuilly
Johannes J. T. M. Donkers
Eyup Aksen
Joost Melai
Yukiko Furukawa
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP04744646A priority Critical patent/EP1654755A1/fr
Priority to JP2006522451A priority patent/JP2007501512A/ja
Publication of WO2005013350A1 publication Critical patent/WO2005013350A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]

Definitions

  • the invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body of silicon with a bipolar transistor including a base, an emitter and a collector, wherein the emitter is formed in a first region of the semiconductor body and wherein an electrically insulating layer is formed on the semiconductor body in which a window is formed in the first region of the semiconductor body and a semiconductor layer of silicon is deposited on the insulating layer which fills the window in the insulating layer and which extends laterally over the insulating layer along the window and after the deposition of the semiconductor layer, the semiconductor layer and the insulating layer are removed in a second region of the semiconductor body which borders the first region which is covered by a stack comprising a remaining part of the insulating layer and a remaining part of the semiconductor layer and hereinafter a metal layer is deposited on top of the remaining part of the semiconductor layer and on the second region of the semiconductor body of silicon and a suicide is formed between the metal layer and the second region of the semiconductor body of silicon and between the metal layer and the remaining part
  • a method of the type mentioned in the opening paragraph is characterized in that the means to prevent bridging of the suicides to be formed comprises that the side face of the stack is structured in such a way that the distance between the upper surface of the remaining part of the semiconductor layer and the upper surface of the second region of the semiconductor body along the surface of the side face of the stack is made longer than the total thickness of the insulating layer and the semiconductor layer.
  • the invention is based on the recognition that increasing the length of a path along the side face of the stack already is sufficient to avoid the occurrence of the bridging problem.
  • the invention is further based on the recognition that such increased path length can be created in a simple manner by structuring the profile of the stack- which in the method of prior art is made rectangular - such that so to say the slope of the profile is changed by which the length of said path is increased.
  • Both a positive slope in the side face of the remainder of the insulating layer as well as a negative slope in the side face of the remainder of the semiconductor layer will result in an increased path along the side face of the stack of both layers, which will result in avoidance of the bridging problem.
  • the invention is based on the recognition that a structuring as envisaged is possible using merely the etching steps which are needed anyway to remove parts of the insulating layer and the semiconductor layer in a specific manner which will be described hereinafter.
  • the method according to the invention does not or at least hardly makes the method more complicated. The method thus also is cheap.
  • the removal of the semiconductor layer and the insulating layer in the second region is done by an etching process such that the side face of the remaining part of the insulating layer is made convex and extends viewed in projection outside the remaining part of the semiconductor layer.
  • the convex part may be substantially linear but this is not necessary.
  • Such a positive outward slope of the side face of the remainder of the insulating layer is easily obtained if a dry etching process is used for removing part of the insulating layer that is based on the chemistry of fluor and carbon.
  • the carbon may be provided by a photoresist layer which will be present during the etching process as a mask.
  • the fluor compound(s) may be added to the plasma.
  • polymers of fluor and carbon will deposit at the edges in the bottom of a hole to be etched in the insulating layer. Subsequently, the same etching process may remove them. However, as a results of these phenomena the remainder of the insulating layer will taper outwardly with a slope of e.g. about 45 degrees. In this way the path length along the side face of the stack is increased by which the bridging problem is avoided.
  • the slope may be smaller than 45 degrees for the envisaged effect, however such a small slope also has disadvantages.
  • a preferred value of the slope lies between 30 and 60 degrees.
  • the removal of the semiconductor layer in the second region is done by an etching process such that the side face of the remaining part of the semiconductor layer is made concave end extends viewed in projection inside towards the remaining part of the insulating layer.
  • the path length along the side face is increased in a simple manner.
  • there is a shadow effect that may be advantageous in avoiding the bridging problem.
  • Such a profile of the remainder of the semiconductor layer may e.g. be obtained in that a first upper part of the semiconductor layer is etched by using an anisotropic dry etching process and a second, lower part of the semiconductor layer is etched using an isotropic etching process.
  • the semiconductor layer is provided with a doping profile such that a lower part of the semiconductor layer has a high doping level and an upper part of the semiconductor layer has a low doping level and the difference in doping level between the parts is used to form the desired concave side face of the remaining part of the semiconductor layer.
  • a difference may result in a different etching speed in the same, e.g. wet, etching agent, whether or not combined with the addition of light to the surface to be etched.
  • a pn-junction is introduced in the semiconductor layer, selective etching of part of the side face of the remainder of the semiconductor layer may be obtained.
  • the pn junction may be removed by etching or overdoping, e.g. by ion implantation of suitable doping atoms.
  • etching or overdoping e.g. by ion implantation of suitable doping atoms.
  • the side face of the remaining part of the semiconductor layer is thermally oxidized and subsequently the resulting oxide is removed by a wet etching agent based on HF.
  • the above mentioned difference in doping level will result in a different depth of oxidation of the side face of the remainder of the semiconductor layer.
  • a notch will result at the lower part of the remainder of the semiconductor layer, providing the required path lengthening and providing a shadow effect.
  • the preferably not yet etched insulating layer will protect the semiconductor body during this etching step.
  • the insulating layer is partly etched, preferably by means of a dry, anisotropic etching process.
  • the remainder of the insulating layer and the remainder of the semiconductor layer and a layer on top thereof are used as a mask for doping the second region of the semiconductor body. In this way an enhanced doping level of said region, which will later on serve as a connection region for the base of the bipolar transistor, is easily provided. High speed and low dissipation of the device are improved in this way.
  • the base is formed by providing the semiconductor body with a doped further semiconductor layer which locally borders on a monocrystalline part of the semiconductor body, thereby forming a first semiconductor region which is monocrystalline and which constitutes the base of the transistor and which further semiconductor layer borders at locations outside the base on a non-monocrystalline part of the semiconductor body thereby forming a second semiconductor region which is not monocrystalline and which constitutes a connection region of the base and the collector is formed by a further part of the semiconductor body situated below the base.
  • Such process is particularly suitable for the manufacturing of very high-speed heterojunction bipolar transistors with e.g. SiGe in the base.
  • the invention comprises a semiconductor device with a bipolar transistor with a base, an emitter and a collector in a semiconductor body of silicon and having above the emitter an insulating region with a window which is filled with a semiconductor region of silicon which extends over the surface of the insulating region and with suicides formed on top of the silicon region and on top of the semiconductor body on both sides of the insulating region, characterized in that the side face of the stack formed by the insulating region and the silicon region is structured in such a way that the distance between the upper surface of the silicon region and the surface of the semiconductor body along the surface of the side face of the stack is made longer than the total thickness of the insulating region and the silicon region.
  • Such a device which is characterized by a slope of the side face of the region above the base / emitter which deviates from a direction perpendicular to the layer structure, has the above mentioned advantages and may be obtained with a high yield by a method according to the invention due to the fact that such a slope results in avoidance of the above explained bridging problem.
  • Both positive and negative slopes are suitable.
  • the slope may be in the insulating or in the silicon region (or both).
  • Figs 1 through 11 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive stages in the manufacture using a first embodiment of a method in accordance with the invention
  • Figs 12 through 15 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive relevant stages in the manufacture using a second embodiment of a method in accordance with the invention
  • Figs 16 through 19 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive relevant stages in the manufacture using a third embodiment of a method in accordance with the invention.
  • the Figures are diagrammatic and not drawn to scale, particularly the dimensions in the thickness direction being exaggerated for clarity. Semiconductor regions of the same conductivity type are generally hatched in the same direction. Like reference nume
  • Figs 1 through 11 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive stages in the manufacture using a first embodiment of a method in accordance with the invention.
  • the starting point (see fig. 1) is formed by a p-type silicon substrate 11 that is provided with an epitaxial. layer 33 of n-type silicon which is moderately doped. Before the deposition of the layer 33 an n+ type buried region 3A1 is formed by means of ion implantation.
  • connection region 3A2 is made for connection of the collector 3 of the transistor to be formed.
  • a thermal oxide layer 9 is formed on the (cleaned) surface of the semiconductor body 100 and on top thereof a thin polycrystalline silicon layer 4 is deposited thereon.
  • a mask 20 e.g. of silicondioxide is patterned on top of the poly-silicon layer 4.
  • a window is opened by means of etching at the location of the active area of the bipolar transistor to be formed.
  • a poly silicon layer 4 also a layer of poly silicon on silicon nitride may be used or only a layer of silicon nitride.
  • the oxide layer 9 is removed inside the window.
  • the silicon layer 12 is monocrystalline at the active area of the transistor and will form the base 1 of the transistor.
  • the layer 12 is provided during growth with a p-type doping spike.
  • a thin sublayer - not indicated separately in the drawing - containing a SiGe mixed crystal may be provided which is made so thin that no misfit dislocations are formed.
  • the silicon layer 12 is polycrystalline and will form part of a connection region 1A of the base 1.
  • a 20 to 200 ran thick silicondioxide layer 13 is deposited by means of CVD.
  • a small window is opened in the insulating layer 13 by means of photolithography and etching.
  • a polycrystalline silicon layer 14 is deposited by means of CVD on top of the surface of the semiconductor body 100 which fills the opening in the insulating layer 13 and extends laterally over said layer.
  • a mask 50, here of photoresist, is patterned above the structure, the width thereof being e.g.
  • 0,5 ⁇ m which is about 100 to 200 nm outside the emitter area whereas the width of the opening in insulating layer 13 below the mask 50 is e.g. about 0,3 ⁇ m but could be as small as about 100 nm in a very advanced device.
  • layer 13 also may comprise a stack of different dielectric layers in view of an etch stop function. It is further noted that the bridging problem which above has been defined and which is avoided in the present invention, may in particular occur if the thickness of the dielectric layer 13 is less than about 60 nm. Then (see fig. 6) the silicon layer 14 is removed outside the mask 50 by means of etching, e.g. dry etching.
  • the insulating layer 13 outside the mask 50 is removed by dry-etching as well.
  • the process is based on the chemistry of compounds of fluor and carbon. Therefore (see figure 7) the silicondioxide layer 13 will under suitable etching conditions, taper outside the mask 50 gradually toward a thickness of zero.
  • a mask 70 which is typically at least 1 ⁇ m wide and extends 0,2 to 0,5 ⁇ m outside the active region, the layers 9,4 and 12 are removed outside the active area of the transistor to be formed.
  • the remaining parts of the insulating layer 13 and the silicon layer 14 and the mask layer 50 on top thereof are used to implant additional p-type impurities in the silicon layer 12 outside this structure.
  • the resistance of the base connection region 1 A is decreased in this way.
  • a metal layer 16, here of titanium, is deposited on the structure 100.
  • the metal layer 16 also could be a stack of different metal layers.
  • the metal layer 15 reacts with the silicon parts to which it is exposed to form suicides 17 at the locations of the base connection region 1A, the collector connection region 3A2 and at the location of the poly- silicon above the emitter to be formed.
  • the parts of the metal layer 16 that did not react with silicon are removed by means of etching.
  • the suicides 17 are transformed from a monosilicide towards a disilicide, the latter having the lower sheet resistance.
  • emitter 2 is formed by outdiffusion of impurities from the remaining part of the silicon layer 14 into the base layer 12.
  • the poly- silicon layer 14 is n-type doped during its deposition as the present example deals with a npn bipolar transistor.
  • an insulating layer 18, e.g. of silicondioxide is deposited on the surface of the semiconductor body 100. It is provided with openings in which connection conductors 19 are formed.
  • FIGs 12 through 15 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive relevant stages in the manufacture using a second embodiment of a method in accordance with the invention. As many of the manufacturing steps are the same as in the previous example, these steps will be not repeatedly described. Only the relevant steps will be discussed. After the situation of figure 5 has been reached, the manufacture proceeds as shown in figure 12. In this example the etching of the poly- silicon layer 14 is done in such a way that the remaining part of the silicon layer 14 shows a sideface with a negative slope, i.e.
  • the sideface tapers inwardly and downwardly towards the interface with the insulating layer 13 below the mask 50.1n this example this is obtained by etching the silicon layer 14 in two etching steps: a first etching step based on C12 chemistry for obtaining anisotropy and based on HBr for obtaining sidewall passivation followed by a second isotropic etching step based on fluor chemistry, e.g. by using SF6. Subsequently, the insulating layer 13 is removed using a anisotropic etching process resulting in a sideface running perpendicular to the layer structure: see figure 13.
  • the stages of figure 13, 14 and 15 correspond with those of figures 7, 8 and 10, and the stage of figure 9 is not shown separately in this example.
  • Figs 16 through 19 are diagrammatic, cross-sectional views, at right angle to the thickness direction, of a semiconductor device with a bipolar transistor at successive relevant stages in the manufacture using a third embodiment of a method in accordance with the invention. It is again referred to the first example for most of the manufacturing steps. The in this example relevant step corresponding with figure 6 is shown in figure 16.
  • the remaining part of the silicon layer 14 has in this example two different doping levels on both sides of the dashed line: a lower part 14A is provided with a high doping level whereas the upper part 14B is provided with a low doping level.
  • the side face of the remaining part of the silicon layer 14 is thermally oxidized so as to form oxide region 40.
  • the oxide region 40 has a stepped profile as shown in figure 17. After a dip in an aqueous solution of HF, said oxide region 40 is removed and the result is (see figure 17) a remaining part of the silicon layer 14 having a notch just below the remaining part of the insulating layer 13.
  • MBE Molecular Beam Epitaxy
  • PVD Physical Vapor Deposition
  • the method according to the invention may be very well applied to a more complex device than a single bipolar transistor.
  • the device may comprise a number of different active or passive electronic or semiconductor components.

Abstract

L'invention concerne la fabrication d'un dispositif (10) à transistor bipolaire dont l'émetteur est formé en utilisant une zone (14) en silicium polycristallin présente dans une fenêtre dans une couche isolante (13) et qui s'étend latéralement sur la couche isolante (13). La zone en silicium (14) et une autre zone en silicium (12) adjacente à la pile formée par la zone isolante (13) et par la zone en silicium (14) sont siliciurées au moyen d'une couche métallique (16) déposée sur la structure. La face latérale de la pile comprend des moyens pour éviter le pontage des siliciures (17) devant être formés. Selon l'invention, les moyens utilisés pour éviter le pontage des siliciures devant être formés comprennent la structuration de la face latérale de la pile de telle sorte que la distance entre la surface supérieure de la zone en silicium (14) et la surface supérieure de l'autre zone en silicium (12) le long de la surface de la face latérale de la pile soit plus longue que l'épaisseur totale de la couche isolante (13) et de la couche semi-conductrice (14). Le pontage des siliciures est évité en ce que la voie est allongée par une pente positive ou négative de la face latérale de la pile. Les modes préférentiels de réalisation concernent la façon de structurer la face latérale de la pile.
PCT/IB2004/051292 2003-08-01 2004-07-26 Methode de fabrication d'un dispositif semi-conducteur avec un transistor bipolaire et dispositif avec un transistor bipolaire WO2005013350A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04744646A EP1654755A1 (fr) 2003-08-01 2004-07-26 Methode de fabrication d'un dispositif semi-conducteur avec un transistor bipolaire et dispositif avec un transistor bipolaire
JP2006522451A JP2007501512A (ja) 2003-08-01 2004-07-26 バイポーラ・トランジスタを有する半導体装置の製造方法及びバイポーラ・トランジスタを有する装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03102405.2 2003-08-01
EP03102405 2003-08-01

Publications (1)

Publication Number Publication Date
WO2005013350A1 true WO2005013350A1 (fr) 2005-02-10

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PCT/IB2004/051292 WO2005013350A1 (fr) 2003-08-01 2004-07-26 Methode de fabrication d'un dispositif semi-conducteur avec un transistor bipolaire et dispositif avec un transistor bipolaire

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Country Link
EP (1) EP1654755A1 (fr)
JP (1) JP2007501512A (fr)
KR (1) KR20060056971A (fr)
TW (1) TW200520221A (fr)
WO (1) WO2005013350A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007057803A1 (fr) * 2005-11-21 2007-05-24 Nxp B.V. Procédé de fabrication d’un dispositif semi-conducteur et dispositif semi-conducteur obtenu par un tel procédé
WO2007000693A3 (fr) * 2005-06-27 2007-08-02 Nxp Bv Dispositif semi-conducteur et procede permettant de produire ce dispositif

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209749A1 (fr) * 2000-05-12 2002-05-29 Matsushita Electric Industrial Co., Ltd. Dispositif a semi-conduteurs et son procede de production
US20020164884A1 (en) * 2001-05-02 2002-11-07 Unaxis Usa Method for thin film lift-off processes using lateral extended etching masks and device
US6563147B1 (en) 2000-01-11 2003-05-13 Mitsubishi Denki Kabushiki Kaisha HBT with a SiGe base region having a predetermined Ge content profile
US20030096444A1 (en) * 2000-03-24 2003-05-22 Stefan Kraus Heterobipolar transistor with T-shaped emitter terminal contact and method of manufacturing it

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563147B1 (en) 2000-01-11 2003-05-13 Mitsubishi Denki Kabushiki Kaisha HBT with a SiGe base region having a predetermined Ge content profile
US20030096444A1 (en) * 2000-03-24 2003-05-22 Stefan Kraus Heterobipolar transistor with T-shaped emitter terminal contact and method of manufacturing it
EP1209749A1 (fr) * 2000-05-12 2002-05-29 Matsushita Electric Industrial Co., Ltd. Dispositif a semi-conduteurs et son procede de production
US20020164884A1 (en) * 2001-05-02 2002-11-07 Unaxis Usa Method for thin film lift-off processes using lateral extended etching masks and device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007000693A3 (fr) * 2005-06-27 2007-08-02 Nxp Bv Dispositif semi-conducteur et procede permettant de produire ce dispositif
US7956399B2 (en) 2005-06-27 2011-06-07 Nxp B.V. Semiconductor device with low buried resistance and method of manufacturing such a device
WO2007057803A1 (fr) * 2005-11-21 2007-05-24 Nxp B.V. Procédé de fabrication d’un dispositif semi-conducteur et dispositif semi-conducteur obtenu par un tel procédé
US8173511B2 (en) 2005-11-21 2012-05-08 Nxp B.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

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JP2007501512A (ja) 2007-01-25
KR20060056971A (ko) 2006-05-25
TW200520221A (en) 2005-06-16
EP1654755A1 (fr) 2006-05-10

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