Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
  • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

• This invention relates in general to a input/output system, and more particularly to a method, apparatus and program storage device for presenting status from a host bus adapter.
• communication adapters and Input/Output (I/O) controllers are provided to transfer data between a host system and a network or peripheral device.
• the memory and processor of the host system are coupled to the adapter or controller by a system or I/O bus or by a network.
• Data is typically transmitted back and forth between a host computer system and peripheral devices, such as disk drives, tape drives, or printers, over a data communication bus.
• the data communication bus couples the host and the peripheral devices together and enables the exchange of data between the system and the peripheral devices .
• One type of data communication bus is a Small Computer System Interconnect (SCSI) data bus.
• SCSI data bus can be configured in different ways and has several modes of operation.
• the SCSI protocol specifies communication between an initiator, or device that issues SCSI commands, and a target, a device that executes SCSI commands.
• the SCSI data bus is connected to the initiator via a host adapter and is connected to target devices via device controllers . Each device controller is matched to the specific type of device connected to the SCSI bus.
• a handshaking protocol is used to control the transfer of data on the data bus connected therebetween.
• UDP Upper Level Protocols
• FCP is a protocol which maps SCSI to Fibre Channel.
• iSCSI maps SCSI to Ethernet.
• FCP and iSCS and other protocols talk in terms of an initiator and a target.
• An initiator is an agent that initiates an exchange and issues a SCSI command to a target.
• a SCSI I/O launched by the operating system to write blocks of data to a storage peripheral may initiate, for example, an FCP exchange between the host and target using command frames known as information units ( ⁇ s) .
• FCP is just one example.
• groups of frames comprising one or more sequences would be used to transport data from host to the target.
• the target would reply that it is ready.
• the initiator responds by issuing a data descriptor information unit.
• the initiator then sends one or more solicited data information units.
• the target responds by issuing a command status information unit indicating completion of the send request.
• the initiation of the FCP exchange with the target replying, the initiator response with data descriptor information and the target issuing command status may be combined in different ways to make a protocol more efficient.
• the target must then accept the data and issue a response of some kind. If no errors or exceptions are received then the response would indicate normal status .
• a typical target is some kind of storage system. Often times a target will be comprised of a Host Bus Adapter (HBA) which handles the protocol communicating with a host like a PC or a specialized piece of hardware. The HBA will notify the host of SCSI commands and will be told from the host where to get or put the data.
• HBA Host Bus Adapter
• the HBA For a write command, the HBA must notify the host that the initiator wants to perform a write operation. If the host is a complex storage system, it will need to determine if the sectors being written are already in the write cache and precisely where the data is to be written. The host may need to do some additional formatting on the data as well. The host will communicate with the HBA where to put the data and the HBA then will store the data. In today's environment, the host will need to communicate to the HBA that the operation was successful and assuming that the HBA did not detect an error then deliver good status back in the response. This additional interaction between the host and the HBA is a. significant amount of processing and handshaking for both the host and the HBA.
• the present invention discloses a method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected.
• the present invention solves the above-described problems by allowing an HBA to automatically respond back to the initiator without waiting for the host to tell the HBA to do so. In one embodiment this is done by having specialized hardware which checks the data and control logic and determines very quickly if an error has occurred during transmission of the data from the HBA to the host. If an error is detected, then a signal is raised to the HBA handling that particular port. The HBA immediately stops automatically sending status back to the initiator and now requires the host to communicate separately for each operation telling the host bus adapter what status to present to the initiator .
• a program storage device in accordance with the principles of the present invention includes a method for transmitting data via a host bus adapter to a host, performing data transmission validation at a host, determining at the host whether data transmission was successful and automatically sending status information from the host bus adapter when data transmission was successful, else causing the host bus adapter to wait for status type identification from the host for transmission of data.
• This program storage device includes a method for receiving data at a host from a host bus adapter, performing data transmission validation at the host, determining at the host whether data transmission was successful and causing the host bus adapter to wait for status type identification from the host for transmission of data when data transmission is determined to be unsuccessful .
• This program storage device includes a method for transmitting data via a host bus adapter to a host and automatically sending status information from the host bus adapter until receiving at the host bus adapter a signal from the host for inhibiting automatic status transmission by the host bus adapter.
• an input/output system in another embodiment, includes a host bus adapter for transmitting data and a host, coupled to the host bus adapter, for performing data transmission validation and determining whether data transmission was successful, wherein the host bus adapter automatically sends status information until the host determines data transmission was not successful and sends the host bus adapter a signal to inhibit automatic status transmission by the host bus adapter.
• a host in another embodiment, includes a host bus adapter interface for receiving data from a host bus adapter, a processor, coupled to the host bus adapter interface, for performing data transmission validation and a port, coupled to the processor, for transmitting a signal for causing the host bus adapter to wait for status type identification for transmission of data when data transmission is determined to be unsuccessful .
• a host bus adapter in another embodiment, includes a protocol handling interface for transmitting data to a host and a processor, coupled to the protocol handling interface, for automatically sending status information until receiving a signal for inhibiting automatic status transmission.
• a method for automatically presenting status from a host bus adapter until an error is detected.
• the method includes transmitting data via a host bus adapter to a host, performing data transmission validation at the host, determining at the host whether data transmission was successful and automatically sending status information from the host bus adapter when data transmission was successful, else causing the host bus adapter to wait for status type identification from the host for transmission of data.
• an input/output system in another embodiment, includes means for transmitting data and means, coupled to the means for transmitting, for performing data transmission validation and determining whether data transmission was successful, wherein the means for transmitting data sends status information when the means for performing data transmission validation determines data transmission was successful, else the means for transmitting data waits for status type identification from the host for transmission of data.
• a host in another embodiment, includes means for receiving data from a host bus adapter, means, coupled to the means for receiving, for performing data transmission validation at the host and means, coupled to the means for performing, for transmitting a signal for causing the host bus adapter to wait for status type identification for transmission of data when data transmission is determined to be unsuccessful .
• a host bus adapter in another embodiment, includes means for transmitting data to a host and means, coupled to the means for transmitting, for automatically sending status information until receiving a signal for inhibiting automatic status transmission.
• Fig. 1 illustrates an Input/Output (I/O) system according to the preferred embodiment of present invention
• Fig. 2 illustrates a system for automatically presenting status from a host bus adapter until an error is detected;
• Fig. 3 illustrates the system error/condition verification system
• Fig. 4 illustrates a flow chart of a method for automatically presenting status from a host bus adapter until an error is detected
• Fig. 5 illustrates a system wherein the process illustrated with reference to Figs. 1-4 may be tangibly embodied in a program storage devices .
• the present invention provides a method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected.
• This invention allows a host bus adapter (HBA) to automatically respond back to the initiator without waiting for the host to tell the HBA to do so.
• the host checks the data and control logic and determines very quickly if an error has occurred during transmission of the data from the HBA to the host . If an error is detected, then a signal is raised to the HBA handling that particular port.
• the HBA immediately stops automatically sending status back to the initiator and now requires the host to communicate separately for each operation telling the HBA what status to present to the initiator.
• Fig. 1 illustrates an Input/Output (I/O) system 100 according to the preferred embodiment of the present invention.
• a processor 110 is coupled to cache memory 120.
• Cache memory 120 is high-speed memory that is provided for improving processor performance.
• Cache 120 resides between the processor 110 and the main system memory 150.
• I/O devices 130 are used to provide various services, such as storage, graphics processing, network connections, printing, etc.
• a system bus 140 which is usually referred to as the local bus, provides a connection between the I/O devices 130, processor 110 and memory 150.
• the local bus 140 connects the processor 110 to main memory 150 and cache 120.
• the I/O devices 130 are coupled to the local bus 140 through a host bus adapter (HBA) 160 and an I/O bus 162.
• HBA host bus adapter
• I/O bus 162 connects the various peripheral devices 130 via the HBA 160 to the processor 110.
• An operating system 170 runs on the processor 110 and is used to coordinate and provide control of various components within I/O system 100 in Fig. 1.
• the operating system 170 may be a commercially available operating system, such as OS/2, which is available from International Business Machines Corporation. "OS/2" is a trademark of International Business Machines Corporation. Instructions for the operating system 170 and applications or programs 180 may be located on a media devices 182, 184, and may be loaded into main memory 150 for execution by processor.
• a bus protocol is used to define the semantics of the bus transaction and to arbitrate bus usage.
• a bus transaction includes at least sending an address and receiving or sending data. For example, a read transaction transfers data from memory 150 to the processor 110 or to an I/O device 130, and a write transaction transfers data from the processor 110 or an I/O device 130 to memory 150.
• a host bus adapter (HBA) 160 is used to connect input/output peripherals, such as media devices 182, 184, to the processor 110.
• I/O devices 130 may include, for example, a SCSI, Fibre Channel, Ethernet, or InfinibandTM Trade Association (www.infinibandta.com) compliant I/O device.
• HBA 160 may be utilized, for example, for implementing a small computer system interface (SCSI) high speed parallel interface defined by the X3T9.2 Committee of the American National Standards Institute (ANSI).
• SCSI small computer system interface
• An interface may connect processor 110 to media devices 182, 184, such as hard disk drives, printers, and other devices.
• a plurality of media devices 182, 184 may be coupled by an I/O bus 162.
• An I/O bus 162 is a parallel bus that carries data and control signals from the host bus adapter 160 to the media devices 182, 184.
• a media device 182, 184 may be a SCSI device, which is a peripheral device that uses the SCSI standard to exchange data and control signals with a processor 110.
• RAID redundant array of independent disks
• RAID is a data storage method in which data, along with information used for error correction, such as parity bits or Hamming codes, is distributed among two or more hard disk drives 184 in order to improve performance and/or data integrity.
• a hard disk array 184 may be governed by array management software and a host bus adapter 160 which handles the error correction.
• Fig. 1 may vary depending on the implementation. Additional connections to local bus 140 may be made through direct component interconnection or through add-in boards.
• a network adapter 186, host bus adapter 160, and expansion bus interface 188 may be connected to local bus 140 by direct component connection.
• a graphics adapter 190 may be connected to local bus 140 by add-in boards inserted into expansion slots.
• host bus adapter 160 provides a connection for media devices 182, 184, such as hard disk drives, tape drives, CD-ROM drives, and digital video disc read only memory drive (DVD-ROM) .
• Typical local bus 140 implementations will support, for example, three or four PCI expansion slots or add-in connectors 192. Nevertheless, those skilled in the art will recognize that the depicted example is not meant to imply architectural limitations with respect to the present invention. For example, the processes of the present invention may be applied to multiprocessor data processing systems.
• Fig. 2 illustrates a system 200 for automatically presenting status from a host bus adapter until an error is detected according to the preferred embodiment of the present invention.
• Fig. 2 shows a HBA 210 that is coupled to a host 220 via a standard bus 230, such as PCI, PCIX, etc.
• the HBA 210 includes a processor 212, memory 214 and a protocol handling interface 216 for handling data transmission between the host 220 and the HBA 210.
• a link 218, such as for optics, is provided.
• the host 220 includes a processor 222 and an HBA interface 224 for providing direct memory access and formatting.
• the HBA interface 224 also provides access 226 to other portions of the host 220.
• the host 220 further includes a port 228 for communicating an auto status inhibit signal 240 to the HBA 210.
• Each host 220 is coupled to an interface card, such as a host bus adapter 210.
• the host bus adapter 210 has a processor 212 and memory 214, such as RAM or EEPROM. In one embodiment, at least a portion of the memory 214 is used to hold adapter code downloaded from the host 220.
• each host bus adapter 210 is located on a separate circuit card. In another embodiment, more than one host bus adapter 210 is located on a circuit card.
• Each host bus adapter 210 is typically connected to a local bus 230, such as a PCI bus.
• the HBA 210 interprets a protocol directly and provides an application interface in order to store and retrieve data to send over the link 218.
• a host 220 of some kind will communicate with this HBA 210.
• This host 220 may be a PC or server, or a set of electronics with a microprocessor, memory and logic which can interface to one or more HBAs 210 and can also interface to internal fabric within the host 220.
• a PCI card could be designed to provide the HBA 210 with a microprocessor 212 and other application specific integrated circuits which could further format the HBA data and communicate with the PCI bus 230.
• Such PCI card would then plug into a server with other components (including like cards) and could act as a storage, tape or print server.
• Both the host 220 and the HBA 210 - typically contain microprocessors 222, 212 which are assisting in handling the interface protocol as well as the protocol between the two components . For performance to be high, it is important to find ways to parallel activities and to minimize transactions across the standard bus 230 as shown.
• the HBA 210 may automatically send status via the link 218 after processing a command, such as a SCSI command. Otherwise the host must process the fact that the information transfer has occurred error free and must then send a command to the HBA 210 informing the HBA 210 that it should give normal ending status to the initiator, e.g., the host 220.
• a command such as a SCSI command.
• Fig. 3 illustrates the system error/condition verification system 300 according to the preferred embodiment of the present invention.
• the preferred embodiment of the present invention eliminates the handshake and processing that both processors must otherwise perform.
• the system requires that all good error checking capability exists on the host. Therefore, as the data is transferred from the HBA to the host, the data is thoroughly checked 310.
• the host is also checking to ensure that state machines and intermediate buffers which are traversed on the way to the data memory do not occur 320. All of these checks are processed by an OR gate 340 along with exception conditions from the processor and catastrophic error conditions like clock checks, bus hangs, etc 330. Any of these checks 310-330 being asserted will therefore cause the host to assert a signal 340 to the HBA thereby inhibiting it from sending automatic status.
• Fig. 4 illustrates a flow chart of a method 400 for automatically presenting status from a host bus adapter until an error is detected according to the preferred embodiment of the present invention .
• data transmission validation 410 Such validation includes checking data for errors, and then checking operational status and condition indicators for an error condition. A determination is made whether an error is detected, or whether a condition or status is violated 420. If not 422, the HBA is configured to automatically send status to the initiator 430. If yes 424, the HBA that is handling the transmission is sent a signal to inhibit auto status 440. The HBA stops automatically sending status to initiator 450. The host is then required to communicate what status to present to the initiator for each operation 460.
• Fig. 5 illustrates a system 500 according to the preferred embodiment of the present invention , wherein the process illustrated with reference to Figs. 1-4 may be tangibly embodied in a computer-readable medium or carrier, e.g. one or more of the fixed and/or removable data storage devices 568 illustrated in Fig. 5, or other data storage or data communications devices.
• a computer program 590 expressing the processes embodied on the removable data storage devices 568 may be loaded into the memory 592 or into system 500, e.g., in a processor 596, to configure the system 500 of Fig. 5, for execution.
• the computer program 590 comprise instructions which, when read and executed by the system 500 of Fig. 5, causes the system 500 to perform the steps necessary to execute the steps or elements of the preferred embodiment of the present invention .

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Debugging And Monitoring (AREA)
• Computer And Data Communications (AREA)
• Bus Control (AREA)
• Information Transfer Between Computers (AREA)

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• 2003
  • 2003-05-14 US US10/437,554 patent/US7085859B2/en not_active Expired - Fee Related
• 2004
  • 2004-05-04 DE DE602004008768T patent/DE602004008768T2/de not_active Expired - Lifetime
  • 2004-05-04 KR KR1020057018294A patent/KR100968314B1/ko not_active Expired - Fee Related
  • 2004-05-04 EP EP04731047A patent/EP1625505B1/en not_active Expired - Lifetime
  • 2004-05-04 CN CNB2004800047182A patent/CN100390768C/zh not_active Expired - Fee Related
  • 2004-05-04 WO PCT/GB2004/001910 patent/WO2004102405A2/en not_active Ceased
  • 2004-05-04 JP JP2006530475A patent/JP4979383B2/ja not_active Expired - Fee Related
  • 2004-05-04 AT AT04731047T patent/ATE372553T1/de not_active IP Right Cessation
  • 2004-05-07 TW TW093112946A patent/TWI259368B/zh not_active IP Right Cessation

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