WO2004097439A1 - 測定装置、及びプログラム - Google Patents
測定装置、及びプログラム Download PDFInfo
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- WO2004097439A1 WO2004097439A1 PCT/JP2004/005982 JP2004005982W WO2004097439A1 WO 2004097439 A1 WO2004097439 A1 WO 2004097439A1 JP 2004005982 W JP2004005982 W JP 2004005982W WO 2004097439 A1 WO2004097439 A1 WO 2004097439A1
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- timing
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- 238000005259 measurement Methods 0.000 title abstract description 6
- 238000004364 calculation method Methods 0.000 claims abstract description 50
- 238000001514 detection method Methods 0.000 claims abstract description 30
- 238000012937 correction Methods 0.000 claims description 26
- 230000006870 function Effects 0.000 claims description 18
- 230000010363 phase shift Effects 0.000 claims description 9
- 240000007320 Pinus strobus Species 0.000 description 27
- 230000008859 change Effects 0.000 description 25
- 238000010586 diagram Methods 0.000 description 19
- 230000000630 rising effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000012030 stroop test Methods 0.000 description 2
- 244000260524 Chrysanthemum balsamita Species 0.000 description 1
- 235000005633 Chrysanthemum balsamita Nutrition 0.000 description 1
- BNPSSFBOAGDEEL-UHFFFAOYSA-N albuterol sulfate Chemical compound OS(O)(=O)=O.CC(C)(C)NCC(O)C1=CC=C(O)C(CO)=C1.CC(C)(C)NCC(O)C1=CC=C(O)C(CO)=C1 BNPSSFBOAGDEEL-UHFFFAOYSA-N 0.000 description 1
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- 238000012545 processing Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
Definitions
- the present invention relates to a measuring device for measuring a digital signal.
- the present invention relates to a measuring device and a program for measuring timings such as a change point of a digital signal value, an intersection of a differential digital signal, and the like.
- This application is related to the following Japanese patent application. For those designated countries that are permitted to be incorporated by reference to the literature, the contents described in the following application are incorporated into this application by reference and are incorporated as part of the description of this application.
- the quality of the electronic device is determined by measuring an output signal of the electronic device. For example, the quality of the electronic device is determined by comparing the output signal of the electronic device with a predetermined pattern. Conventionally, such determination is made by generating a strobe signal at a predetermined cycle and detecting the value of the output signal at the timing of the strobe signal. For example, the value of the detected output signal is compared with the given H comparison level and L comparison level, the output signal is converted into H logic and L logic patterns, and the pattern is compared with the expected value pattern. The judgment is made by the following.
- the quality of the electronic device can be determined by evaluating the waveform of the output signal of the electronic device. For example, the quality of the electronic device can be determined based on whether the timing of the edge of the output signal is within a predetermined range.
- the timing of the edge of the output signal can be measured, for example, by detecting the signal value near the edge of the output signal using a multi-strobe (multi-phase strobe) including a plurality of strobes having slightly different phases.
- a multi-strobe multi-phase strobe
- the output signal near the edge is converted into a pattern of H logic and L logic, and the timing of the edge of the output signal is measured by detecting the phase of the strobe at which the output signal changes from H logic to L logic.
- the characteristics of the electronic device to be tested include, for example, the timing of a change point of an output signal from a high impedance (HIZ) level, and the timing of an intersection of differential output signals.
- HZ high impedance
- the level at the intersection of the HIS level and the differential output signal is generally lower than the H comparison level and higher than the L comparison level. For this reason, it is difficult to detect the timing of the transition point from the HIS level or the timing of the crossing point of the differential output signal by the conventional method.
- the conventional method by gradually shifting the H comparison level or the L comparison level, a change point from the HIZ level or a crossing point of the differential output signal can be detected. It is difficult to do.
- an object of the present invention is to provide a measuring device and a program which can solve the above-mentioned problems. This object is achieved by a combination of features described in independent claims in the claims.
- the dependent claims define further advantageous embodiments of the present invention. Disclosure of the invention
- a measuring apparatus for measuring a differential digital signal, the differential digital signal comprising a first digital signal at an edge of the first digital signal.
- a first reference timing detector for detecting a first timing at which the first digital signal has a predetermined first signal level and a second timing at which the first digital signal has a second signal level different from the first signal level; Of the digital signals, at the edge of the second digital signal, a fourth timing at which the second digital signal has a predetermined fourth signal level, and a fifth signal at which the second digital signal is different from the fourth signal level Detect the second timing that becomes the level Based on the first signal level, the second signal level, the fourth signal level, the fifth signal level, the first timing, the second timing, the fourth timing, and the fifth timing.
- a timing calculating section for calculating a timing of an intersection between an edge of the first digital signal and an edge of the second digital signal.
- the timing calculating section calculates a slope of an edge of the first digital signal based on the first timing and the second timing detected by the first reference timing detecting section, and a first slope calculating section, and a second reference timing detecting section.
- a second slope calculation unit that calculates the slope of the edge of the second digital signal based on the fourth timing and the fifth reference timing detected by the unit. The timing of the intersection may be calculated based on the slope of the edge of the digital signal.
- the timing calculator stores the provisional timing of the intersection with respect to each combination of the slope of the edge of the first digital signal and the slope of the edge of the second digital signal.
- ⁇ ⁇ ⁇ ⁇ ⁇ A timing storage unit that outputs temporary timing according to the slope of the edge of the second digital signal, and a unit phase difference between the phase of the first digital signal and the phase of the second digital signal to correct the temporary timing Is stored for each combination of the edge slope of the first digital signal and the edge slope of the second digital signal, and the given slope of the first digital signal,
- a phase shift correction coefficient storage unit that outputs a unit correction coefficient according to the edge gradient of the second digital signal;
- the timing of the intersection may be calculated based on the provisional timing output by the controller and the correction coefficient output by the phase difference calculator.
- a program for causing a measuring device to measure a differential digital signal comprising: In the signal edge, a first timing at which the first digital signal has a predetermined first signal level and a second timing at which the first digital signal has a second signal level different from the first signal level are detected.
- a second reference timing detector for detecting a second timing that is a fifth signal level different from the fourth signal level; and a first signal level, a second signal level, a fourth signal level, a fifth signal level, and a fifth signal level.
- the timing of the intersection of the edge of the first digital signal and the edge of the second digital signal is determined.
- FIG. 1 is a diagram showing an example of a configuration of a measuring apparatus 100 according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an example of the configuration of the level comparing section 20, the multi-strobe circuit 30, and the phase detecting section 40.
- FIG. 3 is a diagram illustrating an example of a waveform of an output signal output by the electronic device 200.
- FIG. 4 is a diagram illustrating an example of the operation of the phase detection unit 40.
- FIG. 4A shows an example of the operation of the signal level detection unit 42, the other logic circuit 46, and the encoder 50-1.
- FIG. 4B shows the signal level detection unit 44, the exclusive logic. An example of the operation of the circuit 48 and the encoder 50-2 will be described.
- FIG. 5 is a diagram illustrating an example of the operation of the timing calculation unit 80.
- FIG. 6 is a diagram showing an example of a digital signal waveform.
- Figure 6 (a) shows the daisy Fig. 6 (b) shows an example in which the digital signal changes from the HIZ level by the falling edge
- Fig. 6 (b) shows an example in which the digital signal changes from the HIZ level by the falling edge
- Figure 6 (d) shows an example where the digital signal goes from the rising edge to the HIZ level from the falling edge.
- FIG. 7 is a diagram showing an example of the configuration of the timing calculation section 80.
- FIG. 8 is a diagram illustrating an example of output data generated by the output data generation unit 96.
- FIG. 9 is a diagram showing another example of the configuration of the measuring apparatus 100.
- FIG. 10 is a diagram illustrating an example of the waveform of the differential digital signal.
- FIG. 11 is a diagram for explaining an example of a method of calculating the timing of the intersection in the timing calculation section 80.
- FIG. 12 is a diagram showing an example of the configuration of the timing calculation section 80.
- FIG. 13 is a diagram illustrating an example of the configuration of the determination unit 140.
- FIG. 14 is a diagram showing an example of a configuration of a computer 300 that controls the measuring apparatus 100. As shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 shows an example of a configuration of a measuring apparatus 100 according to an embodiment of the present invention.
- the measuring apparatus 100 determines the quality of the electronic device 200 by measuring an output signal output from the electronic device 2000.
- the measuring apparatus 100 includes a reference timing detecting unit 10, a timing calculating unit 80, and a determining unit 140.
- the reference timing detection section 20 includes a level comparison section 20, a multi-strobe circuit 30, and a phase detection section 40.
- the level comparison unit 200 outputs the electronic device 200 The obtained digital signal is compared with a first signal level and a second signal level given in advance.
- the level comparison unit 20 is provided with a first signal level (VOH) and a second signal level (VOL) smaller than the first signal level, and compares the result of comparison between the first signal level and the digital signal. Outputs as H data, and outputs the result of comparison between the second signal level and the digital signal as L data.
- VH first signal level
- VOL second signal level
- the multi-strobe circuit 30 generates a multi-strobe having a plurality of strobes having slightly different phases.
- the multi-strobe circuit 30 generates a multi-strobe at substantially the same timing as the edge of the digital signal. Further, the multi-strobe circuit 30 may generate the manhole strobe at a predetermined cycle corresponding to the edge of the digital signal.
- the phase detection unit 40 detects the timing of a change point at which the value changes in the ⁇ data and the L data output by the level comparison unit 20.
- the phase detection unit 40 detects the values of the ⁇ data and the L data at the timing of each strobe included in the multi-slope generated by the multi-strobe circuit 30. Then, the phase of the change point of the values of the ⁇ data and the L data is calculated based on the timing of the strobe that detects the change of the values of the ⁇ data and the L data. Further, the phase detector 40 outputs HCOMP and LCOMP indicating the timing of the change point of the values of the ⁇ data and the L data.
- the reference timing detecting section 10 sets the first timing (HC OM P) at which the digital signal reaches the predetermined first :! signal level at the edge of the digital signal output by the electronic device 200. And a second timing (LCOMP) at which the digital signal becomes a second signal level different from the first signal level.
- the timing calculation section 80 performs digital processing based on the first signal level and the second signal level given to the reference timing detection section 10 and the first timing and the second timing detected by the phase detection section 40. A third timing at which the signal becomes a predetermined third signal level is calculated. In other words, the timing calculation unit 80 The third timing is calculated when the signal changes from the third signal level to another signal level via the first signal level and the second signal level.
- the timing calculation section 80 is provided with the high impedance level of the digital signal as the third signal level, and calculates the change point timing at which the digital signal level changes from the high impedance level as the third timing. The method of calculating the third timing in the timing calculation section 80 will be described in detail with reference to FIG.
- the determination unit 140 determines the quality of the electronic device 200 based on whether the third timing calculated by the timing calculation unit 80 falls within a predetermined range.
- FIG. 2 shows an example of the configuration of the level comparing section 20, the multi-strobe circuit 30, and the phase detecting section 40.
- the level comparing section 20 has a comparator 22 and a comparator 24.
- the comparator 22 is supplied with the first signal level and the digital signal output by the electronic device 200, and outputs H data according to the result of comparison between the first signal level and the digital signal.
- the comparator 22 indicates L logic (pass) when the digital signal value is equal to or higher than the first signal level, and H logic (fail) when the digital signal value is smaller than the first signal level. Outputs H data indicating).
- the comparator 24 is supplied with the second signal level and the digital signal, and outputs L data according to the result of comparison between the second signal level and the digital signal.
- the comparator 24 indicates L logic when the digital signal value is equal to or lower than the second signal level, and indicates H logic when the digital signal value is greater than the second signal level. Output data.
- the multi-strobe circuit 30 includes a plurality of variable delay circuits (32-0 to 32-16, hereinafter collectively referred to as 32), and a plurality of variable delay circuits (34_0 to 34-4-16). , Hereinafter referred to collectively as 34).
- 32 variable delay circuits
- 34 variable delay circuits
- the number of the variable delay circuits 32 and 34 is not limited to 17 as shown in the figure.
- the plurality of variable delay circuits 32 are set so that the delay amounts are slightly different from each other, and respectively delay the strobe signal supplied from the outside with different delay amounts. Outputs a multi-strobe containing multiple strobes with different phases. Similarly, the plurality of variable delay circuits 34 also output a multi-slope including a plurality of strobes having slightly different phases. It is preferable that the plurality of variable delay circuits 32 and the plurality of variable delay circuits 34 output multi-strobes having substantially the same phase of each strobe at substantially the same timing.
- the phase detector 40 includes a plurality of signal level detectors (42-0 to 42-16, hereinafter collectively referred to as 42), a plurality of signal level detectors (44-0 to 444-116). , Hereinafter referred to collectively as 4 4), a plurality of exclusive logic circuits (46-1 to 46-16, hereinafter collectively referred to as 46), and a plurality of exclusive logic circuits (48-:! ⁇ 48-1) 6, hereinafter referred to as 48), an encoder 50-1 and an encoder 50_2.
- the plurality of signal level detectors 42 are provided corresponding to the plurality of variable delay circuits 32, and output the value of H data at the timing of the strobe output from the corresponding variable delay circuit 32.
- the plurality of signal level detectors 44 are provided corresponding to the plurality of variable delay circuits 34, and output the value of L data at the timing of the strobe output from the corresponding variable delay circuit 34.
- Each exclusive logic circuit 46 outputs the exclusive OR of the outputs of two signal level detectors 42 adjacent to each other with the phase (phase number) of the given strobe. That is, when the value of the H data output from the corresponding two signal level detection units 42 changes, the H logic is output.
- each of the exclusive OR circuits 48 outputs the exclusive OR of the outputs of two signal level detectors 44 whose strobe phases are adjacent to each other.
- the plurality of exclusive logic circuits 46 and the plurality of exclusive logic circuits 4.8 each output a signal indicating at which strobe timing the value of the H data and the L data has changed.
- a signal indicating at which strobe timing the value of the H data and the L data has changed In this example, only the bit corresponding to the phase number of the strobe that detected the change in value outputs a 16-bit signal indicating H logic.
- the encoder 501-1 encodes the signals output from the plurality of exclusive logic circuits 46. Then, an HCOMP indicating the phase number of the strobe that has detected the change in the value of the H data in binary is output.
- the encoder 50-2 encodes the signals output from the plurality of exclusive logic circuits 46, and outputs LCOMP indicating the phase number of the strobe that has detected the change in the value of the L data in binary.
- the reference timing detecting section 10 can control the first timing (H.COMP) and the second timing (LCOMP) at which the digital signal becomes the predetermined first signal level and second signal level. Can be detected.
- FIG. 3 shows an example of an output waveform of a digital signal output from the electronic device 200.
- the voltage at the output pin of the electronic device 200 is at a high impedance (HIZ) level.
- the electronic device 200 outputs a digital signal
- the voltage of the output pin of the electronic device 200 changes from the HIZ level.
- the measuring apparatus 100 in the present example calculates the timing of the point of change of the digital signal output from the electronic device 200 from the HIZ level.
- measuring device 100 further includes a means for controlling the first signal level and the second signal level provided to level comparing section 20 in accordance with the content of the measurement. For example, when measuring the pattern of a digital signal in a normal state, the control means compares the first signal level (VOH) higher than the HIZ level and the second signal level (VOL) lower than the HIZ level with the level comparator 20. Give to. Then, the level comparing section 20 converts the digital signal into an H logic and L logic pattern.
- VOH first signal level
- VOL second signal level
- the control means controls the level comparing section 20 to output the HIZ level (third signal level) and the second signal level.
- the first signal level (VOH) having a value between (VOL) and (VOL).
- the multi-strobe circuit 30 generates substantially the same multi-strobe A and multi-strobe B in response to a change edge from the HIZ level.
- the phase detector 40 uses these multi-stroops to set the digital signal to the VOH and VOL levels at the relevant edge of the digital signal. Detect timing. In this example, the timing at which the digital signal becomes the VOH level is detected by the phase number 3 strobe of the multi-strobe A, and the timing at which the digital signal becomes the VOL level is detected by the phase number 5 of the multi-strobe B. Is detected by
- FIG. 4 is a diagram illustrating an example of the operation of the phase detection unit 40.
- FIG. 4A illustrates an example of the operation of the signal level detection unit 42, the exclusive logic circuit 46, and the encoder 50-1.
- Each level detector 42 detects the value of the H data at the timing of each strobe of the multi-stroop A described in FIG.
- each exclusive logic circuit 46 calculates the exclusive OR of adjacent data, and outputs data indicating the phase number of the strobe that has detected the timing at which the digital signal becomes the VOH level.
- the encoder 50-1 encodes the data output from the exclusive logic circuit 46 and outputs HCOMP indicating the phase number of the strobe that has detected the timing at which the digital signal becomes the VOH level in binary. . Since the encoder 50-1 outputs the phase number of the strobe in a binary number, the calculation in the timing calculation unit 80 becomes easy.
- FIG. 4B is a diagram illustrating an example of the operation of the signal level detection unit 44, the exclusive logic circuit 48, and the encoder 50_2.
- the encoder 50-2 outputs the L COMP indicating the phase number of the strobe that has detected the timing at which the digital signal reaches the VOL level in a binary number. .
- FIG. 5 is a diagram illustrating an example of the operation of the timing calculation section 80.
- the timing calculator 80 calculates the digital signal based on the first timing (HCOMP), the second timing (LCOMP), the first signal level (VQH), and the second signal level (VOL) detected by the phase detector 40. Calculate the timing at which the signal reaches the third signal level (HIZ in this example).
- the vertical axis is signal level
- the first signal level is Q
- the second signal level is, the digital signal in the example of FIG.
- the coordinates of point A are (3, a), and the digital signal is at VOL level.
- the coordinates of point B are (5,] 3). That is, the edge of the digital signal is represented by a straight line passing through these two points.
- the point at which the digital signal changes from the HIZ level is the point at which the y coordinate of the straight line passing through the points A and B becomes the HIZ level.
- the timing calculation unit 80 calculates an equation of a straight line passing through the point A and the point B, and calculates the value of the X coordinate at which the y coordinate of the equation becomes the HIZ level, that is, the timing.
- the output of the electronic device 200 is typically terminated at the VTT level in the measuring device 100.
- the HIZ level is equivalent to the VTT level in the measuring device 100 and is a known value. Further, by substituting the value of the desired signal level into the y coordinate of the equation, the timing at which the digital signal reaches the predetermined signal level can be easily calculated.
- the timing of a change point from the HIZ level is further increased. It can be easily calculated.
- HIS-VOH: VOH-VOL 1: 1
- the timing (third timing) of the change point from the HIS level can be easily calculated from HCOMP- (LCOMP-HCOMP). That is, the third timing can be calculated by subtracting the difference between the second timing and the first timing from the first timing.
- FIG. 6 is a diagram showing an example of a digital signal waveform.
- FIG. 6 illustrates a case where a first signal level (VOH) which is intermediate between the HIS level and the second signal level (VOL) is given.
- VH first signal level
- VOL second signal level
- Figure 6 (a) shows an example in which the digital signal changes from the HIZ level by the falling edge.
- the timing calculation unit 80 By calculating MP- (L COMP-HCOMP), the timing of the change point from the HIZ level is calculated. That is, the timing calculation section 80 calculates the third timing by subtracting the difference between the second timing and the first timing from the first timing.
- FIG. 6 (b) shows an example in which the digital signal changes from the HIS level by a falling edge.
- the timing calculation unit 80 calculates the timing of the change point from the HIS level by calculating LCOMP- (HCO MP-L COMP). That is, the timing calculation section 80 calculates the third timing by subtracting the difference between the first timing and the second timing from the second timing. '
- Fig. 6 (c) shows an example in which the digital signal changes from the falling edge to the HIS level.
- the timing calculating section 80 calculates the timing of the change point at every H YZ level by calculating LCOMP + (L COMP-HC OMP). That is, the timing calculation unit 80 calculates the third timing by adding the difference between the second timing and the first timing to the second timing.
- FIG. 6 (d) shows an example in which the digital signal changes from the rising edge to the HIS level.
- the timing calculation unit 80 calculates the timing of the transition point to the HIZ level by calculating HCOMP + (HCOMP-LC OMP). That is, the timing calculation unit 80 calculates the third timing by adding the difference between the first timing and the second timing to the first timing.
- FIGS. 6 (a) to 6 (d) Whether the waveform of the digital signal corresponds to any of FIGS. 6 (a) to 6 (d) depends on the magnitude relationship between HCOMP and LCOMP, and the relationship between the HIZ level and the first and second signal levels. It can be easily determined based on the magnitude relation.
- the timing calculation unit 80 has been described with reference to FIGS. 6A to 6D based on the magnitude relationship between HCOMP and LCOMP, and the magnitude relationship between the HIZ level, the first signal level, and the second signal level. It is preferable to select which of the calculation methods is used to calculate the third timing.
- FIG. 7 shows an example of the configuration of the timing calculation section 80.
- the level comparing section 20 determines that the signal level difference between the third signal level and the first signal level is substantially the same as the signal level difference between the first signal level and the second signal level.
- the signal level and the second signal level are given in advance.
- the timing calculation section 80 includes a magnitude comparison section 82, a first subtraction section 84, a second subtraction section 86, a third subtraction section 88, a first addition section 90, a second addition section 92, a selection section 94, and output data.
- the timing calculator 80 receives the HCOMP indicating the first timing and the LCOMP indicating the second timing from the phase detector 40.
- the magnitude comparison unit 82 determines the magnitude relation between HCOMP and L COMP.
- the first subtraction unit 84 calculates a difference between LCOMP and HCOMP. At this time, the first subtraction unit 84 selects one of HCOMP and L COMP to subtract the other according to the determination result of the magnitude comparison unit 82.
- the second subtraction unit 86 subtracts the value output by the first subtraction unit 84 from HCOMP and outputs the result. That is, the second subtraction unit 86 outputs the value of one HCOMP (LCOMP-HCOMP) described with reference to FIG.
- the third subtraction unit 88 subtracts the value output by the first subtraction unit 84 from L COMP and outputs the result. That is, the third subtraction unit 88 outputs the value of LCOMP— (HCOMP-LCOMP) described with reference to FIG. 6B.
- the first adder 90 adds the value output by the first subtractor 84 to HCOMP and outputs the result. That is, the first adder 90 outputs the value of HCOMP + (H COMP ⁇ LCOMP) described in FIG. 6D.
- the second adder 92 adds the value output by the first subtractor 84 to LCOMP and outputs the result. That is, the second adding unit 92 outputs the value of LCOMP + (L COMP-HCOMP) described in FIG. 6C.
- the selection unit 94 is configured to output one of the values output by the second subtraction unit 86, the third subtraction unit 88, the first addition unit 90, or the second addition unit 92 based on the control signal and the determination result of the magnitude comparison unit 82. Select and output.
- the control signal is the HIZ level and the first signal This signal is determined by the magnitude relation between the level and the second signal level.
- the output data generation unit 96 generates output data to be passed to the determination unit 140 based on the data output from the selection unit 94.
- FIG. 8 shows an example of output data generated by the output data generation unit 96.
- the output data generation unit 96 converts the data output from the selection unit 94 into a bit indicating the position of a change from the HIZ level, a bit indicating the initial value of the H data, a bit indicating the presence or absence of glitch, and an error.
- Output data including a bit indicating the presence or absence of
- the output data generation unit 96 is used when the data output by the exclusive logic circuit 46 or the data output by the exclusive logic circuit 48 described in FIG. It determines that there is a glitch at the edge of the digital signal, and generates output data with the bit indicating the presence or absence of the glitch being set to "1". In addition, when the data selected by the selection unit 94 indicates a negative value, the output data generation unit 96 generates output data with the bit indicating the presence or absence of an error as 1 as an operation error.
- the quality of electronic device 200 can be more accurately determined.
- the determination unit 140 determines whether or not the timing of the change point from the HIZ level is within a predetermined range and whether or not the edge of the digital signal has a dalitch. The quality of 200 may be determined.
- FIG. 9 shows another example of the configuration of the measuring apparatus 100.
- the measuring apparatus 100 in this example measures the timing of the intersection where the differential digital signals output from the electronic device 200 cross.
- the point of intersection of the differential digital signals is a point where both signals of the differential digital signals have the same signal level at the same timing.
- the measuring apparatus 100 in the present example includes a first reference timing detection unit 100a, a second reference timing detection unit 100b, a timing calculation unit 80, and a determination unit 140.
- the first reference timing detection unit 10a and the second reference timing detection unit 10b have substantially the same function and configuration as the reference timing detection unit 10 described with reference to FIG.
- components denoted by the same reference numerals as those in FIG. 1 have substantially the same functions and configurations as the components described with reference to FIG.
- the first reference timing detection unit 100a outputs the first digital signal at a predetermined first signal level at the edge of the first digital signal among the differential digital signals output by the electronic device 200. A first timing and a second timing at which the first digital signal has a second signal level different from the i-th signal level are detected.
- the method of detecting the first timing and the second timing is the same as the method of detecting the first timing and the second timing described with reference to FIG.
- the second reference timing detection unit 100b sets the second digital signal to a predetermined fourth signal level at the edge of the second digital signal among the differential digital signals output by the electronic device 200.
- a fourth timing and a second timing at which the second digital signal has a fifth signal level different from the fourth signal level are detected.
- the method of detecting the fourth timing and the fifth timing is the same as the method of detecting the first timing and the second timing described with reference to FIG.
- the timing calculator 80 performs the first digital signal based on the first signal level, the second signal level, the fourth signal level, the fifth signal level, the first timing, the second timing, the fourth timing, and the fifth timing. Calculate the timing of the intersection of the signal edge and the second digital signal edge. For example, the timing calculating section 80 calculates the edge equation of the first digital signal based on the first signal level, the second signal level, the first timing, and the second timing as described in FIG. And calculating an edge equation of the second digital signal based on the fourth signal level, the fifth signal level, the fourth timing, and the fifth timing. Then, the timing at which the edge equation of the first digital signal and the edge equation of the second digital signal intersect is calculated.
- the determination unit 140 determines that the timing of the intersection calculated by the timing calculation unit 80 is The quality of the electronic device 200 is determined based on whether the electronic device 200 is within a predetermined range.
- FIG. 10 shows an example of the waveform of the differential digital signal.
- the first reference timing detector 10a sets the first digital signal to the first signal level (VOH) at the edge of the first digital signal output from the differential pin 1 of the electronic device.
- the first timing (HCOMP 1) and the second timing (LCOMP 1) at which the first digital signal becomes the second signal level (VOL) are detected.
- the second reference timing detection unit 10b outputs the fourth timing (VOH) at which the second digital signal becomes the fourth signal level (VOH) at the edge of the second digital signal output from the differential pin 2 of the electronic device.
- HCOMP 2 the fourth timing
- LCOMP 2 the fifth timing
- the first signal level is equal to the fourth signal level
- the second signal level is equal to the fifth signal level.
- the timing calculator 80 calculates the slope of the edge of the first digital signal based on the first timing and the second timing detected by the first reference timing detector 10a. Further, the timing calculation section 80 calculates the slope of the edge of the second digital signal based on the fourth timing and the fifth reference timing detected by the second reference timing detection section 10b. Then, the timing calculation section 80 calculates the timing of the intersection of the differential digital signals based on the slope of the edge of the first digital signal and the slope of the edge of the second digital signal.
- FIG. 11 is a diagram illustrating an example of a method of calculating the timing of the intersection at timing calculation section 80.
- the horizontal axis indicates timing
- the vertical axis indicates signal level.
- the timing of L COMP at the rising edge is defined as the origin.
- L COMM 2 the origin.
- the straight line of the edge of the first digital signal is moved in parallel so that the first timing (HCOMP 1) and the fourth timing (LC '2MP 2) coincide, and HC OMP 1' and LCOMP 1 ' Find a straight line passing through the two points. And translate The intersection of the straight line passing through the two points LCOMP 2 and HCOMP 2 is calculated as the provisional intersection.
- the timing calculation unit 80 calculates the timing of the provisional intersection based on the timing of the edge of the first digital signal and the inclination of the edge of the second digital signal.
- the timing calculating section 80 calculates a difference between the timing of the original intersection and the timing of the provisional intersection from the inclination of each edge and the amount of parallel movement of the straight line. Then, the difference of the timing is added to the calculated provisional intersection. First, since the second digital signal is translated in parallel so that LC ⁇ ⁇ 2 becomes the origin, this phase shift is further added to the timing of the provisional intersection, and the timing of the intersection of the differential digital signals is calculated. calculate.
- FIG. 12 shows an example of the configuration of the timing calculation section 80.
- the timing calculation unit 80 includes a comparison unit (102, 104, 116), a subtraction unit (106, 108, 122, 126), an addition unit (128, 132), and a timing storage unit 1 1 8, a phase shift correction coefficient storage unit 120, a multiplication unit 124, a selection unit (110, 112, 130), an error detection unit 114, and an output data generation unit 134.
- the comparing unit 102 receives the first timing (HC ⁇ 1) and the second timing (LCOMP 1) at the edge of the first digital signal, and determines the magnitude relationship between the first timing and the second timing. It is determined whether the corresponding edge of the first digital signal is a rising edge or a falling edge.
- the comparison unit 104 receives the fourth timing (HC ⁇ 2) and the fifth timing (LCOMP 2) at the edge of the second digital signal, and determines the magnitude relationship between the fourth timing and the fifth timing. Then, it is determined whether the corresponding edge of the second digital signal is a rising edge or a falling edge.
- the subtraction unit 106 calculates a timing difference between the first timing (HCOMP 1) and the second timing (LCO MP 1). At this time, the subtraction unit 106 determines whether to subtract the other from the first timing or the second timing according to the determination result of the comparison unit 102. Since the values of VOH and VOL are known, The slope of the edge of the first digital signal is determined by the timing difference between the first digital signal and the second timing. That is, the subtraction unit 106 functions as a first slope calculation unit that outputs the timing difference as a value indicating the slope of the edge of the first digital signal. The subtraction unit 108 calculates a timing difference between the fourth timing (HCOMP 2) and the fifth timing (LCOMP 2).
- the subtraction unit 108 determines which of the fourth timing and the fifth timing to subtract the other according to the determination result of the comparison unit 104. Similarly, the subtraction unit 108 functions as a second slope calculation unit that outputs the timing difference as a value indicating the slope of the edge of the second digital signal.
- the timing storage unit 118 stores the provisional timing of the intersection of the differential digital signal with respect to each combination of the slope of the edge of the first digital signal and the slope of the edge of the second digital signal. It outputs provisional timing according to the slope of the edge of the first digital signal and the slope of the edge of the second digital signal.
- the phase shift correction coefficient storage section 120 stores a correction coefficient for correcting the provisional timing output from the timing storage section 118 as described with reference to FIG.
- the phase shift correction coefficient storage section 120 stores the unit correction coefficient per unit phase difference between the phase of the first digital signal and the phase of the second digital signal, Stores each combination of the slope and the edge slope of the second digital signal, and outputs a unit correction coefficient according to the given slope of the first digital signal and the slope of the edge of the second digital signal.
- the selection unit 110 sets a reference phase for calculating a phase difference between the phase of the first digital signal and the phase of the second digital signal to LC OM P 1 (second timing) or LC OM P 2 (fifth timing). Timing). In this example, the selection unit 110 determines whether the edge of the first digital signal and the edge of the second digital signal are shifted or shifted based on the determination result of the comparison unit 102, and determines whether the edge is a rising edge. Select LC OMP in.
- the selection unit 112 sets the reference phase for calculating the phase difference between the phase of the first digital signal and the phase of the second digital signal to HC OM P 1 (first timing) or HC OM P 2 (fourth Timing). In this example, the selection unit 112 determines whether the edge of the first digital signal or the edge of the second digital signal is the falling edge based on the determination result of the comparison unit 102, and determines the falling edge. Select HC OM P in.
- the comparing section 1 16 determines the magnitude relationship between the reference phase selected by the selecting section 110 and the reference phase selected by the selecting section 112. Further, the subtraction unit 122 calculates the difference between the reference phase selected by the selection unit 110 and the reference phase selected by the selection unit 112. At this time, the subtraction unit 122 determines which reference phase to subtract from the other according to the determination result of the comparison unit 116.
- the subtraction unit 122 functions as a phase difference calculation unit that calculates a phase difference between the phase of the first digital signal and the phase of the second digital signal.
- the multiplication unit 124 calculates a correction coefficient obtained by multiplying the phase difference calculated by the subtraction unit 122 and the unit correction coefficient output by the phase shift correction coefficient storage unit 120.
- addition section 128 outputs a value obtained by adding the correction coefficient calculated by multiplication section 124 to the reference phase selected by selection section 110. Further, the subtraction unit 126 outputs a value obtained by subtracting the correction coefficient calculated by the multiplication unit 124 from the reference phase selected by the selection unit 110.
- the selection unit 130 selects and outputs one of the values output by the subtraction unit 126 or the addition unit 128 based on the determination result of the comparison unit 116. That is, the selection unit 130, for example, based on the magnitude relationship between the reference phase selected by the selection unit 110 and the reference phase selected by the selection unit 112, for example, of the first digital signal in the example of FIG. It is determined whether the edge has been shifted in the positive or negative direction, and a selection is made as to whether to add or subtract the correction coefficient calculated by the multiplication unit 124 according to the determination result.
- the adder 132 adds the value selected by the selector 130 and the provisional timing output by the timing storage 118 to calculate the timing of the intersection of the differential digital signals. Further, the output data generation unit 134 transfers the output data to the determination unit 140 based on the timing of the intersection of the differential digital signals calculated by the addition unit 132. Generate output data.
- the output data generator 134 may have the same function as the output data generator 96 described in FIG.
- the error detection unit 114 receives the determination results of the comparison unit 102 and the comparison unit 104, and the edge of the first digital signal and the edge of the second digital signal are both rising edges or both falling edges. If it is an edge, detect a measurement error and notify outside.
- the timing calculation section 80 in this example the timing of the intersection of the differential digital signals can be easily calculated.
- FIG. 13 shows an example of the configuration of the determination section 140.
- the measuring apparatus 100 includes a timing calculating unit 80a that calculates the timing of a change point from the HIZ level, and a timing calculating unit 80b that calculates the timing of the intersection of the differential digital signals. Measure the timing of the transition point from the HIZ level of the first digital signal and the timing of the intersection of the differential digital signals simultaneously.
- the HCOMP data and the LCOMP data include glitch detection bits, initial value bits, and the like.
- the timing calculation section 80a has the same function and configuration as the timing calculation section 80 described with reference to FIG. 7, and the timing calculation section 80b includes the timing calculation section 80b described with reference to FIG. It has the same function and configuration as.
- the determination unit 140 includes a shift unit 142, a selection unit 148, a selection unit 150, a logical comparator 152, a logical comparator 154, a subtraction unit 160, a memory 156, a memory 158, a comparison unit 162, a comparison unit. 164, OR circuit 166, AND circuit 168, and latch circuit 170.
- the shift unit 142 performs a cycle shift so that the data of HCOMP1 and LCOMP1 can be logically compared with the data of HCOMP2 and LCOMP2.
- the shift unit 142 has a plurality of latch circuits 144 and a latch circuit 146 for performing cycle / shift.
- the selection unit 148 includes HCOMP 1, LCOMP 1, HCOMP 2, LCO MP 2 selects and outputs either data output from the timing calculation section 80a or data output from the timing calculation section 80b.
- the selector 150 selects and outputs one of HCOM P1, LCOMP1, HCOMP2, or LCOMP2.
- the selectors 148 and 150 are supplied with data select signals indicating which data should be selected in accordance with the test content.
- the selector 148 and the selector 150 may output data having a value of zero.
- the selector 148 selects the data output by the timing calculator 80a, and the selector 150 Outputs zero data.
- the subtraction unit 160 calculates a value obtained by subtracting the data selected by the selection unit 150 from the data selected by the selection unit 148.
- the P 0 terminal in the subtraction unit 160 is a code terminal.
- a lower limit value of data to be output by the subtraction unit 160 is stored in advance in accordance with the test content.
- the upper limit of the data to be output by the subtraction unit 160 is stored in the memory 156 in advance according to the test content.
- the comparing unit 162 determines whether the data output by the subtracting unit 160 is equal to or larger than the lower limit value stored in the memory 156. For example, when the data output by the subtraction unit 160 is smaller than the lower limit, the comparison unit 162 outputs 1 as a failure.
- the comparing section 164 determines whether or not the data output from the subtracting section 160 is equal to or less than the upper limit value stored in the memory 156. For example, when the data output by the subtraction unit 160 is larger than the upper limit value, the comparison unit 164 outputs 1 as a failure.
- the logical comparator 152 outputs 1 as a file when the data selected by the selection unit 148 includes data indicating the presence of a darich.
- the logical comparator 153 outputs 1 as a file when the data selected by the selection unit 150 includes data indicating the presence of a dalitci.
- the OR circuit 166 outputs a signal when at least one of the logical comparator 152, the logical comparator 154, the comparing section 162, or the comparing section 164 outputs 1 as a failure. Output 1 as an aile.
- the logical AND circuit 168 is provided with a logical comparison control signal for controlling whether or not to perform the pass / fail judgment of the electronic device 200. When the logical comparison control signal is 1, the logical sum circuit 166 Outputting the output to the latch circuit 170 c By such an operation, the quality of the electronic device 200 can be easily determined.
- FIG. 14 shows an example of a configuration of a computer 300 that controls the measuring apparatus 100.
- the computer 300 stores a program that causes the measuring device 100 to function as the measuring device 100 described with reference to FIGS. 1 to 13. Further, the combination device 300 may function as the measurement device 100.
- the computer 300 includes a CPU 700, a ROM 702, a RAM 704, a communication interface 706, a hard disk drive 710, an FD disk drive 712, and a CD-ROM drive 716.
- CPU 700 operates based on programs stored in ROM 702, RAM 704, hard disk 710, FD disk 714, and / or CD-ROM 718.
- the program includes the computer 300 as the reference timing detecting unit 10, the timing calculating unit 80, and the determining unit described with reference to FIG. 1 or FIG. Function as 140.
- the communication interface 706 controls the measuring device 100 in accordance with the program, by referring to the reference timing detecting portion 10, the timing calculating portion 80, and the timing calculating portion 10 described with reference to FIG. ⁇ Transmit a control signal to function as the determination unit 140.
- a hard disk drive 710, ROM 702, or RAM 704 as an example of a storage device stores setting information, a program for operating the CPU 700, and the like. Further, the program may be stored in a recording medium such as a flexible disk 720 or a CD-ROM 722.
- the flexible drive 712 reads the program from the flexible disk 714 and provides the program to the CPU 700 when the flexible disk 714 stores the program.
- CD-ROM drive 716 CD-ROM stores programs If so, read the program from the CD-ROM 718 and provide it to the CPU 700.
- the program may be directly read out from the recording medium to the RAM and executed, or may be read out and executed in the RAM after being installed in the hard disk drive.
- the program may be stored on a single recording medium or on a plurality of recording media.
- the program stored in the recording medium may provide each function in cooperation with the operating system. For example, the program may request the operating system to perform a part or all of the function, and provide the function based on a response from the operating system.
- Recording media for storing programs include flexible disks, CD-ROMs, optical recording media such as DVDs and PDs, magneto-optical recording media such as MDs, tape media, magnetic recording media, IC cards and miniature cards. Semiconductor memory and the like can be used. Further, a storage device such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium. ⁇
- the timing measured by the measuring apparatus 100 is not limited to the timing of the point of change from the HIZ level or the timing of the intersection of the differential digital signals. For example, it is clear that the timing of the transition point from the L level at the rising edge of the digital signal can be easily measured. Industrial applicability As is clear from the above description, according to the present invention, it is possible to easily calculate the timing at which the output signal output from the electronic device changes from the HIZ level. Further, the timing of the intersection of the differential digital signals output from the electronic device can be easily calculated.
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- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Measuring Phase Differences (AREA)
Abstract
Description
Claims
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DE112004000730T DE112004000730T5 (de) | 2003-04-25 | 2004-04-26 | Messvorrichtung und Programm |
US11/256,048 US7209853B2 (en) | 2003-04-25 | 2005-10-21 | Measuring apparatus and program |
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JP2003122130A JP4429625B2 (ja) | 2003-04-25 | 2003-04-25 | 測定装置、及びプログラム |
JP2003-122130 | 2003-04-25 |
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US11/256,048 Continuation US7209853B2 (en) | 2003-04-25 | 2005-10-21 | Measuring apparatus and program |
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PCT/JP2004/005982 WO2004097439A1 (ja) | 2003-04-25 | 2004-04-26 | 測定装置、及びプログラム |
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US (1) | US7209853B2 (ja) |
JP (1) | JP4429625B2 (ja) |
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US7126366B2 (en) * | 2002-06-10 | 2006-10-24 | Advantest Corp. | Semiconductor test apparatus |
JP4875889B2 (ja) * | 2005-12-08 | 2012-02-15 | ハイデンハイン株式会社 | エンコーダのカウントミス検出回路およびエンコーダのカウントミス検出方法 |
US7671602B1 (en) * | 2007-01-24 | 2010-03-02 | Integrated Device Technology, Inc. | Method and apparatus for cross-point detection |
KR20100034030A (ko) | 2007-06-27 | 2010-03-31 | 가부시키가이샤 어드밴티스트 | 검출 장치 및 시험 장치 |
JP5226014B2 (ja) * | 2008-01-23 | 2013-07-03 | 株式会社アドバンテスト | 試験装置 |
JP5210646B2 (ja) * | 2008-01-25 | 2013-06-12 | 株式会社アドバンテスト | 被測定信号の変化点を検出する装置、方法および試験装置 |
DE112009000703T5 (de) | 2008-03-27 | 2011-02-17 | Advantest Corp. | Messvorrichtung, Parallelmessvorrichtung, Testvorrichtung, elektronische Anordnung |
US7945403B2 (en) * | 2008-05-08 | 2011-05-17 | Advantest Corporation | Signal measurement apparatus, signal measurement method, recording media and test apparatus |
JP2011169594A (ja) * | 2008-06-13 | 2011-09-01 | Advantest Corp | マルチストローブ回路およびそのキャリブレーション方法および試験装置 |
US20110054827A1 (en) * | 2009-08-26 | 2011-03-03 | Advantest Corporation, a Japanese Corporation | Test apparatus and method for modulated signal |
US10084492B2 (en) | 2014-05-05 | 2018-09-25 | Raytheon Company | Method and system for non-persistent real-time encryption key distribution |
Citations (2)
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JPS58111525A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | タイミング検出回路 |
JP2004045085A (ja) * | 2002-07-09 | 2004-02-12 | Matsushita Electric Ind Co Ltd | クロスオーバ電圧評価方法および検査装置 |
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US6263290B1 (en) * | 1995-02-22 | 2001-07-17 | Michael K. Williams | Process and machine for signal waveform analysis |
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2004
- 2004-04-26 DE DE112004000730T patent/DE112004000730T5/de not_active Withdrawn
- 2004-04-26 WO PCT/JP2004/005982 patent/WO2004097439A1/ja active Application Filing
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS58111525A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | タイミング検出回路 |
JP2004045085A (ja) * | 2002-07-09 | 2004-02-12 | Matsushita Electric Ind Co Ltd | クロスオーバ電圧評価方法および検査装置 |
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US7209853B2 (en) | 2007-04-24 |
US20060036411A1 (en) | 2006-02-16 |
JP4429625B2 (ja) | 2010-03-10 |
DE112004000730T5 (de) | 2006-03-16 |
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