WO2004090915A1 - チップ抵抗器およびその製造方法 - Google Patents
チップ抵抗器およびその製造方法 Download PDFInfo
- Publication number
- WO2004090915A1 WO2004090915A1 PCT/JP2004/005038 JP2004005038W WO2004090915A1 WO 2004090915 A1 WO2004090915 A1 WO 2004090915A1 JP 2004005038 W JP2004005038 W JP 2004005038W WO 2004090915 A1 WO2004090915 A1 WO 2004090915A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resistor
- insulating layer
- electrode
- thickness
- chip resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/003—Thick film resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
Definitions
- the present invention relates to a chip resistor and a method for manufacturing the same.
- FIG. 11 of the present application shows a conventional chip resistor disclosed in Japanese Patent Application Publication No. 2002-57009.
- This resistor includes a metal resistor 90 and a pair of electrodes 91 attached to the lower surface of the resistor. These electrodes 91 are separated from each other by a predetermined distance S6. On the lower surface of each electrode 91, a solder layer 92 is formed. ,
- the above-mentioned conventional chip resistor is manufactured by the method shown in FIG. First, two metal plates 90 'and 91' are prepared (ST1), and the metal plate 90 'is joined to the upper surface of the metal plate 91' (ST2). Next, a part of the metal plate 91 ′ is cut by machining to form a void 93 (ST3). Next, a solder layer 92, is formed on the lower surface of the metal plate 91 '(ST4). This gives an intermediate assembly consisting of the metal plates 90 ', 91' and the solder layer 92 '. Finally, by cutting the intermediate assembly, a desired chip resistor is obtained (ST5).
- the above chip resistor has the following problems. As shown in FIG.
- the resistor 90 of the above chip resistor is supported by electrodes 91 that are spaced apart from each other. Due to such a structure, the resistor 90 may bend or break when an impact force is applied to the central portion thereof. Such an impact force can be generated, for example, when the chip resistor is automatically mounted on a circuit board using a suction collet. Disclosure of the invention
- a chip resistor provided according to a first aspect of the present invention includes: a resistor including an electrode forming surface; at least two electrodes provided on the electrode forming surface; and an insulating layer provided on the electrode forming surface.
- the electrode forming surface includes an inter-electrode region located between the two electrodes and covered by the insulating layer.
- the insulating layer has a thickness that is the same or substantially the same as the thickness of the electrode.
- the thickness of the insulating layer is smaller than the thickness of the electrode.
- the difference between the thickness of the insulating layer and the thickness of the electrode is such that, when the resistor is deflected by receiving a load, the insulating layer contacts the flat mounting surface before the resistor is damaged. Is set to.
- the thickness of the insulating layer is smaller than the thickness of the electrode.
- the insulating layer is formed by thick film printing.
- the method for manufacturing a chip resistor provided by the second aspect of the present invention includes: a step of patterning an insulating layer on an electrode forming surface of a resistor material member; Forming a conductive layer having the same or substantially the same thickness as the insulating layer in a region where the insulating material is not formed; and dividing the resistor material member into a plurality of chip-shaped resistors. ing. The division of the resistor material is performed such that each of the plurality of chip-shaped resistors includes a part of the insulating layer and an electrode part separated by the part of the insulating layer.
- the pattern formation of the insulating layer is performed by thick film printing.
- the formation of the conductive layer is performed by a plating process.
- the division of the resistor material member is performed by punching or cutting.
- FIG. 1 is a perspective view showing a chip resistor according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along line II-II in FIG. 3A to 3C are perspective views showing a part of the steps of the method of manufacturing the chip resistor.
- FIG. 4A to 4B are perspective views showing a step performed after the step of FIG. 3C.
- FIG. 5 is a perspective view showing a part of the steps of another manufacturing method of the chip resistor.
- 6A to 6B are perspective views showing a step performed after the step of FIG.
- FIG. 7 is a sectional view showing a chip resistor according to the second embodiment of the present invention.
- FIG. 8A is a sectional view showing a chip resistor according to the third embodiment of the present invention.
- FIG. 8B is a bottom view showing the chip resistor of the third embodiment.
- FIG. 9A is a sectional view showing a chip resistor according to a fourth embodiment of the present invention.
- FIG. 9B is a bottom view showing the chip resistor of the fourth embodiment.
- FIG. 10 is a perspective view showing a chip resistor according to a fifth embodiment of the present invention.
- FIG. 11 is a perspective view showing a conventional chip resistor.
- FIG. 12 shows a method for manufacturing the above-mentioned conventional chip resistor.
- the illustrated chip resistor A1 includes a resistor 1, a first insulating layer 2A, a second insulating layer 2B, and a pair of electrodes 3.
- the resistor 1 has an elongated rectangular shape and a constant thickness.
- the resistor 1 can be formed using a metal material such as a Ni—Cu-based alloy, a ⁇ 11-3 ⁇ 4 ⁇ 11-based alloy, or a Ni—Cr-based alloy.
- a metal material such as a Ni—Cu-based alloy, a ⁇ 11-3 ⁇ 4 ⁇ 11-based alloy, or a Ni—Cr-based alloy.
- the metal material for forming the resistor is not limited to these, and another metal material having a resistivity suitable for the size and the target resistance value of the chip resistor A1 may be used.
- the first and second insulating layers 2A, 2B are made of, for example, epoxy resin.
- the first insulating layer 2A is provided on the lower surface (electrode formation surface) 10b of the resistor 1, and the second insulating layer 2B is provided on the upper surface 10a of the resistor 1. More specifically, the lower surface 10b of the resistor 1 can be divided into a region where the two electrodes 3 are formed and a region other than the region (hereinafter, referred to as an "inter-electrode region").
- the first insulating layer 2A covers the entire area between the electrodes.
- the second insulating layer 2B covers the entire upper surface 10a of the resistor 1 Is covered.
- the pair of electrodes 3 are provided apart from each other in the longitudinal direction of the resistor 1.
- Each electrode 3 is made of, for example, copper.
- each electrode 3 is in contact with the end face 20 of the first insulating layer 2A. Therefore, the distance between the two electrodes 3 is the same as the length s1 of the first insulating layer 2A.
- a solder layer 39 for improving solderability is formed on the lower surface of each electrode 3.
- the resistance value of the chip resistor A1 (the resistance value between the pair of electrodes 3) is set, for example, in the range of 1 ⁇ to 10 ° ⁇ .
- the thickness t1 of the electrode 3 and the thickness t2 of the first insulating layer 2 ⁇ are the same or substantially the same.
- the resistor 1 can be supported by the two electrodes 3 and the insulating layer 2A. Therefore, compared to the conventional chip resistor (FIG. 11), the chip resistor A 1 of the present invention is less likely to be damaged even when an impact force is applied to the center of the resistor 1.
- a metal plate 1A having a uniform thickness throughout is prepared.
- the plate 1A has such a size (length ⁇ width) that a plurality of resistors 1 can be obtained.
- an insulating layer 2B ' is formed so as to cover the entire upper surface 10a of the plate 1A.
- the formation of the insulating layer 2B is performed, for example, by printing a thick film of epoxy resin. If necessary, a step of marking the surface of the formed insulating layer 2B 'may be performed.
- FIG. 3C a plurality of insulating strips 2A 'extending parallel to each other are formed on the lower surface 10b of the plate 1A.
- each insulating strip 2A ' is separated from each other by a predetermined distance in the horizontal direction of the figure.
- the insulating strip 2A ' is formed by thick film printing using the same resin and apparatus as used for forming the insulating layer 2B'. According to the thick film printing, the size (especially the width) of each insulating strip 2A 'can be accurately finished to a predetermined dimension. In addition, the thickness of each insulating strip 2A 'can be easily increased or decreased.
- a conductive layer 3A ' is formed in a region between the plurality of insulating strips 2A', and a solder layer 39A 'is formed on each conductive layer 3A'.
- the conductive layer 3A ' is a portion that becomes the original shape of the electrode 3, and is formed by, for example, copper plating. According to the plating process, each conductive layer 3 A ′ and its adjacent It is possible to avoid creating a gap between the insulating strip 2A '. Therefore, the distance between adjacent conductive layers 3A 'is the same as the width of insulating strip 2A'. As described above, the width of the insulating strip 2A 'can be accurately finished to a predetermined dimension by thick film printing.
- the distance between the adjacent conductive layers 3A '(and thus the distance between the pair of electrodes 3) can be accurately finished to a predetermined size. Further, in the plating process, the thickness of each conductive layer 3A 'can be adjusted by adjusting the processing time. Therefore, the thickness of each electrode 3 and the first insulating layer 2A can be easily made substantially the same.
- the formation of the solder layer 39 A can also be performed by plating.
- the plate 1A is repeatedly punched as shown in FIG. 4B.
- one punching die (not shown) is used repeatedly for this punching.
- the punching operation is performed on each of a plurality of rectangular areas (indicated by dashed lines) shown in FIG. 4B. These rectangular areas are arranged in a matrix state, and adjacent rectangular areas are separated from each other by a predetermined distance S2. As shown in the figure, the center of each rectangular area overlaps with the insulating strip 2A ', and the two ends adjacent to the center overlap with the solder layer 39A ,. I'm wrapping. By punching such a rectangular area, a desired chip resistor A1 can be obtained.
- the above-mentioned method of manufacturing a chip resistor has the following advantages over the conventional manufacturing method (Fig. 12). That is, in the conventional method, the metal plate 9 1 ′ was mechanically cut when the pair of electrodes 91 separated from each other was provided (ST 3 in FIG. 12). The distance between the two electrodes 91 (S6 in Fig. 11) affects the resistance of the chip resistor. For this reason, in order to finish the resistance value to a desired value, it is necessary to accurately perform a cutting operation of the metal plate 9 1 ′. However, such work requires careful and time-consuming work that can hinder chip resistor productivity. On the other hand, in the manufacturing method of the present invention, as described above with reference to FIG. 4A, the setting of the separation distance between the pair of electrodes 3 can be extremely easily and accurately performed by the plating process. it can.
- a shearing machine or a rotary cutter is used as means for obtaining a plurality of resistors from the plate 1A.
- Any cutting means may be used.
- the plate 1A shown in FIG. 4A is cut along a cutting line C1 shown in FIG. 5 (each cutting line C1 is an insulating strip 2A 'and a conductive layer 3A'). Extending at right angles to the longitudinal direction).
- a plurality of bar-shaped resistor aggregates A 1 ′ shown in FIG. 6A are obtained.
- each resistor assembly A 1 ′ is cut along a cutting line C 2.
- one resistor assembly A 1 ′ force ⁇ a plurality of chip resistors A 1 are obtained.
- the chip resistor A1 of the present invention can be surface-mounted on a circuit board using, for example, a solder reflow technique. Specifically, the chip resistor A1 is mounted on the circuit board so that each electrode 3 (solder layer 39) contacts a terminal provided on the circuit board. In this state, the circuit board and the chip resistor A1 are heated in the reflow furnace. Thereafter, the chip resistor A1 is fixed to the circuit board by cooling and solidifying the molten solder.
- molten solder may protrude from between the electrode of the resistor and the circuit board.
- the molten solder may adhere to the lower surface of the resistor 90 (between the electrodes), and the expected resistance may not be obtained.
- the chip resistor A 1 FIGGS. 1 and 2) of the present invention, the region between the electrodes of the resistor 1 is covered with the first insulating layer 2A. Therefore, the molten solder does not adhere to the region between the electrodes.
- the upper surface 10a of the chip resistor A1 is covered with the second insulating layer 2B. With this configuration, the upper surface 10a is prevented from coming into improper contact with other conductive members.
- the thickness t2 of the first insulating layer 2A and the thickness tl of the electrode 3 are the same or substantially the same.
- t2 is greater than tl (t2> tl) and vice versa (t2 ⁇ tl).
- the size of t2 is, for example, such that the first insulating layer 2A does not protrude downward beyond the lower surface of the solder layer 39.
- the size of t2 is within the range described below.
- the chip resistor A 1 is regarded as a simple support beam (both ends of the antibody 1 are supported by a pair of electrodes 3), and furthermore, the resistor 1 is regarded as being elastically deformed under an evenly distributed load.
- the maximum bending stress ⁇ max and maximum The radius ⁇ max is given by Equations 1 and 2 below.
- w is an evenly distributed load applied to the resistor 1
- E is the modulus of longitudinal elasticity of the resistor 1
- si is the dimension between the electrodes 3
- Z and I are the resistors 1 defined by the following equation 34. Are the section modulus and second moment of area.
- Equation 14 when the maximum radius ⁇ max at which the maximum bending stress ⁇ max reaches the elastic limit ⁇ y is obtained, it is obtained as expressed in Equation 5.
- the relationship of the following Expression 6 may be established. That is, if the difference between the thicknesses tlt 2 is within the range shown in Expression 6, the inter-electrode portion of the resistor 1 is bent until the surface of the first insulating layer 2A is at the same height as the electrode 3, and thereafter Will be supported by the mounting surface of the circuit board (assuming that the mounting surface of the circuit board is flat). Therefore, the maximum bending stress ⁇ max generated in the resistor 1 does not reach the elastic limit ⁇ y, and the effect of preventing the resistor 1 from being damaged can be obtained. - ⁇ —- ⁇ - ⁇ - ⁇ ⁇ ⁇ ⁇ (6)
- the elastic limit referred to in the present invention means the yield stress in the case of a steel material or the like, and means 0.2% resistance in the case of a non-ferrous material.
- the Ni_Cu-based alloy, the Cu-Mn-based alloy, the Ni-Cr-based alloy, etc. forming the resistor 1 are non-ferrous materials. Therefore, it is appropriate to use 0.2% resistance to these materials as the ⁇ life limit ⁇ y.
- An example of a numerical value substituted into the right side of the above Expression 6 is as follows.
- t 1 ⁇ t 2 is less than about 30 ⁇ .
- the numerical value setting includes, for example, the material of the resistor 1, the size of the chip resistor, the relative positional relationship with the mounting object (such as a circuit board), the reference amount (the amount of radius, Stress value).
- FIG. 7 shows a chip resistor A2 according to a second embodiment of the present invention.
- the chip resistor A2 has the same configuration as the chip resistor A1 of the first embodiment, except for the following points. That is, in the first embodiment, the thickness of the first insulating layer 2A is uniform, but in the second embodiment, the thickness of the first insulating layer 2A is non-uniform.
- the first insulating layer 2A of the second embodiment has a trapezoidal cross section.
- the thickness at the center of the trapezoid that is, the maximum thickness of the first insulating layer) t 2
- the impact force applied to the chip resistor A2 can be borne by the pair of electrodes 3 and the first insulating layer 2A.
- FIG. 8A and 8B show a chip resistor A3 according to a third embodiment of the present invention.
- the chip resistor A3 in the chip resistor A3, four electrodes 3 are provided on the lower surface of the resistor 1. A region of the lower surface of the resistor 1 where the four electrodes 3 are not provided is covered with the first insulating layer 2A.
- the chip resistor A3 is substantially the same as the chip resistor A1 of the first embodiment.
- the chip resistor A3 can be used as follows. That is, of the four electrodes 3, two electrodes 3 are used as current electrodes, and the remaining two electrodes 3 are used as voltage electrodes.
- the pair of current electrodes 3 is connected in series to the current path of the electric circuit.
- a voltmeter is connected to the pair of voltage electrodes 3. Since the resistance value of the chip resistor A3 is known, the voltage drop in the resistor 1 of the chip resistor A3 is measured using the voltmeter. By applying this measured value to the Ohm equation, it is possible to know the value of the current flowing through the resistor 1.
- more than four electrodes may be provided. If the total number of electrodes is increased, for example, it is possible to use only some of them.
- FIG. 9A and 9B show a chip resistor A4 according to a fourth embodiment of the present invention.
- three pairs of electrodes 3a, 3b, 3c are provided on the lower surface of the resistor 1.
- the first pair of electrodes 3a are separated from each other by a distance s3.
- the second pair of electrodes 3b are separated from each other by a distance s4, and the third pair of electrodes 3c are separated from each other by a distance s5.
- s 3> s 4> S 5 is set, but the present invention is not limited to this.
- the right electrodes 3a to 3c are arranged along the right end of the resistor 1, but may be arranged differently.
- the above-described chip resistors A3 and A4 can be manufactured in the same manner as the chip resistor A1 of the first embodiment.
- the insulating layer 2A ' which forms the basis of the insulating layer 2A, is patterned by thick film printing. For this reason, it is possible to easily cope with different patterns such as the number, shape and arrangement of the electrodes 3.
- FIG. 10 shows a chip resistor A5 according to a fifth embodiment of the present invention.
- This chip resistor A5 is the same as the chip resistor A1 of the first embodiment except that a third insulating layer 2C covering the two opposing side surfaces 10c of the resistor 1 is provided. It has substantially the same configuration. According to such a configuration, it is possible to prevent the molten solder or the like from adhering to the side surface 10c.
- the third insulating layer 2C can be easily provided by forming an insulating layer on the side surface of the bar-shaped resistor material 1A 'shown in FIG. 6A.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/552,301 US20060273423A1 (en) | 2003-04-08 | 2004-04-07 | Chip resistor and method for manufacturing same |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003103843A JP3971335B2 (ja) | 2003-04-08 | 2003-04-08 | チップ抵抗器およびその製造方法 |
| JP2003-103843 | 2003-04-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004090915A1 true WO2004090915A1 (ja) | 2004-10-21 |
Family
ID=33156836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2004/005038 Ceased WO2004090915A1 (ja) | 2003-04-08 | 2004-04-07 | チップ抵抗器およびその製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20060273423A1 (ja) |
| JP (1) | JP3971335B2 (ja) |
| KR (1) | KR100730851B1 (ja) |
| CN (1) | CN100568406C (ja) |
| WO (1) | WO2004090915A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377782A (zh) * | 2012-04-20 | 2013-10-30 | 乾坤科技股份有限公司 | 电阻装置 |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4047760B2 (ja) * | 2003-04-28 | 2008-02-13 | ローム株式会社 | チップ抵抗器およびその製造方法 |
| JP4640952B2 (ja) * | 2005-05-27 | 2011-03-02 | ローム株式会社 | チップ抵抗器およびその製造方法 |
| WO2009028215A1 (ja) * | 2007-08-30 | 2009-03-05 | Kamaya Electric Co., Ltd. | 金属板チップ抵抗器の製造方法及び製造装置 |
| JP4537465B2 (ja) * | 2008-02-18 | 2010-09-01 | 釜屋電機株式会社 | 抵抗金属板低抵抗チップ抵抗器の製造方法 |
| CN102379012B (zh) * | 2009-04-01 | 2014-05-07 | 釜屋电机株式会社 | 电流检测用金属板电阻器及其制造方法 |
| US9305687B2 (en) | 2010-05-13 | 2016-04-05 | Cyntec Co., Ltd. | Current sensing resistor |
| JP2013055130A (ja) * | 2011-09-01 | 2013-03-21 | Rohm Co Ltd | ジャンパー抵抗器 |
| CN104376938B (zh) * | 2013-08-13 | 2018-03-13 | 乾坤科技股份有限公司 | 电阻装置 |
| US10312317B2 (en) | 2017-04-27 | 2019-06-04 | Samsung Electro-Mechanics Co., Ltd. | Chip resistor and chip resistor assembly |
| CN110520942B (zh) | 2017-05-23 | 2021-08-10 | 松下知识产权经营株式会社 | 金属板电阻器及其制造方法 |
| JPWO2019017237A1 (ja) * | 2017-07-19 | 2020-05-28 | パナソニックIpマネジメント株式会社 | チップ抵抗器 |
| CN110114843B (zh) | 2017-12-01 | 2021-07-23 | 松下知识产权经营株式会社 | 金属板电阻器及其制造方法 |
| JP7270386B2 (ja) * | 2018-01-11 | 2023-05-10 | 北陸電気工業株式会社 | チップ状金属抵抗器及びその製造方法 |
| JP7703972B2 (ja) * | 2021-09-22 | 2025-07-08 | 株式会社大真空 | 温度センサ付き水晶振動デバイス |
| CN114388208B (zh) * | 2022-01-28 | 2023-12-15 | 株洲中车奇宏散热技术有限公司 | 一种蛇形电阻弯制方法及撬棒电阻 |
| US12068092B2 (en) * | 2022-04-08 | 2024-08-20 | Cyntec Co., Ltd. | Structure of resistor device and system for measuring resistance of same |
| DE102022113553A1 (de) * | 2022-05-30 | 2023-11-30 | Isabellenhütte Heusler Gmbh & Co. Kg | Herstellungsverfahren für einen elektrischen Widerstand |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS4727876Y1 (ja) * | 1969-10-11 | 1972-08-24 | ||
| JPH0864401A (ja) * | 1994-08-26 | 1996-03-08 | Rohm Co Ltd | チップ状電子部品 |
| JPH08236324A (ja) * | 1994-12-07 | 1996-09-13 | Dale Electronics Inc | 表面取付けレジスターおよびその製造方法 |
| JP2001118701A (ja) * | 1999-10-19 | 2001-04-27 | Koa Corp | 電流検出用低抵抗器及びその製造方法 |
| JP2002057009A (ja) * | 2000-08-07 | 2002-02-22 | Koa Corp | 抵抗器の製造方法および抵抗器 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4706060A (en) * | 1986-09-26 | 1987-11-10 | General Electric Company | Surface mount varistor |
| KR0130869B1 (ko) * | 1994-06-02 | 1998-05-15 | 김정덕 | 칲 저항기의 외부 전극 제조 방법 |
| KR980005074A (ko) * | 1996-06-10 | 1998-03-30 | 이형도 | 다면형 칩 저항기 |
| TW424245B (en) * | 1998-01-08 | 2001-03-01 | Matsushita Electric Industrial Co Ltd | Resistor and its manufacturing method |
-
2003
- 2003-04-08 JP JP2003103843A patent/JP3971335B2/ja not_active Expired - Lifetime
-
2004
- 2004-04-07 WO PCT/JP2004/005038 patent/WO2004090915A1/ja not_active Ceased
- 2004-04-07 US US10/552,301 patent/US20060273423A1/en not_active Abandoned
- 2004-04-07 CN CNB2004800093049A patent/CN100568406C/zh not_active Expired - Lifetime
- 2004-04-07 KR KR1020057018907A patent/KR100730851B1/ko not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4727876Y1 (ja) * | 1969-10-11 | 1972-08-24 | ||
| JPH0864401A (ja) * | 1994-08-26 | 1996-03-08 | Rohm Co Ltd | チップ状電子部品 |
| JPH08236324A (ja) * | 1994-12-07 | 1996-09-13 | Dale Electronics Inc | 表面取付けレジスターおよびその製造方法 |
| JP2001118701A (ja) * | 1999-10-19 | 2001-04-27 | Koa Corp | 電流検出用低抵抗器及びその製造方法 |
| JP2002057009A (ja) * | 2000-08-07 | 2002-02-22 | Koa Corp | 抵抗器の製造方法および抵抗器 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377782A (zh) * | 2012-04-20 | 2013-10-30 | 乾坤科技股份有限公司 | 电阻装置 |
| CN103377782B (zh) * | 2012-04-20 | 2016-04-06 | 乾坤科技股份有限公司 | 电阻装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100730851B1 (ko) | 2007-06-20 |
| JP2004311747A (ja) | 2004-11-04 |
| CN1771568A (zh) | 2006-05-10 |
| CN100568406C (zh) | 2009-12-09 |
| KR20050120703A (ko) | 2005-12-22 |
| US20060273423A1 (en) | 2006-12-07 |
| JP3971335B2 (ja) | 2007-09-05 |
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