WO2004066150A1 - 割り込み制御方法および割り込み制御装置 - Google Patents
割り込み制御方法および割り込み制御装置 Download PDFInfo
- Publication number
- WO2004066150A1 WO2004066150A1 PCT/JP2003/000670 JP0300670W WO2004066150A1 WO 2004066150 A1 WO2004066150 A1 WO 2004066150A1 JP 0300670 W JP0300670 W JP 0300670W WO 2004066150 A1 WO2004066150 A1 WO 2004066150A1
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- WIPO (PCT)
- Prior art keywords
- interrupt
- disable
- register
- controller
- control device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 26
- 230000008569 process Effects 0.000 claims description 9
- 230000005764 inhibitory process Effects 0.000 claims 3
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010411 cooking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B37/00—Nuts or like thread-engaging members
- F16B37/04—Devices for fastening nuts to surfaces, e.g. sheets, plates
- F16B37/06—Devices for fastening nuts to surfaces, e.g. sheets, plates by means of welding or riveting
- F16B37/062—Devices for fastening nuts to surfaces, e.g. sheets, plates by means of welding or riveting by means of riveting
- F16B37/065—Devices for fastening nuts to surfaces, e.g. sheets, plates by means of welding or riveting by means of riveting by deforming the material of the nut
Definitions
- the present invention relates to an interrupt control method and an interrupt control device for executing a predetermined interrupt process by one interrupt controller to which an interrupt signal from another device is input among a plurality of interrupt controllers.
- one interrupt factor (macro) is assigned to one interrupt number, or more specifically, an interrupt controller that performs the process specified by that number.
- an interrupt controller that performs the process specified by that number.
- An object of the present invention is to provide an interrupt control method and an interrupt control device capable of performing various interrupt controls required by a user while suppressing a circuit scale, in order to solve the above-described problem of the conventional technology. And Disclosure of the invention
- an interrupt control method or an interrupt control device includes a plurality of interrupt controllers.
- Interrupt control method for executing interrupt processing Z interrupt control device, wherein an interrupt number is set for each of the other devices, and based on the set interrupt number.
- One of the plurality of interrupt controllers is determined.
- the interrupt number may be set in a register for each of the other devices.
- the interrupt controller that inputs the interrupt signal may be determined from some of the plurality of interrupt controllers.
- an interrupt disabling number for disabling the interrupt of the other device may be set, and the other device on which the interrupt disabling number has been set may be notified that the interrupt has been disabled. Good.
- the interrupt disable number may be set in a register for each of the other devices.
- a user who incorporates the system LSI according to the present invention into various devices such as home appliances can determine which interrupt to use simply by changing the interrupt number or interrupt disable number set in the register for each interrupt factor. And the processing when an interrupt occurs can be arbitrarily switched.
- FIG. 1 shows, among various devices into which the interrupt control device according to the first embodiment of the present invention is incorporated, a combination of interrupt factors in a device A, an interrupt number and an interrupt condition assigned to each interrupt factor
- FIG. 2 is an explanatory diagram schematically showing a hardware configuration of the interrupt control device according to the first embodiment of the present invention
- FIG. 3 is a diagram showing an embodiment of the present invention.
- FIG. 4 is a flowchart showing a procedure of an interrupt control process in the interrupt control device according to the first embodiment.
- FIG. 4 is a description schematically showing a hardware configuration of the interrupt control device according to the second embodiment of the present invention.
- FIG. 1 shows, among various devices into which the interrupt control device according to the first embodiment of the present invention is incorporated, a combination of interrupt factors in a device A, an interrupt number and an interrupt condition assigned to each interrupt factor
- FIG. 2 is an explanatory diagram schematically showing a hardware configuration of the interrupt control device according to the first embodiment of the present invention
- FIG. 3 is
- FIG. 5 is a diagram showing a list of interrupt numbers that can be set in each of the interrupt number setting circuits 402 a to 400 21 according to the second embodiment of the present invention.
- FIG. 6 is an explanatory diagram schematically showing a hardware configuration of an interrupt control device according to a third embodiment of the present invention.
- FIG. 7 is an interrupt control device according to the related art. Description that schematically shows the hardware configuration of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram of an interrupt control device of a certain device A among various devices into which an interrupt control device according to the first embodiment of the present invention (specifically, a system LSI built into various devices such as home appliances) is incorporated.
- FIG. 9 is an explanatory diagram showing a relationship between a combination, an interrupt number assigned to each interrupt factor, and an interrupt condition. As shown in Fig. 1, device A does not assume seven interrupt factors 1, 4, 6, 7, 8, 13 and 15, and each factor has an interrupt number 15, 16, 17 , 18, 19, 20, 21 are assigned. Note that device B, which is different from device A, differs from Fig. 1 in the combination of interrupt factors and the priority of interrupts between factors.
- FIG. 2 is an explanatory diagram schematically showing a hardware configuration of the interrupt control device according to the first embodiment of the present invention.
- FIG. 2 shows only those parts related to the present invention among various circuits on the system LSI which is the interrupt control device according to the present invention.
- reference numeral 200 denotes a CPU, which sets an interrupt number in each register of an interrupt number setting circuit 202 a to 202 p, which will be described later, and sets an interrupt level and an interrupt destination address to interrupt controllers 204 a to 204 g, which will be described later. Set various information required for interrupt processing.
- 201a to 201p are interrupt factors, specifically, a MAC port for executing a specific process.
- a predetermined interrupt signal interrupt occurrence flag
- 202a to 202p are interrupt number setting circuits.
- the number of interrupt factors here, for example, only 16, is prepared, and each is associated with one interrupt factor. For example, taking the interrupt number setting circuit 202a as an example, this circuit is physically connected to interrupt source 1, and when an interrupt occurs in the macro, an interrupt signal indicating that fact is input. .
- the interrupt number setting circuit 202a specifically includes a register 202a_1 and a decoder 202a-12, and the register 202a_1 includes an interrupt assigned in advance to the interrupt factor 1 by the CPU 200.
- the interrupt number 15 is set.
- the decoder 202a-2 is a circuit that outputs a signal to any one of a plurality of bus lines according to the contents held in the register 202a-1.
- Reference numeral 203 denotes a controller determination circuit, which comprises seven OR circuits 203a to 203g in the example of FIG. 2 for the number of interrupt numbers.
- the controller determining circuit 203 converts the signals output from the decoders 202a-2 to 202p-2 of the interrupt number setting circuits 202a to 202p by OR circuits 203a to 203g into interrupt controllers 204a to 204 described later. It is a circuit to assign to any of g.
- Reference numeral 204 denotes an interrupt controller, which is composed of seven interrupt controllers 204a to 204g in the example of FIG. 2 for the number of interrupts. In the following description, unless otherwise specified, 204 a to 204 g and their aggregate 204 are also called “interrupt controllers”.
- FIG. 3 is a flowchart illustrating a procedure of an interrupt control process in the interrupt control device according to the first embodiment of the present invention.
- the CPU 200 executing the predetermined program for setting the interrupt information sends, to each of the interrupt controllers 204 a to 204 g, the conditions of the interrupt specified by the interrupt numbers 15 to 21 (interrupt level, interrupt destination address, (Such as an interrupt level mask value) (step S301).
- the CPU 200 sets the interrupt numbers assigned to the corresponding interrupt factors 201a to 201p in the registers 202a-1 to 202p-1 of the interrupt number setting circuits 202a to 202p (step S 302).
- the register 202a-1 is set with the interrupt number 15 assigned to the interrupt factor 201a, and the register 202b-1 is set with a predetermined value indicating that no interrupt number is assigned. Note that the order of step S301 and step S302 may be reversed.
- step S303: Yes the interrupt 202 set in the interrupt number setting circuit 202a that receives the interrupt signal is sent from the register 202a-1.
- the number is read out to the decoder 202a-2 (step S304).
- the above number is decoded by the decoder 202a-2, that is, a signal is output to one of the bus lines from the decoder 202a-2 (step S305), and the OR circuit to which this signal is input is output.
- the output being 1 only in the OR circuit 203 a among 203 a to 203 g, an interrupt signal is input to the interrupt controller 204 a connected to the circuit (step S 306).
- the interrupt controller 204a executes the program of the interrupt address according to the priority set therein and the like (step S307).
- the process returns to step S303 to execute a new interrupt. Wait state.
- the combination of interrupts, the interrupt number corresponding to each interrupt, and the interrupt condition change depending on which register of the interrupt number setting circuits 202a to 202 is set to which interrupt number. It can be done. Therefore, the same interrupt control device can be directly connected to various devices only by changing the setting of the interrupt number or the like in terms of hardware. Also, since there is no needless mounting of a controller for interrupts that are not used at the embedded destination, the circuit scale can be reduced and power consumption can be reduced. You.
- the number of outputs from each of the decoders 202 a_2 to 202 p-2 of the interrupt number setting circuits 202 a to 202 p, and the OR circuit 203 in the controller determination circuit 203 The number of inputs to a to 203 must be the same as the number of interrupt factors 201 a to 201 p (16 in the above example).
- the circuits from the interrupt number setting circuits 202a to 202p to the interrupt controllers 204a to 204g become complicated and large-scale. There was a problem that would. Therefore, the circuit may be simplified by providing a certain restriction on the setting of the interrupt number as in Embodiment 2 described below.
- FIG. 4 is an explanatory diagram schematically showing a hardware configuration of the interrupt control device according to the second embodiment of the present invention.
- the number of interrupt sources is 12 (16 in the first embodiment), and three interrupt numbers are assigned to them (seven in the first embodiment). Shall be.
- the interrupt number setting circuits 202a to 202p are connected to the seven OR circuits 203a to 203g, respectively.
- ⁇ 4021 are only connected to two OR circuits each.
- the signal output from the interrupt number setting circuit 402a corresponding to the interrupt cause 401a is not input to the 403a and 403b of the OR circuits 403a to 403f in the preceding stage. Further, since the above signal is input to only 404a or 404 of the three interrupt controllers via the subsequent OR circuits 403g and 403h, the 0th one of the three interrupt processes prepared in advance is used. Processing and the first processing and the power can not be activated.
- interrupt number setting circuit 402a In other words, "00" is stored in the register in the interrupt number setting circuit 402a. Indicates that even if an interrupt number other than “01” is set, the wiring cannot be executed due to hardware. Conversely, the interrupt numbers that can be set in the interrupt number setting circuit 402 a are limited to either “0 0” or “01”.
- FIG. 5 is a list of interrupt numbers that can be set for each of the interrupt number setting circuits 402 a to 420 1 according to the second embodiment. As shown in Fig. 5, each circuit has a limit on the interrupt number that can be set. For example, it is not possible to set the interrupt number "0 2" in the interrupt number setting circuit 402a.
- the wiring in the controller determination circuit 403 can be greatly simplified in exchange for this. This effect increases as the number of interrupt sources increases.
- the first and second embodiments are examples in which interrupts from various macros connected to the interrupt control device are permitted.However, in some cases, conversely, it is desired to prohibit interrupts from a specific macro port. is there.
- FIG. 6 is an explanatory diagram schematically showing the hardware configuration of the interrupt control device according to the third embodiment, focusing on this difference.
- one signal line output from the decoder 602 b in the interrupt number setting circuit 602 is connected to the interrupt disable register 601 a in the interrupt source 601.
- the CPU 600 sets a predetermined value (interruption prohibition number) indicating that the interrupt is disabled in the register 62a, the value is decoded. The value becomes 1 on the output line of the decoder 602 b, and this signal is input to the interrupt disable register 601 a.
- An interrupt disable flag is set in the interrupt disable register 601a that receives this signal, and the interrupt factor 601 does not output an interrupt signal as long as the above flag is set.
- the CPU 6000 rewrites the register 602a to set the interrupt number instead of the interrupt disable number, the disable flag of the interrupt disable register 601a is also released.
- interrupt prohibition was implemented by setting the interrupt level to 0, so the interrupt signal itself was transmitted from the interrupt source to the interrupt controller. Since it is not generated, the circuit is not occupied by interrupts that are prohibited anyway, and processing is efficient.
- a user who incorporates the system LSI according to the present invention into various devices simply changes the interrupt number or the interrupt disable number set in the register for each interrupt factor. Since the ability to use interrupts and the processing when an interrupt occurs can be switched arbitrarily, an interrupt control method that can perform the various interrupt controls required by the user while suppressing the circuit size And it is suitable for interrupt control devices, especially for system LSIs with excellent versatility and cost performance.
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Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004567141A JPWO2004066150A1 (ja) | 2003-01-24 | 2003-01-24 | 割り込み制御方法および割り込み制御装置 |
PCT/JP2003/000670 WO2004066150A1 (ja) | 2003-01-24 | 2003-01-24 | 割り込み制御方法および割り込み制御装置 |
EP03701871A EP1562116A1 (en) | 2003-01-24 | 2003-01-24 | Interrupt control method and interrupt control device |
CNB038240785A CN100336022C (zh) | 2003-01-24 | 2003-01-24 | 中断控制方法和中断控制装置 |
AU2003203386A AU2003203386A1 (en) | 2003-01-24 | 2003-01-24 | Interrupt control method and interrupt control device |
US11/084,010 US20050165990A1 (en) | 2003-01-24 | 2005-03-21 | Interrupt control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/000670 WO2004066150A1 (ja) | 2003-01-24 | 2003-01-24 | 割り込み制御方法および割り込み制御装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/084,010 Continuation US20050165990A1 (en) | 2003-01-24 | 2005-03-21 | Interrupt control device |
Publications (1)
Publication Number | Publication Date |
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WO2004066150A1 true WO2004066150A1 (ja) | 2004-08-05 |
Family
ID=32750595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/000670 WO2004066150A1 (ja) | 2003-01-24 | 2003-01-24 | 割り込み制御方法および割り込み制御装置 |
Country Status (5)
Country | Link |
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EP (1) | EP1562116A1 (ja) |
JP (1) | JPWO2004066150A1 (ja) |
CN (1) | CN100336022C (ja) |
AU (1) | AU2003203386A1 (ja) |
WO (1) | WO2004066150A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100458708C (zh) * | 2005-07-05 | 2009-02-04 | 英业达股份有限公司 | 中断控制系统及方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100397375C (zh) * | 2005-12-02 | 2008-06-25 | 北京中星微电子有限公司 | 多中断处理单元的中断处理的装置和方法 |
US8291202B2 (en) * | 2008-08-08 | 2012-10-16 | Qualcomm Incorporated | Apparatus and methods for speculative interrupt vector prefetching |
JP6266239B2 (ja) * | 2013-07-11 | 2018-01-24 | ルネサスエレクトロニクス株式会社 | マイクロコンピュータ |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01113834A (ja) * | 1987-10-28 | 1989-05-02 | Hitachi Ltd | データ処理装置 |
JPH0367338A (ja) * | 1989-08-05 | 1991-03-22 | Mitsubishi Electric Corp | 割り込み制御回路 |
JPH04309134A (ja) * | 1991-04-08 | 1992-10-30 | Nec Corp | 割り込み制御回路 |
US5161228A (en) * | 1988-03-02 | 1992-11-03 | Ricoh Company, Ltd. | System with selectively exclusionary enablement for plural indirect address type interrupt control circuit |
JPH08221351A (ja) * | 1995-02-15 | 1996-08-30 | Fuji Facom Corp | 割込み番号の設定処理方式 |
JPH11149382A (ja) * | 1997-11-19 | 1999-06-02 | Nec Eng Ltd | 情報処理装置及びマイクロプロセッサの割込み制御装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1113834A (ja) * | 1997-06-26 | 1999-01-22 | Rinrin Japan:Kk | ホイールバランスウエイト |
US6219743B1 (en) * | 1998-09-30 | 2001-04-17 | International Business Machines Corporation | Apparatus for dynamic resource mapping for isolating interrupt sources and method therefor |
-
2003
- 2003-01-24 EP EP03701871A patent/EP1562116A1/en not_active Withdrawn
- 2003-01-24 AU AU2003203386A patent/AU2003203386A1/en not_active Abandoned
- 2003-01-24 CN CNB038240785A patent/CN100336022C/zh not_active Expired - Fee Related
- 2003-01-24 WO PCT/JP2003/000670 patent/WO2004066150A1/ja active Application Filing
- 2003-01-24 JP JP2004567141A patent/JPWO2004066150A1/ja not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01113834A (ja) * | 1987-10-28 | 1989-05-02 | Hitachi Ltd | データ処理装置 |
US5161228A (en) * | 1988-03-02 | 1992-11-03 | Ricoh Company, Ltd. | System with selectively exclusionary enablement for plural indirect address type interrupt control circuit |
JPH0367338A (ja) * | 1989-08-05 | 1991-03-22 | Mitsubishi Electric Corp | 割り込み制御回路 |
JPH04309134A (ja) * | 1991-04-08 | 1992-10-30 | Nec Corp | 割り込み制御回路 |
JPH08221351A (ja) * | 1995-02-15 | 1996-08-30 | Fuji Facom Corp | 割込み番号の設定処理方式 |
JPH11149382A (ja) * | 1997-11-19 | 1999-06-02 | Nec Eng Ltd | 情報処理装置及びマイクロプロセッサの割込み制御装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100458708C (zh) * | 2005-07-05 | 2009-02-04 | 英业达股份有限公司 | 中断控制系统及方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1562116A1 (en) | 2005-08-10 |
CN1688975A (zh) | 2005-10-26 |
AU2003203386A1 (en) | 2004-08-13 |
JPWO2004066150A1 (ja) | 2006-05-18 |
CN100336022C (zh) | 2007-09-05 |
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