WO2004053961A1 - Procede de fabrication d'une structure multicouche - Google Patents

Procede de fabrication d'une structure multicouche Download PDF

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Publication number
WO2004053961A1
WO2004053961A1 PCT/IB2003/006397 IB0306397W WO2004053961A1 WO 2004053961 A1 WO2004053961 A1 WO 2004053961A1 IB 0306397 W IB0306397 W IB 0306397W WO 2004053961 A1 WO2004053961 A1 WO 2004053961A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
level
sige
support substrate
implantation
Prior art date
Application number
PCT/IB2003/006397
Other languages
English (en)
Inventor
Carlos Mazure
Original Assignee
S.O.I.Tec Silicon On Insulator Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to EP03789590A priority Critical patent/EP1568073A1/fr
Priority to AU2003294170A priority patent/AU2003294170A1/en
Priority to JP2004558309A priority patent/JP4762547B2/ja
Publication of WO2004053961A1 publication Critical patent/WO2004053961A1/fr
Priority to US11/106,135 priority patent/US7510949B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the target substrate 20 can be made of silicon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de production d'une structure multicouche fabriquée à partir de matériaux à semiconducteur, cette structure comprenant un substrat (20) fabriqué à partir d'un premier matériau à semiconducteur et d'une couche mince superficielle fabriquée à partir d'un second matériau à semiconducteur. Ces deux matériaux à semiconducteur comportent des paramètres de réseau différents, caractérisés en ce que le procédé comprend les étape consistant : à produire une couche (110) comprenant une couche mince superficielle sur un substrat support (100), à créer une zone de fragilisation dans l'ensemble (10) formée par le substrat support et la couche déposée, à lier cet ensemble à un substrat cible (20), à le détacher au niveau de la zone de fragilisation, et à traiter la surface de la structure obtenue.
PCT/IB2003/006397 2002-07-09 2003-12-05 Procede de fabrication d'une structure multicouche WO2004053961A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03789590A EP1568073A1 (fr) 2002-12-06 2003-12-05 Procede de fabrication d'une structure multicouche
AU2003294170A AU2003294170A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
JP2004558309A JP4762547B2 (ja) 2002-12-06 2003-12-05 多層構造の製造方法
US11/106,135 US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0215499A FR2848334A1 (fr) 2002-12-06 2002-12-06 Procede de fabrication d'une structure multicouche
FR02/15499 2002-12-06

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/615,259 Continuation-In-Part US6953736B2 (en) 2002-07-09 2003-07-09 Process for transferring a layer of strained semiconductor material

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/106,135 Continuation US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Publications (1)

Publication Number Publication Date
WO2004053961A1 true WO2004053961A1 (fr) 2004-06-24

Family

ID=32320086

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/006397 WO2004053961A1 (fr) 2002-07-09 2003-12-05 Procede de fabrication d'une structure multicouche

Country Status (8)

Country Link
EP (1) EP1568073A1 (fr)
JP (1) JP4762547B2 (fr)
KR (1) KR100797210B1 (fr)
CN (1) CN1720605A (fr)
AU (1) AU2003294170A1 (fr)
FR (1) FR2848334A1 (fr)
TW (1) TWI289880B (fr)
WO (1) WO2004053961A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140453A (ja) * 2004-11-10 2006-06-01 Sharp Corp 直接ウェハ結合による低欠陥のゲルマニウム膜の製造
US9097987B2 (en) 2002-11-12 2015-08-04 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101960604B (zh) * 2008-03-13 2013-07-10 S.O.I.Tec绝缘体上硅技术公司 绝缘隐埋层中有带电区的衬底
CN105023991B (zh) * 2014-04-30 2018-02-23 环视先进数字显示无锡有限公司 一种基于无机物的led积层电路板的制造方法
CN108231695A (zh) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 复合衬底及其制造方法
CN107195534B (zh) * 2017-05-24 2021-04-13 中国科学院上海微系统与信息技术研究所 Ge复合衬底、衬底外延结构及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (fr) * 1998-09-10 2000-03-23 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin, et produits obtenus
EP1050901A2 (fr) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Procédé de séparation d'un elément composé et procédé pour la fabrication d'un film mince
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (fr) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
WO2002071491A1 (fr) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication
WO2003017358A1 (fr) * 2001-08-17 2003-02-27 Rosemount Aerospace, Inc. Procede de fabrication d'une structure semi-conductrice contenant du sic sur une couche d'oxyde

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
JP2003249641A (ja) * 2002-02-22 2003-09-05 Sharp Corp 半導体基板、その製造方法及び半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (fr) * 1998-09-10 2000-03-23 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin, et produits obtenus
EP1050901A2 (fr) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Procédé de séparation d'un elément composé et procédé pour la fabrication d'un film mince
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (fr) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle
WO2002071491A1 (fr) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication
WO2003017358A1 (fr) * 2001-08-17 2003-02-27 Rosemount Aerospace, Inc. Procede de fabrication d'une structure semi-conductrice contenant du sic sur une couche d'oxyde

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TARASCHI GIANNI, LANGDO THOMAS A. ET AL.: "Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY - B, vol. 20, no. 2, March 2002 (2002-03-01), pages 725 - 727, XP002259419 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9097987B2 (en) 2002-11-12 2015-08-04 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
JP2006140453A (ja) * 2004-11-10 2006-06-01 Sharp Corp 直接ウェハ結合による低欠陥のゲルマニウム膜の製造
JP4651099B2 (ja) * 2004-11-10 2011-03-16 シャープ株式会社 直接ウェハ結合による低欠陥のゲルマニウム膜の製造

Also Published As

Publication number Publication date
FR2848334A1 (fr) 2004-06-11
TWI289880B (en) 2007-11-11
AU2003294170A1 (en) 2004-06-30
KR20050084146A (ko) 2005-08-26
KR100797210B1 (ko) 2008-01-22
TW200511393A (en) 2005-03-16
EP1568073A1 (fr) 2005-08-31
JP2006509361A (ja) 2006-03-16
CN1720605A (zh) 2006-01-11
JP4762547B2 (ja) 2011-08-31

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