TW200511393A - Manufacturing process for a multilayer structure - Google Patents
Manufacturing process for a multilayer structureInfo
- Publication number
- TW200511393A TW200511393A TW092134368A TW92134368A TW200511393A TW 200511393 A TW200511393 A TW 200511393A TW 092134368 A TW092134368 A TW 092134368A TW 92134368 A TW92134368 A TW 92134368A TW 200511393 A TW200511393 A TW 200511393A
- Authority
- TW
- Taiwan
- Prior art keywords
- multilayer structure
- substrate
- ensemble
- manufacturing process
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present invention relates to a production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate (20) made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps: producing a layer (110) comprising said superficial thin layer on a support substrate (100), creating an embrittlement zone in the ensemble (10) formed by said support substrate and said deposited layer, bonding said ensemble with a target substrate (20), detaching at the level of this embrittlement zone, treating the surface of the resulting structure.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0215499A FR2848334A1 (en) | 2002-12-06 | 2002-12-06 | Multi-layer structure production of semiconductor materials with different mesh parameters comprises epitaxy of thin film on support substrate and adhesion on target substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200511393A true TW200511393A (en) | 2005-03-16 |
TWI289880B TWI289880B (en) | 2007-11-11 |
Family
ID=32320086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092134368A TWI289880B (en) | 2002-12-06 | 2003-12-05 | Manufacturing process for a multilayer structure |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP1568073A1 (en) |
JP (1) | JP4762547B2 (en) |
KR (1) | KR100797210B1 (en) |
CN (1) | CN1720605A (en) |
AU (1) | AU2003294170A1 (en) |
FR (1) | FR2848334A1 (en) |
TW (1) | TWI289880B (en) |
WO (1) | WO2004053961A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7110081B2 (en) | 2002-11-12 | 2006-09-19 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US7247545B2 (en) * | 2004-11-10 | 2007-07-24 | Sharp Laboratories Of America, Inc. | Fabrication of a low defect germanium film by direct wafer bonding |
EP2269226A1 (en) * | 2008-03-13 | 2011-01-05 | S.O.I.Tec Silicon on Insulator Technologies | Substrate having a charged zone in an insulating buried layer |
CN105023991B (en) * | 2014-04-30 | 2018-02-23 | 环视先进数字显示无锡有限公司 | A kind of manufacture method of the LED laminated circuit boards based on inorganic matter |
CN108231695A (en) * | 2016-12-15 | 2018-06-29 | 上海新微技术研发中心有限公司 | Composite substrate and method for manufacturing the same |
CN107195534B (en) * | 2017-05-24 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Ge composite substrate, substrate epitaxial structure and preparation method thereof |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
FR2783254B1 (en) * | 1998-09-10 | 2000-11-10 | France Telecom | METHOD FOR OBTAINING A LAYER OF MONOCRYSTALLINE GERMANIUM ON A MONOCRYSTALLINE SILICON SUBSTRATE, AND PRODUCTS OBTAINED |
JP2001015721A (en) * | 1999-04-30 | 2001-01-19 | Canon Inc | Separation method of composite member and manufacture of thin film |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
JP3607194B2 (en) * | 1999-11-26 | 2005-01-05 | 株式会社東芝 | Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate |
FR2809867B1 (en) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE |
US6573126B2 (en) * | 2000-08-16 | 2003-06-03 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
WO2002071491A1 (en) * | 2001-03-02 | 2002-09-12 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits |
WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
US6566158B2 (en) * | 2001-08-17 | 2003-05-20 | Rosemount Aerospace Inc. | Method of preparing a semiconductor using ion implantation in a SiC layer |
JP2003249641A (en) * | 2002-02-22 | 2003-09-05 | Sharp Corp | Semiconductor substrate, manufacturing method therefor and semiconductor device |
-
2002
- 2002-12-06 FR FR0215499A patent/FR2848334A1/en active Pending
-
2003
- 2003-12-05 KR KR1020057010109A patent/KR100797210B1/en active IP Right Grant
- 2003-12-05 AU AU2003294170A patent/AU2003294170A1/en not_active Abandoned
- 2003-12-05 TW TW092134368A patent/TWI289880B/en not_active IP Right Cessation
- 2003-12-05 WO PCT/IB2003/006397 patent/WO2004053961A1/en active Application Filing
- 2003-12-05 JP JP2004558309A patent/JP4762547B2/en not_active Expired - Lifetime
- 2003-12-05 CN CNA2003801052499A patent/CN1720605A/en active Pending
- 2003-12-05 EP EP03789590A patent/EP1568073A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JP4762547B2 (en) | 2011-08-31 |
EP1568073A1 (en) | 2005-08-31 |
JP2006509361A (en) | 2006-03-16 |
AU2003294170A1 (en) | 2004-06-30 |
FR2848334A1 (en) | 2004-06-11 |
WO2004053961A1 (en) | 2004-06-24 |
KR20050084146A (en) | 2005-08-26 |
TWI289880B (en) | 2007-11-11 |
CN1720605A (en) | 2006-01-11 |
KR100797210B1 (en) | 2008-01-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |