Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/213—Channel regions of field-effect devices
  • H10D62/221—Channel regions of field-effect devices of FETs
  • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
  • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
  • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/62—Electrodes ohmically coupled to a semiconductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
  • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
  • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Definitions

• This invention relates generally to RF power transistors, and more particularly the invention relates to a laterally diffused MOS transistor (LDMOS) and the method of manufacturing same.
• LDMOS laterally diffused MOS transistor
• the LDMOS transistor is used in RF applications as a power amplifier.
• the high frequencies require small dimensions such as gate lengths of less than a micron, thin gate oxide of less than 500 A, a short channel for cut off frequency (F t ) greater than 10 GH 3 , reduced source-drain resistance (Rdson), and a high reverse breakdown voltage through use of a lightly doped drain extension.
• a process flow includes the use of nitride masking of the gate structure for a sidewall spacer formation, and the double use of a source and drain mask for dopant implant and for suicide contact formation.
• either titanium or cobalt can be used for the suicide contacts, thereby eliminating the shrinkage associated with tungsten suicide gate.
• Figs. 1-13 are section views illustrating steps in fabricating an LDMOS transistor in accordance with an embodiment of the invention.
• DETAILED DESCRIPTION OF THE INVENTION [09]
• Figs. 1 - 13 are section views illustrating the fabrication of an LDMOS transistor in accordance with one embodiment of the invention. As shown in Fig. 1, the structure is formed in a silicon substrate 10 which typically comprises an epitaxial layer as the top surface.
• a first mask and etch are employed to form a P+ doped sinker region 12 (which becomes a source conduction region), low pressure chemical vapor deposited (LPCVD) nitride and a thermal pad oxide are formed, and then a second mask and etch are employed to expose the silicon surface and grow field oxide 14.
• LPCVD low pressure chemical vapor deposited
• a second mask and etch are employed to expose the silicon surface and grow field oxide 14.
• a N-type field implant is made in a recessed region and then field oxide 14 is grown. Thereafter the field oxide can be planarized using, for example, chemical mechanical planarization (CMP) which is then followed by a P+ implant 16 which will contact the channel region.
• CMP chemical mechanical planarization
• a silicon nitride layer 22 is formed by low pressure chemical vapor deposition with a thickness of about 1 ,000 A and then a gate photoresist mask 24 is formed over nitride layer 22.
• the exposed nitride 22, polysilicon 20, and oxide 18 are then removed by etching.
• the polysilicon functions as an etch stop when the nitride is etched
• the silicon oxide functions as an etch stop in etching the polysilicon
• the silicon substrate functions as an etch-stop in etching the silicon oxide.
• the gate structure comprising nitride layer 22, polysilicon 20, and gate oxide 18 is masked by photoresist 26, and in Fig. 6 a P- dopant is implanted to form a lightly doped (e.g., 10 atoms/cc) channel region 28.
• Mask 26 is then removed and N-type dopant is implanted to form lightly doped (e.g., 10 17 atoms/cc) drain (LDD) 30 on one side of the gate structure.
• Silicon oxide deposition forms a silicon oxide layer of approximately 2,OO ⁇ A, and then the oxide layer is etched back using preferential etchant thereby leaving sidewall spacers 32 around the gate structure.
• the exposed surface of substrate 10 is then oxidized (seal oxidation) with a thickness of approximately 350 A - 50 ⁇ A. This oxidation will not oxidize the top of the polysilicon gate because of the protective nitride cap 22. Thereafter, nitride cap 22 is removed by a suitable etchant, such as phosphoric acid, with the seal oxide 34 having a remaining thickness of approximately 300 A.
• An N+ source/drain implant mask 36 as shown in Fig. 7 is then employed to implant N-type dopant and forming source region 38 and N+ (e.g., io 19"20 atoms/cc) drain region 40. It will be noted that the source region abuts spacer 32 while the N+ drain region 40 is spaced from spacer 32 by the LDD region 30.
• oxide 34 is removed from over source 38 and N+ drain 40, and then the photoresist 36 is stripped. Titanium or cobalt is then sputtered over the surface in contact with P+ (e.g., greater than 10 19 atoms/cc) region 16 and source region 38 and also in contact with N+ (e.g., greater than 10 19 atoms/cc) drain region 40 as shown in Fig. 8.
• P+ e.g., greater than 10 19 atoms/cc
• N+ e.g., greater than 10 19 atoms/cc
• an interlayer dielectric 50 (PECVD) is deposited over the surface of the structure, and after a contact mask and etch through dielectric 50, a barrier metal is deposited. Chemical vapor deposited tungsten or tungsten compound plugs 52 contacting silicide contacts 42, 44, and 46 to the source, drain, and gate, respectively, are then formed.
• a first metal layer is sputtered on interlayer dielectric 50 and selectively etched to form contacts 54, and thereafter a second dielectric layer 58 is deposited over metal contacts 54 and the first interlayer dielectric 50.
• a via mask and etch is employed to expose the contacts 54 and a seed/glue metal layer 60 is formed over the surface of the second inter dielectric layer 58 and extends to contacts 54.
• a second metal layer 62 is then formed over the seed metal 60 for interconnect lines as shown in Fig. 12.
• An LDMOS transistor fabricating in accordance with the invention can have a gate length of 0.5 - 0.6 ⁇ , with a gate oxide thickness of 350 A-450 A. The transistor has superior linearity due to reduced drain-source on resistance, and a higher Ft is realized due to the shorter channel length. A higher transconductance (Gm) is provided by the reduced gate oxide thickness, shorter gate, and reduced Rdson.
• Gm transconductance

Landscapes

• Insulated Gate Type Field-Effect Transistor (AREA)

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Publications (2)

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• 2002
  • 2002-11-21 US US10/302,639 patent/US6727127B1/en not_active Expired - Lifetime
• 2003
  • 2003-11-19 JP JP2004555528A patent/JP2006516176A/ja active Pending
  • 2003-11-19 AU AU2003299562A patent/AU2003299562A1/en not_active Abandoned
  • 2003-11-19 WO PCT/US2003/037210 patent/WO2004049399A2/en not_active Ceased
  • 2003-11-20 TW TW092132617A patent/TWI325154B/zh not_active IP Right Cessation

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