AU2003299562A1 - Laterally difussed mos transistor (ldmos) and method of making same - Google Patents

Laterally difussed mos transistor (ldmos) and method of making same

Info

Publication number
AU2003299562A1
AU2003299562A1 AU2003299562A AU2003299562A AU2003299562A1 AU 2003299562 A1 AU2003299562 A1 AU 2003299562A1 AU 2003299562 A AU2003299562 A AU 2003299562A AU 2003299562 A AU2003299562 A AU 2003299562A AU 2003299562 A1 AU2003299562 A1 AU 2003299562A1
Authority
AU
Australia
Prior art keywords
difussed
ldmos
laterally
mos transistor
making same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003299562A
Other languages
English (en)
Other versions
AU2003299562A8 (en
Inventor
Johan Darmawan
John Mason
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cree Microwave LLC
Original Assignee
Cree Microwave LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Microwave LLC filed Critical Cree Microwave LLC
Publication of AU2003299562A1 publication Critical patent/AU2003299562A1/en
Publication of AU2003299562A8 publication Critical patent/AU2003299562A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
AU2003299562A 2002-11-21 2003-11-19 Laterally difussed mos transistor (ldmos) and method of making same Abandoned AU2003299562A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/302,639 US6727127B1 (en) 2002-11-21 2002-11-21 Laterally diffused MOS transistor (LDMOS) and method of making same
US10/302,639 2002-11-21
PCT/US2003/037210 WO2004049399A2 (en) 2002-11-21 2003-11-19 Laterally difussed mos transistor (ldmos) and method of making same

Publications (2)

Publication Number Publication Date
AU2003299562A1 true AU2003299562A1 (en) 2004-06-18
AU2003299562A8 AU2003299562A8 (en) 2004-06-18

Family

ID=32107689

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003299562A Abandoned AU2003299562A1 (en) 2002-11-21 2003-11-19 Laterally difussed mos transistor (ldmos) and method of making same

Country Status (5)

Country Link
US (1) US6727127B1 (enExample)
JP (1) JP2006516176A (enExample)
AU (1) AU2003299562A1 (enExample)
TW (1) TWI325154B (enExample)
WO (1) WO2004049399A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3981028B2 (ja) * 2002-09-11 2007-09-26 株式会社東芝 半導体装置
JP2006245391A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 半導体装置
SG130099A1 (en) * 2005-08-12 2007-03-20 Ciclon Semiconductor Device Co Power ldmos transistor
JP4907920B2 (ja) * 2005-08-18 2012-04-04 株式会社東芝 半導体装置及びその製造方法
US7554154B2 (en) * 2006-07-28 2009-06-30 Alpha Omega Semiconductor, Ltd. Bottom source LDMOSFET structure and method
US8076734B2 (en) * 2007-11-29 2011-12-13 International Business Machines Corporation Semiconductor structure including self-aligned deposited gate dielectric
KR101578931B1 (ko) * 2008-12-05 2015-12-21 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조 방법
CN103794593A (zh) * 2012-10-30 2014-05-14 上海华虹宏力半导体制造有限公司 功率mos晶体管阵列
US8981475B2 (en) 2013-06-18 2015-03-17 International Business Machines Corporation Lateral diffusion metal oxide semiconductor (LDMOS)
RU2535283C1 (ru) * 2013-06-26 2014-12-10 Открытое акционерное общество "Научно-производственное предприятие "Пульсар" Способ изготовления мощных кремниевых свч ldmos транзисторов
US20150035067A1 (en) * 2013-08-05 2015-02-05 Globalfoundries Singapore Pte. Ltd. Low rdson device and method of manufacturing the same
CN103871898B (zh) * 2014-02-21 2016-08-17 上海华力微电子有限公司 一种高压晶体管制备工艺
US9543299B1 (en) * 2015-09-22 2017-01-10 Texas Instruments Incorporated P-N bimodal conduction resurf LDMOS
RU2639579C2 (ru) * 2016-03-31 2017-12-21 Акционерное общество "Научно-производственное предприятие "Пульсар" Способ изготовления мощных кремниевых свч ldmos транзисторов с модернизированным затворным узлом элементарных ячеек
US11430888B2 (en) 2020-07-02 2022-08-30 Micron Technology, Inc. Integrated assemblies having transistors configured for high-voltage applications
US11664443B2 (en) * 2021-05-10 2023-05-30 Nxp Usa, Inc. LDMOS transistor with implant alignment spacers

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722910A (en) * 1986-05-27 1988-02-02 Analog Devices, Inc. Partially self-aligned metal contact process
JPH0766393A (ja) * 1993-08-23 1995-03-10 Nec Kansai Ltd 半導体装置の製造方法
JPH08186256A (ja) * 1994-12-29 1996-07-16 Sony Corp Ｌｄｄ構造のトランジスタの製造方法及びトランジスタ
JP3629326B2 (ja) * 1996-02-20 2005-03-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JPH10116986A (ja) * 1996-08-22 1998-05-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5869875A (en) 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
US6215152B1 (en) * 1998-08-05 2001-04-10 Cree, Inc. MOSFET having self-aligned gate and buried shield and method of making same
US6506648B1 (en) * 1998-09-02 2003-01-14 Cree Microwave, Inc. Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure
JP3255134B2 (ja) * 1999-01-22 2002-02-12 日本電気株式会社 半導体装置の製造方法
US6063704A (en) * 1999-08-02 2000-05-16 National Semiconductor Corporation Process for incorporating silicon oxynitride DARC layer into formation of silicide polysilicon contact
JP2001237415A (ja) * 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法
JP4056195B2 (ja) * 2000-03-30 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
TWI325154B (en) 2010-05-21
WO2004049399A2 (en) 2004-06-10
JP2006516176A (ja) 2006-06-22
AU2003299562A8 (en) 2004-06-18
TW200415713A (en) 2004-08-16
WO2004049399A3 (en) 2006-04-27
US6727127B1 (en) 2004-04-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase