WO2004010505A1 - Plaquette de silicium sur isolant et son procede de production - Google Patents

Plaquette de silicium sur isolant et son procede de production Download PDF

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Publication number
WO2004010505A1
WO2004010505A1 PCT/JP2003/009006 JP0309006W WO2004010505A1 WO 2004010505 A1 WO2004010505 A1 WO 2004010505A1 JP 0309006 W JP0309006 W JP 0309006W WO 2004010505 A1 WO2004010505 A1 WO 2004010505A1
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WO
WIPO (PCT)
Prior art keywords
layer
etch stop
ion implantation
soi
substrate
Prior art date
Application number
PCT/JP2003/009006
Other languages
English (en)
Japanese (ja)
Inventor
Kiyoshi Mitani
Isao Yokokawa
Original Assignee
Shin-Etsu Handotai Co.,Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2002209866A external-priority patent/JP2004055750A/ja
Priority claimed from JP2002209911A external-priority patent/JP4147577B2/ja
Priority claimed from JP2002221724A external-priority patent/JP4147578B2/ja
Application filed by Shin-Etsu Handotai Co.,Ltd. filed Critical Shin-Etsu Handotai Co.,Ltd.
Publication of WO2004010505A1 publication Critical patent/WO2004010505A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers

Definitions

  • the present invention relates to an SOI wafer and a method for manufacturing the same, and more particularly, to an SOI wafer having a plurality of SOI layers having different thicknesses formed on the surface of a silicon oxide film and a method for manufacturing the same.
  • CMOS-ICs and high-withstand-voltage ICs have a silicon oxide film insulator layer formed on a silicon single crystal substrate (hereinafter also referred to as a base wafer), and another silicon A so-called SOI wafer is used in which a single crystal layer is stacked as an SOI (Silicon on Insulator) layer.
  • SOI Silicon on Insulator
  • a typical manufacturing method of SOI wafers is a bonding method.
  • a first silicon single crystal substrate serving as a base wafer and a second silicon single crystal substrate (hereinafter also referred to as a bond wafer) serving as an SOI layer serving as a device forming region are bonded via a silicon oxide film.
  • the bond wafer is reduced to a desired film thickness and thinned to make the bond wafer an SOI layer.
  • the smart cut method (trade name) is known as a simple and easy method to obtain a uniform film thickness. This is, Hydrogen is ion-implanted so that a high-concentration hydrogen layer is formed at a fixed depth position with respect to the bonding surface of the bond wafer (referred to as a first main surface). Is peeled off.
  • the SOI wafer 50 ' (reference numeral 7 is a base wafer and reference numeral 2 is a silicon oxide film) is obtained on the surface of the SOI layer 8 after stripping.
  • a damage layer 8a due to ion implantation is formed, and the roughness of the peeled surface itself is considerably larger than the mirror surface of the Si wafer at the product level.
  • the surface of the SOI layer 8 after peeling has to be flattened by a mirror polishing (commonly called touch polishing, which uses mechanical and chemical polishing) with a small polishing allowance. Has been done.
  • the short-wavelength roughness component of the peeled surface can be removed relatively easily, but non-uniformity in the polishing surface is newly added to the polishing allowance.
  • the distribution of the thickness t of the obtained SOI layer has a standard deviation ⁇ 1 of about 1 to 2 nm in the same wafer.
  • a distribution of about 3 nm or more occurs in the standard deviation ⁇ ⁇ 2 of the film thickness t (t1, t2, t3) between the wafers of the same specification and the u-halotte.
  • a method of flattening the peeled surface by heat treatment in an inert gas atmosphere or a hydrogen atmosphere is also conceivable.However, the surface roughness after peeling has considerable unevenness, and it is easy for partial unevenness to occur. Therefore, heat treatment conditions of more than 1 hour at 1100 ° C or more and more than several hours at 1200 ° C or more are necessary, which is not practical.
  • process control such as hydrogen ion implantation must be strict, leading to a reduction in manufacturing efficiency and yield.
  • the level of non-uniformity of the film thickness as described above reaches 10 to several tens of percent of the target average film thickness, and is directly linked to the quality variation of the semiconductor device using the SOI wafer and the reduction of the manufacturing yield.
  • an SOI layer having an ultrathin film and excellent film thickness uniformity and having a partially different thickness in the plane of the SOI layer cannot be conventionally manufactured. could not.
  • the invention also provides an SOI wafer capable of improving its functional characteristics and a method of manufacturing an SOI wafer capable of suppressing variation in quality and improving manufacturing yield. Disclosure of the invention
  • a method for manufacturing an SOI wafer according to the first aspect of the present invention comprises a first substrate (corresponding to a base wafer) and a second substrate (corresponding to a bond wafer) made of silicon single crystal.
  • an ion implantation layer for an etch stop having a concentration peak at a second depth position shallower than the first depth position in an ion implantation profile in the depth direction is formed.
  • An etch stop layer forming step of forming an etch stop layer having a higher oxygen concentration than the surrounding portion in the combined silicon single crystal thin film based on the ion implantation layer for the etch stop, and a surface layer higher than the etch stop layer of the combined silicon single crystal thin film A thickness reducing step of reducing the thickness of the bonded silicon single crystal thin film by selectively etching the side based on the oxygen concentration difference;
  • the method of the first invention basically applies the principle of the smart cut method.However, in the conventional smart cut method, only one ion-implanted layer is formed. There is a feature in forming two. Specifically, it is Bondueja An ion implantation layer for separation is formed on the second substrate, and an ion implantation layer for etch stop is formed at a position shallower than the ion implantation layer for separation. Then, after bonding the second substrate on which the two ion implantation layers are formed to the first substrate, which is a base wafer, the bonded silicon single crystal thin film is peeled off from the second substrate by the ion implantation layer for peeling.
  • the surface layer portion of the bonded silicon single crystal thin film bonded on the first substrate by this peeling is etched up to an etch stop layer formed based on the ion implantation layer for etch stop.
  • the etch stop layer formed therein has a higher oxygen concentration than the surrounding portion and is formed as a high oxygen concentration layer based on the ion implantation layer for etch stop.
  • Such a high oxygen concentration layer in silicon (for example, a silicon oxide layer) has a remarkable etching selectivity with respect to an alkaline solution or the like with silicon having a low oxygen concentration, so that the etching of the bonded silicon single crystal thin film is performed. It can be stopped reliably. ⁇
  • the above-mentioned ion implantation layer for etch stop is formed with reference to the main surface of the second substrate having good flatness before bonding the second substrate, and is shallower than the ion implantation layer for peeling. Therefore, variations in ion implantation depth hardly occur. Accordingly, the obtained etch stop layer has an oxygen concentration profile having a steep and uniform peak position depth reflecting the flatness of the main surface of the substrate finished by mirror polishing or the like. As a result, by etching back the bonded silicon single crystal thin film to the etch stop layer, it is possible to obtain an SOI layer having an extremely good film thickness distribution not only within the wafer but also between the wafers.
  • the surface of the bonded silicon single crystal thin film once becomes a relatively rough peeled surface as in the conventional smart cut method due to the peeling by the peeling ion implantation layer.
  • it is flattened by etching which also serves to reduce the thickness of the bonded silicon single crystal thin film. That is, conventionally, the thickness distribution of the SOI layer Tatchibolish, which was the main cause of the deterioration, is eliminated from the process.
  • the surface can be sufficiently flattened without severe heat treatment.
  • the second substrate is preferably a mirror-polished wafer whose first main surface used as a reference for ion implantation is a mirror-polished surface.
  • the thickness uniformity of the finally obtained SOI layer can be ensured to be, for example, 0.4 nm or less in terms of the standard deviation of the film thickness in the same wafer.
  • a method for manufacturing an SOI wafer according to the second invention includes at least one of a first substrate (corresponding to a base wafer) and a second substrate made of silicon single crystal (corresponding to a bond wafer).
  • the portion located on the side opposite to the first silicon layer portion in the thickness direction of the second substrate is As a second silicon layer portion, after the bonding step, at least a region of the second silicon layer portion that is in contact with the etch stop layer is selectively etched based on the oxygen concentration difference, thereby reducing the thickness.
  • the formation of the etch stop layer and the selective etching are performed in the same manner as in the first invention. Therefore, the functions and effects of the etch stop layer are exactly the same as those of the first invention.
  • the distribution of ions in the implantation depth direction can be relatively well controlled by controlling the ion implantation energy.
  • the implanted ions form crystal defects (damaged layers) in the second silicon layer of the second substrate.
  • the oxygen diffused into the second substrate is captured by the crystal defects to form an etch stop layer.
  • the etch stop layer has an oxygen concentration profile shape with a steep and uniform peak position depth corresponding to the implanted ion distribution of the etch stop ion implanted layer and thus the crystal defect distribution.
  • the uniformity of the film thickness of the I layer can be ensured to be, for example, 0.4 nm or less by the standard deviation of the film thickness in the same wafer. It is also possible to ensure that the standard deviation value between the wafers of the same specification is 2 nm or less. As a result, even if the SOI layer is made ultra-thin to 50 nm or less, and even to 20 nm or less, it is possible to reduce the variation in film thickness within and between wafers to a range that can sufficiently withstand practical use. It becomes possible.
  • the step of forming an ion injection layer for etch stop is performed from the first main surface of the second substrate prior to the bonding step.
  • a portion of the second silicon layer including a region in contact with the etch stop ion implantation layer or the etch stop layer formed based on the etch stop ion implantation layer is removed.
  • a pre-thinning step of reducing the thickness of the second substrate can be performed.
  • a method for manufacturing an SOI wafer in which an SOI layer is formed on a surface of an insulating film so as to have a different thickness is provided.
  • the second substrate By implanting ions by ion implantation from the first main surface side of the second substrate to the second substrate on which the pattern layer is formed, the second substrate to be a so I layer as viewed from the first main surface A first depth position separated by one silicon layer portion; an etch stop ion injection layer for forming an etch stop ion injection layer having different formation depth positions from the first main surface according to the pattern of the pattern layer; After the ion injection layer forming step and the pattern layer being removed from the second substrate, the second substrate and the first substrate are bonded to each other with the first main surfaces interposed therebetween via the insulating film.
  • the laminating process
  • the area in contact with the etch stop layer is determined based on the oxygen concentration difference.
  • a first feature of the third method is that an ion-implantation ion-implantation layer is formed in a second substrate, which is a bond wafer made of silicon single crystal, by an ion-implantation method.
  • ions are implanted into the etch stop ion implantation layer from the first main surface J side of the second substrate 1 on which the pattern layer 20 is formed. It is formed by this. Therefore, the formed ion implantation layer 6 for etch stop is located at the first depth position across the first silicon layer portion 60 to be the SOI layer as viewed from the first main surface J. From each other.
  • the formation depth position of the etch stop ion implantation layer can be controlled by appropriately adjusting the ion implantation energy, the thickness of the silicon oxide film, and the thickness of the pattern layer.
  • the ion implantation layers for etch stop formed at different depth positions are formed without interruption in the in-plane direction.
  • the film thickness of the first silicon layer 60 to be the SOI layer can be appropriately adjusted as shown in FIGS. 19A to 19D.
  • FIGS. 19B and 19D show an example of manufacturing an SOI wafer including a region having a thickness of a part in the SOI layer. Is a case where a region having a zero film thickness is not formed.
  • FIGS. 19A and 19B show the case where the silicon oxide film 2 and the pattern layer 20 are formed on the first main surface J.
  • FIGS. 19C and 19D show the first main surface.
  • the ion implantation is performed in any of those states.
  • the pattern layer is formed in a predetermined pattern using known photolithography and photoetching.
  • the pattern at this time is reflected on the film thickness pattern of the first silicon layer portion to be the SOI layer.
  • etch stop layer that is an oxygen-rich layer having a higher oxygen concentration than its surroundings.
  • Such a high oxygen concentration layer in silicon for example, a silicon oxide layer
  • the ion implantation layer for etch stop is formed with reference to the first main surface of the second substrate having good flatness, the ion implantation depth does not easily vary. This means that even if a pattern layer or an insulating film is formed on the first main surface, the flatness of the first main surface reflects the flatness of the first main surface. It can be said that variations in depth are unlikely to occur. Therefore, the obtained etch stop layer has an oxygen concentration profile shape that is steep and has a uniform peak position depth reflecting the flatness of the first main surface finished by mirror polishing or the like.
  • the second substrate should use a mirror-polished wafer whose first main surface is a mirror-polished surface. Particularly, it is preferable in the third invention.
  • the first substrate and the second substrate from which the pattern layer has been removed by etching or the like are attached to each other on the first main surfaces via an insulating film.
  • the bonded silicon single crystal thin film that is to be the S ⁇ I layer including the etch stop layer formed based on the ion implantation layer for etch stop is etched back by etch back.
  • the second silicon layer is etched to the etch stop layer.
  • the etching reduction of the second substrate itself may be performed directly by etch back, but it is advisable to use the following method from the viewpoint of work efficiency.
  • One of them includes a region in contact with an etch stop ion implantation layer or an etch stop layer formed based on the etch stop ion implantation layer after the bonding step and prior to the etching thickness reducing step.
  • This preliminary thickness reduction step is performed by mechanical grinding or mechanical chemical polishing using a surface grinder, etc., or in this case, the thickness reduction of only the silicon layer of the second silicon layer can be considered.
  • a method using a solution having an etching rate higher than the etching liquid used in the process is performed by a method such as dry etching having a high etching rate.
  • a method applying the principle of the conventional smart cut method can be adopted as one of the effective methods other than the above.
  • ions are implanted from the first main surface side of the second substrate, so that the ion implantation profile in the depth direction has a second depth deeper than the first depth position described above.
  • An ion-implanted layer for stripping having a concentration peak at the position is formed in advance.
  • the second substrate is separated at the separation ion-implanted layer.
  • the surface of the bonded silicon single crystal thin film serving as the separation surface due to separation in the ion implantation layer for separation is the same as in the conventional smart cut method.
  • the surface is rough, the surface is not flattened by the touching brush, but is flattened by the etching thinning process which also serves to reduce the thickness of the bonded silicon single crystal thin film. Therefore, even though the conventional smart cut method is used, the tactile polishing is not required. Also, even if there is some unevenness in the surface roughness of the peeled surface, the history almost disappears by etching, and severe heat treatment conditions are not required at all.
  • FIGS. 21A and 21B show an example in which the ion implantation layer 4 for peeling is formed in a state where at least the pattern forming layer 21 to be a pattern layer is formed.
  • FIG. 21A shows a state where the insulating film 2 is formed
  • FIG. 21B shows a state where the insulating film is not formed.
  • a pattern layer is formed.
  • an ion implantation layer 6 for etch stop is formed, and then, a strip ion implantation layer 4 is formed with the pattern layer removed. It is an example.
  • FIG. 21C shows a state in which the insulating film 2 is formed
  • FIG. 21D shows a state in which the insulating film is not formed.
  • the reason why the ion implantation layer for peeling is formed in such a form is that the ion implantation layer for peeling is formed before the bonding step, depending on the heating conditions required for forming the pattern forming layer to be the pattern layer. This is because it is assumed that the peeling may occur in an unintended form.
  • an SOI wafer in which SOI layers having different thicknesses are formed on the surface of the insulating film as shown in the schematic diagrams of FIGS. 20A and 2OB is finally obtained.
  • the level of non-uniformity of the thickness of the SOI layer can be reduced more effectively than the conventional one, and the standard deviation of the thickness within the same wafer can be improved.
  • the difference value can be kept to 0.4 nm or less.
  • the standard deviation between wafers with the same specifications can be kept below 2 nm.
  • the maximum thickness of the SOI layer of the SOI wafer is ultra-thin, 50 nm or less, or even 20 nm or less
  • film thickness variations within and between wafers can be reduced to a range that can withstand practical use.
  • the film thickness variation can be reduced to the above numerical range, it is possible to significantly improve the functional characteristics of the semiconductor device using the SOI wafer.
  • the term “SOI layer having a different thickness” is used to demarcate regions so that the thicknesses are intentionally different. This is the result of trying to form a uniform film thickness over the entire surface as in the conventional SOI wafer manufacturing method. It is different from SOI @ Eha.
  • the standard deviation value of the thickness of the SOI layer referred to here is a standard deviation value for each region intentionally formed so that the formed film thickness is the same or an average thereof. It shall indicate a value.
  • FIGS. 20A and 20B in FIG. 20B, it indicates the standard deviation value or the average value of the film thickness of each layer forming the SOI layer, and in FIG. It indicates the standard deviation of the film thickness of each A region and each B region or its average value.
  • FIG. 1 is a process explanatory view showing a first embodiment of an SOI wafer manufacturing method according to a first invention.
  • Figure 2 shows the effect of particles on the formation of the etch stop layer.
  • FIG. 3 is a diagram schematically showing an example of removing a damaged layer after a peeling step.
  • FIG. 4 is a diagram schematically showing an example of removing a damaged layer after the thickness reducing step.
  • FIG. 5 is an explanatory diagram of the effect of the present invention.
  • FIG. 6 is a process explanatory view showing a second embodiment of the SOI wafer manufacturing method according to the first invention.
  • FIG. 7 is a process explanatory view showing a third embodiment of the SOI wafer manufacturing method according to the first invention.
  • FIG. 8 is a process explanatory view showing a fourth embodiment of the SOI wafer manufacturing method according to the first invention.
  • FIG. 9 is a process explanatory view showing a modified example of the process of forming the ion stop layer for the etch stop.
  • FIG. 1OA is a first diagram showing the problems of the conventional method for manufacturing SOI wafers.
  • FIG. 10B is a second diagram showing the problems of the conventional method for manufacturing S O I ⁇ : —C.
  • FIG. 10C is a third diagram showing a problem of the conventional method for manufacturing an SOI wafer.
  • FIG. 11 is a process explanatory view showing a first embodiment of the SOI wafer manufacturing method according to the second invention.
  • FIG. 12 is a process explanatory view showing a second embodiment of the SOI wafer manufacturing method according to the second invention.
  • FIG. 13 is a process explanatory view showing a first embodiment of the method for producing an SOI wafer according to the third invention.
  • Figure 14 illustrates the effect of particles on the etch stop layer formation, along with the countermeasures.
  • FIG. 15 is a diagram schematically showing an example of removing a damaged layer after a peeling step.
  • FIG. 16 is a process explanatory view showing a second embodiment of the method for manufacturing an SOI wafer according to the third invention.
  • FIG. 17 is an explanatory process diagram showing a third embodiment of the method for manufacturing an SOI wafer according to the third invention.
  • FIG. 18 is a process explanatory view showing a fourth embodiment of the method for producing an SOI wafer according to the third invention.
  • FIG. 19A is a first schematic diagram for explaining a first embodiment of the production method of the third invention.
  • FIG. 19B is a second schematic diagram for explaining the first embodiment of the production method of the third invention.
  • FIG. 19C is a third schematic view for explaining the first embodiment of the production method of the third invention.
  • FIG. 19D is a fourth schematic view for explaining the first embodiment of the production method of the third invention.
  • FIG. 2OA is a first schematic diagram for explaining an SOI wafer targeted by the third invention.
  • FIG. 20B is a second schematic diagram for explaining the SOI wafer targeted by the third invention.
  • FIG. 21A is a first schematic diagram for explaining a second embodiment of the production method of the third invention.
  • FIG. 21B is a second schematic diagram for explaining a second embodiment of the production method of the third invention.
  • FIG. 21C is a third schematic diagram for explaining a second embodiment of the production method of the third invention.
  • FIG. 2D is a fourth schematic view for explaining the second embodiment of the production method of the third invention.
  • FIG. 22 is a process explanatory view showing a modification of the process for forming an ion implantation layer for etch stop.
  • FIG. 23 is an explanatory process diagram showing a fifth embodiment of the method for producing an SOI wafer according to the third invention.
  • FIG. 24 is an explanatory process diagram showing a sixth embodiment of the method for producing an SOI wafer according to the third invention.
  • FIG. 1 illustrates a basic embodiment of a method for manufacturing an SOI wafer according to the first invention.
  • the base as the first substrate
  • a silicon oxide film 2 as an insulating film is formed on the first main surface J side of the bond wafer 1.
  • the silicon oxide film 2 can be formed by, for example, wet oxidation, but a method such as CVD (Chemical Vapor Deposition) can also be adopted.
  • the thickness ta of the recon oxide film is set to a value of not less than 50 nm and not more than 2 / m in consideration of being used as a layer of a MOS FET or the like.
  • the base wafer 7 (first substrate) is also a silicon single crystal substrate, but this may be an insulating substrate such as a quartz substrate or a sapphire substrate, or a SiC, GaAs, In It is also possible to use a compound semiconductor substrate such as P. Also, instead of the silicon oxide film 2, a silicon nitride film / silicon oxynitride film or the like can be formed as an insulating film.
  • step (1) hydrogen ions are implanted into the first main surface of the bond wafer 1; in this embodiment, the main surface J on which the silicon oxide film 2 is formed by irradiating a hydrogen ion beam, for example.
  • An ion implantation layer 4 for separation is formed.
  • the peeling ion-implanted layer 4 showed a hydrogen concentration at a position of 100 11 m or more and 200 nm or less (first depth position da). It is good to form it so that a peak position occurs.
  • the first depth position da corresponds to the thickness of the bonded silicon single crystal thin film 5.
  • the first depth position da is less than 100 nm, a sufficiently thick bonded silicon single crystal thin film 5 (described later) cannot be obtained, and if it exceeds 2000 nm, the energy of the ion implanter becomes extremely high. Need to be done.
  • the average thickness tc of the SOI layer 15 (process 1) to be finally obtained is set to about 10 to 50 nm, the ion implantation layer 4 for peeling is formed by hydrogen in the depth direction of the wafer.
  • the concentration profile was measured, the position of 100 to 500 nm (first depth position da: except for silicon oxide film 2 if silicon oxide film 2 is formed on the surface) It is preferable to form such that a peak position of the hydrogen concentration is generated at the depth.
  • the ion The implantation depth is adjusted by the ion energy (acceleration voltage). For example, when using hydrogen ions, setting the thickness ta of the silicon oxide film to 50 nm sets the first depth position da for ion implantation for separation. It is preferable to adjust the energy of the ion implantation for forming the layer 4 to about 10 kV to 60 keV.
  • the ions for forming the separation ion-implanted layer are at least one selected from the group consisting of hydrogen ions and rare gas (He, Ne, Ar, Kr, Xe) ions.
  • the ion implantation layer 4 for exfoliation may be formed by implanting rare gas ions such as helium ions, neon ions, or argon ions instead of hydrogen ions.
  • ions are implanted from the same first main surface J of the bond wafer (second substrate) 1 to form a second depth position (but, When the silicon oxide film 2 is formed on the surface, the silicon oxide film 2 is represented by a depth excluding the silicon oxide film 2).
  • the etch stop ion implantation layer 6 is preferably formed so as to be located at least 50 nm shallower than the first depth position.
  • the average thickness tc of the SOI layer 15 (process 1) to be finally obtained is set to about 10 to 50 nm, but is set at a position of 50 to 300 nm (the second depth position db ) Should be formed so that the peak position of the hydrogen concentration occurs.
  • This second depth position db corresponds to the thickness of the SOI layer 15 finally obtained.
  • the ion implantation energy for forming the ion implantation layer 6 for etch stop at the second depth position db is as follows. When setting to nm, it is better to adjust to about 5 k to 40 keV. As described above, since implantation can be performed at a lower energy and shallower than in the case of ion implantation for exfoliation, variation in ion implantation depth can be further reduced, which leads to uniformity in the thickness of the SOI layer.
  • the ion implantation amount at the time of forming the ion implantation layer 6 for etch stop is 1 ⁇ 10 15 Z cm 2 to 4 ⁇ 10 16 / cm 2 , which is smaller than the ion implantation amount at the time of forming the ion implantation layer 4 for stripping. It is better to make it smaller. If it is less than 1 ⁇ 10 15 Zcm 2 , the formation of the later-described etch stop layer 6 (process 1) will be incomplete, and the desired etch stop effect will not be obtained. If the ion implantation amount exceeds 4 ⁇ 10 16 Zcm 2 , undesired separation of the bond wafer (second substrate) 1 may occur in the ion implantation layer 6 for the etch stop.
  • the ion species for forming the etch stop ion implanted layer 6 can be variously selected depending on what method is used to form the etch stop ion implanted layer 6 as an etch stop layer composed of a high oxygen concentration layer. it can. For example, at least one selected from the group consisting of hydrogen ions, rare gas ions and silicon ions can be used. In the process of FIG. 1, hydrogen ions (or rare gas ions such as helium ions and argon ions or silicon ions instead of hydrogen) may be used. These ion species mainly serve to form crystal defects (damage) in the bondue (second substrate) 1 for capturing oxygen.
  • step (3) the wafers (1) and (7) are bonded together on the side on which the silicon oxide film (2) is formed (that is, on the first main surface (J, K side)).
  • step (1) the laminate is heat-treated at a low temperature of 400 to 600 ° C., so that the bond wafer 1 is peeled at substantially the concentration peak position of the above-described peeling ion-implanted layer 4, and the base wafer 1 ⁇ side The remaining portion becomes the bonded silicon single crystal thin film 5 (peeling step).
  • the ion implantation layer 6 for the etch stop does not peel off due to the heat treatment because the ion implantation amount is kept low.
  • the peeling heat treatment can be omitted by increasing the ion implantation amount when forming the peeling ion-implanted layer 4 or by activating the surface by performing plasma treatment on the surfaces to be overlapped in advance. is there.
  • the remaining bondweed portion 3 after peeling can be reused as a bondwere or base wafer again after re-polishing the peeled surface.
  • an etch stop layer 6 ′ having a higher oxygen concentration than the surrounding portion is formed in the bonded silicon single crystal thin film 5 based on the above-described ion implantation layer 6 for etch stop.
  • Etch stop layer forming step the oxygen concentration of the etch stop ion implanted layer 6 is reduced by performing an oxygen diffusion step of diffusing oxygen from the surface of the bonded silicon single crystal thin film 5 toward the etch stop ion implanted layer 6.
  • a kind of internal oxidation treatment is performed to form an elevated etch stop layer 6 '.
  • a certain density of crystal defects are formed in a concentrated manner in the form of the ion implantation layer 6 for etching stop by ion implantation with hydrogen ions or the like, so that oxygen diffused from the wafer surface is formed.
  • the oxygen diffusion step can be specifically performed by a heat treatment in an oxygen-containing atmosphere.
  • an oxygen-containing atmosphere for example, an oxygen gas atmosphere, an oxygen mixed gas in which oxygen is mixed with nitrogen or argon, and a gas atmosphere made of a gas (eg, water vapor) composed of a compound molecule containing an oxygen atom can be used.
  • the heat treatment temperature increases, the diffusion rate of oxygen increases, and the formation of the etch stop layer 6 ′ can be promoted. However, if the heat treatment temperature is too high, Crystal defects (eg, Oxygen-induced Stacking Faults) in the ion implanted layer 6 can grow and penetrate the S ⁇ I layer 15 ′. It is desirable that the heat treatment temperature for diffusion is set to 700 ° C. or more and 100 ° C. or less.
  • a damage layer 8d due to ion implantation is formed on the bonded silicon single crystal thin film 5 immediately after peeling.
  • the heat treatment temperature for oxygen diffusion is set to a relatively high temperature as described above, the above-described crystal defects grow and grow from the damaged layer 8d, and the problem of penetrating the SOI layer may be more likely to occur. .
  • the etching margin dc may be such that the damage layer 8d can be removed, and for example, it is appropriate to set the etching margin to about 0.05 to 0.15 / im.
  • the etching can be performed using chemical etching such as mixed acid etching such as hydrofluoric acid and nitric acid, alkali etching such as KOH and NaOH, or gas phase etching such as ion etching.
  • chemical etching such as mixed acid etching such as hydrofluoric acid and nitric acid, alkali etching such as KOH and NaOH, or gas phase etching such as ion etching.
  • the conventional touch-polishing for removing the damaged layer 8d is not performed.
  • the film thickness distribution of the bonded silicon single crystal thin film 5 after peeling is significantly impaired by the touching brush, and accordingly, an etching allowance for removing the damage layer 8 d is easily secured. It can be said that.
  • the oxygen diffusion heat treatment may be performed alone, but it may be combined with the heat treatment for other purposes.
  • a bonding heat treatment for firmly bonding the first substrate 7 and the bonded silicon single crystal thin film 5 (in the present embodiment, a step performed at a low temperature)
  • a bonding heat treatment for firmly bonding the first substrate 7 and the bonded silicon single crystal thin film 5 via the silicon oxide film 2 is required.
  • This bonding heat treatment is usually performed at a high temperature of 100 ° C or more and 130 ° C or less.
  • a protective oxide film 5a is formed on the surface of the bonded silicon single crystal thin film.
  • the etch stop layer 6 ′ is formed as a high oxygen concentration layer, but is finally removed, and does not require the high insulating property of the silicon oxide layer 2. Therefore, it is sufficient that the etch stop layer 6 ′ can sufficiently perform the etching stop function, and the formed thickness tb (6 in FIG. 1) is, for example, 2 nm or more and 50 nm or less. desirable. When the formed thickness is less than 2 nm, the etching stop function may be insufficient, and when the formed thickness exceeds 50 nm, the oxygen diffusion treatment tends to be lengthened.
  • the etch stop layer 6 'must be able to reliably stop the etching from progressing to the underlying silicon layer that should ultimately remain as the SOI layer 15. For example, as shown in (2) of FIG. 2, if foreign matter such as particles P is attached to the first main surface J of the bond wafer 1 serving as the ion implantation side when forming the ion implantation layer 6 for etch stop, Ion implantation is hindered in the adhesion region, and a large number of pinholes 6 h are generated in the obtained etch stop layer, from which etchant may penetrate and the underlying silicon layer may be damaged.
  • the ion implantation into the first main surface J of the bond wafer (second substrate) 1 and the cleaning of the first main table J are alternately repeated to adjust the predetermined dose. It is effective to adopt an injection method. That is, the ion implantation is repeated while removing foreign matter such as particles P by washing. In this case, since the possibility of the particles P reattaching to the exact same position on the wafer surface after cleaning is extremely small, the probability of occurrence of pinholes 6 can be greatly reduced. Further, instead of performing the cleaning, a method of repeating the ion implantation into the first main surface J of the bond wafer (second substrate) 1 while changing the angle may be adopted.
  • the ion beam can also flow around the lower side of the particle P.
  • the ion implantation angle or direction is changed, the ion implantation is performed while the shadow area of the particle P changes on the first main surface J.
  • the region not ion-implanted is reduced, and the probability of occurrence of pinholes 6 can be greatly reduced.
  • the oxide film 5a is removed with hydrofluoric acid as shown in step (1), and then the etch stop layer of the combined silicon single crystal thin film 5 is formed.
  • the portion 8 closer to the surface layer than 6 ′ is selectively etched based on the difference in oxygen concentration to reduce the thickness of the bonded silicon single crystal thin film.
  • an alkaline solution for example, an aqueous solution such as NaOH, KOH or TMAH (TetraMethyl Ammonium Hydroxide) can be used.
  • the etch stop layer 6 ' is formed based on the etch stop ion implantation layer 6 as described above.
  • the etch stop ion-implanted layer 6 is formed based on the main surface J of the bond wafer (second substrate) 1 having good flatness before bonding the bond wafer (second substrate) 1, Since it is formed at a position shallower than the layer 4, variations in ion implantation depth are unlikely to occur. Therefore, the etch stop layer 6 'has an oxygen concentration profile shape that is steep and has a uniform peak position depth reflecting the flatness of the main surface of the substrate finished by mirror polishing or the like.
  • the average thickness tc of the SOI layer 15 is set to an ultrathin film of about 10 to 50 nm.
  • the film thickness uniformity of the SOI layer 15 can be kept at, for example, 0.4 nm or less with the standard deviation of the film thickness within the same wafer, and the same specifications as shown in Fig. 5
  • the S ⁇ I layer 15 is ultra-thin to 20 nm or less (for example, 10 nm), it is possible to reduce variations in film thickness within and between wafers to a range that can withstand practical use. It becomes.
  • the etch stop layer 6 remaining on the SOI layer 15 is removed by etching, so that the SOI wafer 50 is obtained.
  • the etch stop layer 6 ' is a high oxygen concentration layer, for example, a silicon oxide layer, and can be easily removed by etching using hydrofluoric acid. Further, the etch stop layer 6 'may be removed by dry etching (gas phase etching).
  • a planarizing heat treatment for further planarizing the surface of the SOI layer 15 can be performed.
  • This flattening heat treatment can be performed in an inert gas such as argon gas or a hydrogen gas or a mixed gas thereof at a temperature of about 1100 to 1200 ° C. for a short time of about 1 to 2 hours.
  • Bonding can be performed together with heat treatment. Specifically, it can be performed using a heat treatment furnace with a heater such as a general batch type vertical furnace and a horizontal furnace, and a single wafer that completes the heat treatment in several seconds to several minutes by lamp heating or the like. It can also be performed using a RTA device.
  • Damage layer 15a may remain slightly. Therefore, as shown in FIG. 4, after the thickness reduction step, the outermost layer of the SOI layer 15 is thermally oxidized, and then the formed thermal oxide film 15 s is removed by etching with hydrofluoric acid or the like. By performing the oxidation treatment, the above-mentioned damaged layer 15a can be effectively removed.
  • the silicon oxide film 2 may be formed only on the side of the base wafer 7 (the steps after step (1) are the same as in FIG. 1). Also, as shown in steps (1) to (3) in FIG. 7, the silicon oxide films 2a and 2b are formed on the bonding surfaces (first main surfaces J and K) of both the base wafer 7 and the bond wafer 1. (Steps 1 and 2 are the same as in Figure 1).
  • an ion implantation layer for etch stop can be formed in the bonded silicon single crystal thin film using oxygen ions.
  • FIG. 8 shows an example of the process.
  • Step (2) is the same as in FIG.
  • the ion implantation layer 60 for etching stop is formed using oxygen ions.
  • the ion implantation layer 60 for etch stop is preferably formed such that a peak position of the oxygen concentration occurs at a position of 50 nm or more and 300 nm (second depth position db).
  • the ion implantation amount is preferably set to 1 ⁇ 10 15 / cm 2 to 4 ⁇ 10 17 / cm 2 .
  • the ion implantation layer 60 for etch stop can be formed as a high oxygen concentration layer from the beginning by oxygen ion implantation.
  • This heat treatment temperature is preferably in the range of 900 to 130 ° C. Selective etch below 900 ° C If the effect of improving the durability is small, and exceeds 130 ° C., a problem of metal contamination ⁇ the occurrence of slip dislocation occurs.
  • the heat treatment can be performed alone at 700 to 100 ° C., which is the same as the oxygen diffusion heat treatment of FIG.
  • the heat treatment atmosphere may be an inert gas (Ar) atmosphere, or an oxygen diffusion treatment using an oxygen-containing atmosphere to further enrich oxygen in the ion implantation layer 60 for etch stop. (So-called additional diffusion treatment of oxygen).
  • the above heat treatment can also be used for the bonding heat treatment performed after the peeling step is completed or the above-described surface protection oxidation heat treatment performed at a lower temperature prior to the bonding heat treatment.
  • the oxygen diffusion thermal treatment shown in the step (2) may be omitted. Step 1 and subsequent steps are the same as in Figure 1.
  • a preliminary ion implantation layer 6 is formed using at least one of hydrogen ion, rare gas ion, and silicon ion.
  • an ion implantation layer 60 for etch stop can be formed. After that, oxygen diffusion heat treatment may be further performed.
  • the ion stop layer for etch stop can be formed in the bonded silicon single crystal thin film using germanium ions.
  • the etch stop ion implant layer becomes a silicon-germanium layer and can immediately function as an etch stop layer to the silicon layer for a particular etchant.
  • the Etsuchin grayed solution for selectively etching the silicon layer with respect to silicon Hmm germanium layer, a mixed solution of kappa Omicron Eta and K 2 C r 2 0 7 and propanol are suitable (Bibliography; Applied Physics Letters, 56 (1990), 373-375).
  • an etch stop layer formed of Shirikonge Rumaniumu layer, S i S i G e can removed using an etching solution for selectively Etsuchin grayed respect, specifically, HF and H 2 0 2 and CH 3 A mixed solution with CO ⁇ H can be used. Electrochemical Society, 138 (1991) 202-204). Further, selective etching can be performed by using dry etching.
  • FIG. 11 illustrates a basic embodiment of a method for manufacturing an SOI wafer according to the second invention. Since there are many steps common to the first embodiment, detailed description of portions common to the first embodiment including possible modifications will be omitted, and differences will be described.
  • a base wafer 7 as a first substrate (see step 3) and a bond wafer 1 as a second substrate made of a silicon single crystal (see step 1) are prepared.
  • a silicon oxide film 2 as an insulating film is formed on the 'first main surface J side of the pondu wafer 2.
  • the silicon oxide film 2 can be formed by, for example, wet oxidation, but it is also possible to adopt a method such as CVD (Chemical Vapor Deposition).
  • the thickness t X of the silicon oxide film is set to a value of about 50 nm or more and 2 Aim or less in consideration of the fact that the silicon oxide film is used together with an insulating layer such as MIS-FET.
  • the base wafer 7 (first substrate) is also a silicon single crystal substrate.
  • this may be an insulating substrate such as a quartz substrate or a sapphire substrate, or a SiC, GaAs, I
  • a compound semiconductor substrate such as nP.
  • a silicon nitride film / silicon oxynitride film or the like can be formed as an insulating film.
  • step (1) hydrogen ions are implanted from the first main surface (bonding surface) J of the bond wafer 1 through the silicon oxide film 2 to a depth position corresponding to the SOI layer formation thickness (however, silicon oxide is applied to the surface).
  • the film 2 is formed, it is represented by a depth excluding the silicon oxide film 2).
  • the average thickness tc of the SOI layer 15 (process 1) to be finally obtained is set to about 10 to 50 nm, but the ion implantation layer 6 for etch stop is 50 to 50 nm. Formed so that a hydrogen concentration peak position occurs at a depth position db of 300 nm Good to do. This depth position db corresponds to the thickness of the SOI layer 15 finally obtained.
  • the ion implantation energy for forming the etch stop ion implantation layer 6 at the depth position db is 5 when hydrogen ions are used and the thickness tX of the silicon oxide film is set to 50 nm. It is better to adjust to keV or more and about 40 eV or less.
  • the amount of ion implantation when forming the ion implantation layer 6 for etch stop is preferably 1 ⁇ 10 15 / cm 2 to 4 ⁇ 10 16 cm 2 . If it is less than 1 ⁇ 10 15 / cm 2 , formation of damage for forming an etch stop layer 6 ′ (process (1)) described later will be incomplete, and an oxygen concentration layer having a sufficient etch stop effect will not be obtained. If the ion implantation amount exceeds 4 ⁇ 10 16 Zcm 2 , undesired peeling of the bonded silicon single crystal thin film 5 may occur in the ion implantation layer 6 for etching stop.
  • the ion species for forming the etch stop ion implanted layer 6 may vary depending on the method used to form the etch stop ion implanted layer 6 as an etch stop layer 6 composed of a high oxygen concentration layer. You can choose. For example, at least one selected from the group consisting of hydrogen ions, rare gas (He, Ne, Ar, Kr, and Xe) ions, silicon ions, and oxygen ions can be used. In the process of FIG. 11, hydrogen ions are used. These ion species mainly serve to form crystal defects (damage) in the bondue (second substrate) 1 to capture oxygen.
  • step (1) an oxygen diffusion step of diffusing oxygen toward the ion implantation layer for etch stop 6 is performed, thereby increasing the oxygen concentration of the ion implantation layer for etch stop 6 to increase the oxygen concentration of the etching stop layer.
  • 6 ′ is formed (etch stop layer forming step).
  • Oxygen diffused from the wafer surface is subjected to crystal defects (damaged) formed in the etch stop ion implantation layer 6. It can be easily formed on the etch stop layer 6 'composed of a high oxygen concentration layer.
  • This treatment can be said to be a kind of internal oxidation treatment.
  • the oxygen diffusion step in the etch stop layer forming step can be performed in the same manner as in the first embodiment.
  • step (3) the wafers (1) and (7) are bonded together on the side where the silicon oxide film 2 is formed (that is, on the first main surfaces J and K sides). A bonding heat treatment is performed at 250 ° C.
  • step (2) the bond wafer 1 is reduced while leaving the bonded silicon single crystal thin film 5 to be the SOI layer including the etch stop layer 6 '.
  • the bond silicon wafer 8 is mechanically ground using a surface grinder or the like while leaving a silicon layer 8 for etching at about 0.1 to 10 / m on the etch stop layer 6, and further, if necessary. Grind.
  • step (2) the silicon layer 8 for etching is etched back to the position of the etch stop layer 6 'by selective etching.
  • the etch stop layer 6 ′ is a force S formed as a high oxygen concentration layer, which is ultimately removed, and does not require complete insulation like the silicon oxide layer 2. Accordingly, it is sufficient that the etch stop layer 6 can sufficiently fulfill the etching stop function, and its formed thickness tb is desirably, for example, 2 nm or more. If the formed thickness is less than 2 nm, the etching stopping function may be insufficient.
  • the etch stop layer 6 ′ also performs the ion implantation into the first main surface J of the bond wafer (second substrate) 1 and the cleaning of the first main table J again. It is effective to adopt a method in which a predetermined dose is injected alternately and repeatedly. Instead of performing the cleaning, a method of repeating the ion implantation into the first main surface J of the bond wafer (second substrate) 1 while changing the angle may be adopted.
  • the portion 8 of the bonded silicon single crystal thin film 5 closer to the surface layer than the etch stop layer 6 ′ is selectively etched based on the oxygen concentration difference to reduce the thickness of the bonded silicon single crystal thin film.
  • an alkaline solution for example, an aqueous solution such as NaOH, KOH or TMAH (TetraMethyl Ammonium Hydroxide) can be used.
  • the etch stop layer 6 ′ is formed based on the etch stop ion implantation layer 6 as described above. Since the etch stop ion implantation layer 6 is formed at a shallow position corresponding to the average thickness tc of the SOI layer 15 of about 10 to 50 nm, the ion implantation depth does not easily vary. Les ,. Therefore, the etch stop layer 6 has an oxygen concentration profile shape which is relatively steep and has a uniform peak position depth. As a result, an SOI layer 15 having an extremely good film thickness distribution can be obtained not only within the wafer but also between the wafers corresponding to the oxygen concentration profile shape.
  • the obtained film thickness uniformity of the SOI layer 15 is the same.
  • the standard deviation of the film thickness within a wafer can be secured, for example, to 0.4 nm or less.
  • the SOI layer 7 is ultra-thin to 20 nm or less (for example, 10 nm), it is possible to reduce the variation in film thickness within the wafer and between wafers to a range that can sufficiently withstand practical use. Become.
  • the etch stop layer 6 ' is removed by etching.
  • the etch stop layer 6 ' is a high oxygen concentration layer, for example, a silicon oxide layer, and can be easily removed by etching using hydrofluoric acid. Further, the etch stop layer 6 may be removed by dry etching (vapor phase etching). After removing the etch stop layer 6 ′, a flattening heat treatment for further flattening the surface of the SOI layer 15 similar to the first embodiment can be performed.
  • the bonding and bonding in step (3) are performed. Synthetic heat treatment was performed, but after forming the ion implantation layer 6 'for etch stop in step (1), bonding and bonding heat treatment in step (3) was performed without performing oxygen diffusion heat treatment, and grinding and polishing in step (2) After performing the thickness reducing step, the same oxygen diffusion heat treatment as in step 1 may be performed.
  • a sacrificial oxidation process of thermally removing the outermost layer of the SOI layer 15 and then removing the formed thermal oxide film 15 s with hydrofluoric acid or the like may be performed. it can.
  • the silicon oxide film 3 may be formed only on the side of the base wafer 7, or the silicon oxide film may be formed on the bonding surfaces of both the base wafer 7 and the pondu wafer 1.
  • an ion implantation layer for etch stop can also be formed in the bonded silicon single crystal thin film using oxygen ions.
  • the ion implantation layer 6 for etch stop is formed using oxygen ions.
  • the etch stop ion implanted layer 6 is preferably formed such that a peak position of the oxygen concentration occurs at a depth position db of 50 to 300 nm. Further, the ion implantation amount is preferably set to 1 ⁇ 10 15 / cm 2 to 4 ⁇ 10 17 Z cm 2 .
  • the oxygen diffusion heat treatment in the step (2) can be omitted.
  • the heat treatment can be performed in an inert gas atmosphere such as argon instead of the oxygen atmosphere.
  • the oxygen concentration can be converted into the etch stop layer 6 while further increasing the oxygen concentration of the ion implantation layer 6 for etch stop. That is, by using the oxygen ion implantation and the oxygen diffusion heat treatment together, the oxygen concentration profile of the etch stop layer 6 can be made sharper with a higher peak oxygen concentration and, consequently, the combined silicon single crystal layer. 5 Selective etchability to reduce thickness be able to.
  • the heat treatment after the oxygen ion implantation promotes the reaction between the implanted oxygen ions and the silicon atoms, stabilizes the etch stop layer 6 ′, and also enhances the selective etching effect. If the heat treatment in step (2) is omitted, the bonding heat treatment in step (3) also serves as the heat treatment.
  • preliminary ions are implanted using any one of hydrogen ions, helium ions, and argon ions, and oxygen ions are implanted into the preliminary ion implanted layer to ultimately stop etching. It can also be used as an ion implantation layer.
  • step (1) after a porous silicon layer 31 is formed on the first main surface side of the bond wafer 1 by a well-known anodizing treatment, silicon to be an SOI layer is formed on the porous silicon layer 31.
  • the epitaxial layer 37 is grown in vapor phase. Further, a silicon oxide film 2 is formed on the surface of the silicon epitaxial layer 37, and ions are implanted from the surface thereof to form an ion implantation layer for etch stop.
  • step (2) the portion of the bond wafer 1 located above the porous silicon layer 31 is removed by surface grinding or the like, or a fluid is sprayed on the porous layer to peel it off.
  • step (3) the remaining porous silicon layer 31 and a portion of the silicon epitaxial layer / layer 37 above the etch stop layer 6 'are selectively etched.
  • steps 4 and 5 are the same as steps 5 and ⁇ in FIG.
  • the oxygen diffusion heat treatment for forming the etch stop layer 6 ′ removes only the porous silicon layer after the bonding heat treatment step and exposes the silicon epitaxial layer 37. Let It can be performed in a state.
  • FIG. 13 illustrates a basic embodiment of a method for manufacturing an SOI wafer according to the third invention.
  • a base wafer 7 as a first substrate and a bond wafer 1 as a second substrate made of a silicon single crystal shown in step (2) are prepared.
  • a silicon oxide film 2 as an insulating film is formed on the first main surface J side of the bond wafer 1.
  • This silicon oxide film 2 can be formed by, for example, wet oxidation or dry oxidation, but it is also possible to adopt a method such as CVD (Chemical Vapor Deposition).
  • the thickness of the silicon oxide film is set to a value of 50 nm or more and 2 // m 'or less in consideration of being used as an insulating layer of, for example, MOSS-FET.
  • the base wafer 7 (first substrate) is also a single crystal silicon substrate. 1 This may be an insulating substrate such as a quartz substrate or a sapphire substrate, or a SiC, GaAs, In It is also possible to use a compound semiconductor substrate such as P.
  • a silicon nitride film / silicon oxynitride film or the like can be formed as an insulating film.
  • the formation of the silicon oxide film 2 may be omitted.
  • a pattern forming layer 21 to be a pattern layer 20 described later is formed on the main surface of the silicon oxide film 2 by CVD or the like so as to have a predetermined thickness.
  • the pattern forming layer 21 takes into account that the layer forming the lamination interface with the pattern forming layer 21 is made of silicon oxide (insulating film) such as silicon (bondua) or silicon oxide.
  • silicon oxide insulating film
  • a silicon nitride film can be formed as a pattern forming layer 21 by CVD or the like.
  • the surface can better reflect the good flatness of the first main surface J.
  • the pattern forming layer 21 when removing a pattern layer 20 formed based on the pattern forming layer 21 described later, only the pattern layer can be easily and reliably etched away with hot phosphoric acid. Further, as the pattern forming layer 21, a silicon oxide film or a resist film can be used in addition to the silicon nitride film. After forming the pattern forming layer 21 in this manner, the first main surface J of the bond wafer 1, and in this embodiment, the first main surface J on which the silicon oxide film 2 is formed in addition to the pattern forming layer 21. Then, hydrogen ions are implanted by, for example, irradiating a hydrogen ion beam to form a separation ion-implanted layer 4.
  • the conditions for forming the ion implantation layer 4 for stripping are as follows: when the hydrogen concentration profile in the depth direction of the wafer is measured, the position (100 nm or more and 200 nm or less) It is preferable to form the structure so that the peak position of the hydrogen concentration occurs at the second depth position da). Further, in order to perform a smooth peel smoothly, to inject the amount of hydrogen ions (amount de chromatography's) and 2 X 1 0 1 6 pieces / cm 2 ⁇ 1 X 1 0 1 7 or Bruno c 'm 2 Is desirable.
  • the pattern layer 20 can be formed by a patterning process using known photolithography and photoetching.
  • the surface of the pattern forming layer 21 is formed so as to reflect the good flatness of the first main surface J as described above, the pattern layer 20 naturally reflects the flatness. Things. '
  • a hydrogen ion beam is irradiated from the first main surface J side of the bond wafer 1, that is, in this embodiment, to the respective surfaces of the pattern layer 20 and the silicon oxide film 2.
  • Hydrogen ions are implanted, and the pattern layer has a concentration peak at each of the first depth positions shallower than the second depth position (similar to the second depth position, the depth from the first main surface J).
  • the etch stop ion implantation layer 6 having a different formation depth position from the first main surface J is formed according to the 20 pattern.
  • the difference in depth at the first depth position and the depth itself for forming the ion implantation layer 6 for chistop are determined by the thickness of the pattern layer 20, the thickness of the silicon oxide film 2, and the irradiation depth. It is adjusted by the ON energy. In this manner, the ion implantation layer 6 for etch stop having various predetermined first depth positions is formed without interruption in the in-plane direction. Further, from the viewpoint of sufficiently securing the formation thickness of the region having the maximum thickness in the finally obtained SOI layer 15, the deepest position in the first depth position is larger than the second depth position. It is desirable to form it so as to be located at least 50 nm shallower.
  • the average thickness tc of the region having the maximum thickness in the SOI layer 15 (process 1) to be finally obtained is set to about 10 to 50 nm. It is better to form the position so that the deepest position db is at a position of 50 to 300 nm.
  • the ion implantation amount when forming the etch stop ion implantation layer 6 is preferably 1 ⁇ 10 15 Z cm 2 to 4 ⁇ 10 16 / cm 2 . Further, the ion species for forming the ion implantation layer for etch stop 6 are also the same as in the first embodiment.
  • the ion implantation layer 4 for peeling and the ion implantation layer 6 for etching stop are formed in the bond wafer 1.
  • the ion implantation layer 4 for peeling is formed first with the layer 21 for pattern formation formed, when forming the ion implantation layer for peeling, for example, Even if surface contamination or surface roughness due to the attachment of foreign matter or the like to the surface of the application layer 21 occurs, it is finally removed together with the removal of the pattern layer 20.
  • the bonding can be performed well.
  • the bond wafer 1 and the base wafer 7 on which the ion implantation layer 4 for stripping and the ion implantation layer 6 for etching are formed the pattern layer 20 is removed from the bond wafer 1 by, for example, etching, and then washed with a cleaning liquid. Washed.
  • the wafers (1) and (7) are bonded together on the side where the silicon oxide film 2 is formed (that is, on the first main surface J and K sides).
  • step (2) the laminate is By performing the heat treatment at a low temperature of about 600 ° C., the bond wafer 1 is separated at the approximate concentration peak position of the above-described ion-implanted layer 4 for separation, and the portion remaining on the base wafer 1 side is a bonded silicon single crystal thin film. It becomes 5 (preliminary thickness reduction step).
  • the ion implantation layer 6 for etch stop does not peel off due to the heat treatment because the ion implantation amount is kept low.
  • an etch stop layer 6 ′ having a higher oxygen concentration than the surrounding portion is formed in the bonded silicon single crystal thin film 5 based on the above-described ion implantation layer 6 for etch stop.
  • Etch stop layer forming step In the present embodiment, from the surface of the bonded silicon single crystal thin film 5, that is, from the surface on the second silicon layer 61 side in the thickness direction of the bond wafer (second substrate), the ion implantation layer for etch stop is formed.
  • an oxygen diffusion step of diffusing oxygen by means of oxygen a kind of internal oxidation treatment is performed in which the oxygen concentration of the ion implantation layer for etch stop 6 is increased to form the etch stop layer 6 ′.
  • a certain concentration of crystal defects is concentratedly formed in the form of the ion implantation layer 6 for etching stop by ion implantation with hydrogen ions or the like, so that oxygen diffused from the surface of the wafer is removed.
  • the etch stop layer 6 ' can be easily formed as a high oxygen concentration layer by being captured by crystal defects formed in the etch stop ion implantation layer 6.
  • the oxygen diffusion step can be performed by heat treatment in an oxygen-containing atmosphere, as in the first embodiment.
  • the heat treatment temperature for oxygen diffusion is desirably set to 700 ° C. or more and 100 ° C. or less.
  • the outermost layer portion of the bonded silicon single crystal thin film 5 can be removed by etching.
  • the etching allowance dc in this case may be such that the damaged layer 8d shown in FIG. 15 can be removed, and is set to, for example, about 0.1 to 0.15 z ra.
  • the conventional touch-polishing for removing the damaged layer 8d is not performed.
  • the thickness distribution of the bonded silicon single crystal thin film 5 after peeling is not longer any concern that it will be greatly impaired by Tatsubolish. Accordingly, an etching fee for removing the damage layer 8d is secured.
  • the oxygen diffusion heat treatment may be performed alone, but it is also possible to use the heat treatment for another purpose as in the first embodiment. Further, it is desirable that the formed thickness of the etch stop layer 6 is, for example, not less than 2 nm and not more than 50 nm.
  • the etch stop layer 6 ′ must be able to reliably stop etching from progressing to the underlying silicon layer that should ultimately remain as the SOI layer 15.
  • foreign matter such as particles P adheres to the surface on the first main surface J of the bond wafer 1 which is the ion injection side when forming the ion implantation layer 6 for etch stop.
  • ion implantation is hindered in the adhesion region, and a large number of pinholes 6 h are generated in the obtained etch stop layer, from which the etching liquid may penetrate and the underlying silicon layer may be attacked. .
  • the etch stop layer 6 ′ is formed in this manner, as shown in step ⁇ , after the oxide film 5 a is removed with hydrofluoric acid, the etch stop of the combined silicon single crystal film 5 is stopped. 6, the surface of the second silicon layer 61, at least the region in contact with the etch stop layer 6 ', is selectively etched based on the oxygen concentration difference, so that the combined silicon single crystal thin film 5 is formed. To reduce the thickness.
  • the average thickness tc of the region having the maximum thickness in the SOI layer 15 is set to be an ultrathin film of about 10 to 50 nm
  • the SOI layer 15 The film thickness uniformity can be ensured to be, for example, 0.4 nm or less by the standard deviation of the film thickness within the same wafer, and as shown in FIG.
  • the film thickness within the wafer and between the wafers can be reduced. Variations can be reduced to the extent that they are sufficiently practical.
  • the etch stop layer 6 'remaining on the SOI layer 15 is removed by etching as shown in step (2), whereby the SOI wafer 50 is obtained.
  • the etch stop layer 6 ' is a high oxygen concentration layer, for example, a silicon oxide layer, and can be easily removed by etching using hydrofluoric acid.
  • the SOI layer is formed as shown in FIG. 20B, the etch stop layer 6 'and the silicon oxide film 2 may be in contact with each other. In that case, if necessary, The etch stop layer 6 'may be removed.
  • a planarization heat treatment for further planarizing the surface of the SOI layer 15 can be performed as in the first embodiment.
  • the SOI wafer manufactured by the above process has SOI layers having different thicknesses in the plane and has excellent uniformity in film thickness. If devices are fabricated using such SII I wafers, it is easy to mix SOI layers with different thicknesses in one chip, which can be useful for diversification of devices to be fabricated.
  • a silicon oxide film may be formed only on the first main surface of the base wafer.
  • a silicon oxide film can be formed on the bonding surfaces (first main surfaces J and K) of both the base wafer and the bond wafer.
  • an ion implantation layer for etch stop oxygen ions are used.
  • An ion implantation layer for etch stop can be formed in the bonded silicon single crystal thin film.
  • FIG. 18 shows an example of the process.
  • Step (2) is the same as FIG.
  • an ion implantation layer 62 for etch stop is formed using oxygen ions.
  • the etch stop ion implantation layer 62 is preferably formed so that a peak position of the oxygen concentration occurs at a position (depth position db) of 50 nm or more and 500 or less.
  • the ion injection amount is preferably 1 ⁇ 10 15 pieces / cm 2 to 4 ⁇ 10 17 pieces / cm 2 .
  • the ion implantation layer 62 for etch stop can be formed as a high oxygen concentration layer from the beginning by oxygen ion implantation.
  • This heat treatment temperature is preferably in the range of 900 to 130 ° C. When the temperature is lower than 900 ° C., the effect of improving the selective etching property is small, and when the temperature exceeds 130 ° C., a problem of metal contamination and slip dislocation occurs.
  • the heat treatment can be performed alone at 900 to 100 ° C.
  • the heat treatment atmosphere may be an inert gas (Ar) atmosphere, or an oxygen diffusion treatment using an oxygen atmosphere may be used to further enrich oxygen in the ion implantation layer 60 for the etch stop. (So-called additional diffusion treatment of oxygen).
  • the above-mentioned heat treatment may be combined with the bonding heat treatment or the above-mentioned surface protection oxidation heat treatment performed at a lower temperature prior to the bonding heat treatment. In this case, of course, in FIG. 18, the oxygen diffusion heat treatment shown in step 1 may be omitted. Note that the process after step (2) is the same as in Fig. 13.
  • the preliminary ion-implanted layer 66 is formed using one kind selected from the group consisting of hydrogen ions, rare gas ions, and silicon. It is also possible to form an etch stop ion implantation layer 6 by implanting oxygen ions into the preliminary ion implantation layer 66. You. Thereafter, an oxygen diffusion treatment may be further performed.
  • the ion implantation layer for etching stop can be formed in the bonded silicon single crystal thin film using germanium ions.
  • the ion implantation layer 4 for stripping is formed in the step (1), and then the ion implantation layer 6 for etch stop is formed in the step (2).
  • a pattern layer 20 is formed in step (1).
  • the etch stop ion implantation layer 6 is formed in step (2).
  • step (2) after removing the pattern layer 20 by etching or the like, the peeling ion-implanted layer 4 is formed. Subsequent steps 3 and thereafter are the same as those in Fig. 13.
  • the formation mode of the ion injection layer for peeling and the ion injection layer for etch stop can be performed as follows. As shown in FIG. 24, in step (1), after forming a pattern forming layer, a pattern layer 20 is formed. Then, an ion implantation layer 6 for etch stop is formed. Then, the ion implantation layer 4 for peeling is formed continuously. At this time, the separation ion implantation layer 4 also has different formation depth positions from the first main surface J according to the pattern of the pattern layer 20, but the difference in the formation depth positions, that is, If the difference in the desired film thickness required for the SOI layer (tb in Fig. 13) is sufficiently smaller than 50 (for example, 20 to 50 nm), there is no problem.
  • Bondueha (second substrate) 1 can be peeled at peeling ion implantation layer 4.
  • the separation ion implantation layer and the etch stop ion implantation layer can be continuously formed, so that the working efficiency can be improved.
  • the step of forming the ion implantation layer 6 for etch stop and then forming the ion implantation layer 4 for stripping was performed.
  • the order of forming them was reversed: After forming the ion-implantation layer 6 for etching stop and the ion-implantation layer 4 for stripping in the step (2), the steps after the step (2) are the same as the steps after the step (3) in FIG.
  • the separation ion implantation layer is formed, and the separation step is performed using the separation ion implantation layer. Another embodiment without such a peeling step will be described below.
  • FIG. 16 illustrates an embodiment of the manufacturing method according to the third invention, which does not include a peeling step.
  • step (1) an ion implantation layer 6 for etch stop is formed.
  • the pattern layer 20 is formed in the following form.
  • a silicon oxide film or a known resist film is formed on the first main surface J of the bond wafer 1 as a pattern layer forming layer.
  • the silicon oxide film or the resist film is subjected to a patterning process using photolithography so as to have a predetermined pattern, thereby forming a pattern layer 20.
  • the working efficiency can be improved by forming the pattern layer 20 directly on the silicon surface (the surface of the bond wafer 1) using a silicon oxide film or a resist film in particular.
  • a step (1) after removing the pattern layer 20 by etching or the like, an oxygen diffusion step of diffusing oxygen toward the ion implantation layer for etch stop 6 is performed. 6 to form an etch stop layer 6 ′ (etch stop layer forming step).
  • a layer region 5a is formed together with the etch stop layer 6 '.
  • the layer region 5a is to be a silicon oxide film.
  • step (3) both wafers (1) and (7) are bonded together on the formation side of the layer region (5a) which is a substitute layer for the silicon oxide film (that is, the first main surface (J) side), and a further 80 Bonding heat treatment is performed at 0 ° C to 125 ° C.
  • step (1) the bond evaha (second substrate) 1 is reduced while leaving a part of the second silicon layer 61 including a region in contact with the etch stop layer 6 '(preliminary reduction step).
  • the bonder 1 is mechanically ground using, for example, a surface grinder, leaving a silicon layer 61 ′ for etching on the etch stop layer 6 ′ of about 0.1 to 10 ⁇ m.
  • step (1) a silicon single crystal thin film 5 having a thickness similar to that of the bonded silicon single crystal thin film 5 in FIG. 13 is obtained.
  • step (1) the silicon layer 61 'is etched back to the position of the etching stop layer 6' by selective etching (etching thinning step).
  • etching thinning step is the same as step (1) in FIG. 13, and the subsequent steps are also the same.
  • step (3) After performing the bonding and bonding heat treatment in step (3) without performing the oxygen diffusion heat treatment, perform the preliminary thickness reduction step by grinding in step (2), and then perform the same oxygen diffusion heat treatment as in step (2). It may be.
  • the heat treatment of the oxygen diffusion heat treatment can also serve as the bonding heat treatment. Also, this bonding heat treatment may be performed simultaneously with the heat treatment of the planarization heat treatment performed after the step (1).
  • the oxygen diffusion heat treatment in the step (2) can be omitted.
  • an oxygen diffusion heat treatment may be performed to further increase the oxygen concentration.
  • the heat treatment may be performed in an inert gas atmosphere such as argon.
  • the bonding heat treatment in step (3) also serves as the heat treatment.
  • step (1) after a porous silicon layer 31 is formed on the first main surface side of the bond wafer 1 by well-known anodizing treatment, a silicon layer to be an SOI layer is formed on the porous silicon layer 31.
  • the epitaxial layer 37 is grown in vapor phase. Further Then, a pattern layer is formed by using a silicon oxide film or the like on the first main surface on the bonding surface side of the epitaxial layer 37, and ion implantation is performed from the first main surface side to form an etch stop.
  • An ion implantation layer for use After removing the pattern layer, an oxygen diffusion heat treatment is performed to form an etch stop layer 6 '. Then, on the first main surface of the silicon epitaxial layer 37, a bonding heat treatment for the base wafer 7 is performed. Next, as shown in step (2), a portion of the bond wafer 1 located above the porous silicon layer 31 is removed by grinding or the like, or a fluid is sprayed on the porous layer to peel it off. Then, as shown in step 3, the remaining porous silicon layer 31 and the portion of the silicon epitaxial layer 37 above the etch stop layer 6 'are selectively etched. Subsequent steps 4 and 5 are the same as steps 6 and ⁇ in FIG. Even in the case of using the ELTRAN method, the oxygen diffusion heat treatment for forming the etch stop layer 6 ′ removed only the porous silicon layer and exposed the silicon epitaxial layer 37 after the bonding heat treatment. It can be performed in a state.

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Abstract

L'invention concerne un procédé de production d'une plaquette de silicium sur isolant (SOI) permettant de réduire l'uniformité d'épaisseur de film intra-plaquette et l'uniformité d'épaisseur de film inter-plaquettes à des niveaux suffisamment faibles même si le niveau d'épaisseur de film requis d'une couche de SOI est très faible. Plus particulièrement, une couche d'implantation ionique de pelage (4) est formée sur une plaquette de liaison (1), une couche d'implantation ionique d'arrêt de gravure (6) étant formée plus superficiellement que cette couche d'implantation ionique de pelage (4). Ensuite, après le couplage de la plaquette de liaison (1) constituée des deux couches d'implantation ionique (4, 6) avec une plaquette de base (7), un film mince monocristallin de silicium lié (5) est arraché par pelage de la plaquette de liaison (1) au moyen de la couche d'implantation ionique de pelage (4). De plus, la couche avant du film mince monocristallin de silicium lié (5) collé sur la plaquette de base (7) par ce pelage est rétrogravée jusqu'à une couche d'arrêt de gravure (6') formée sur le modèle de la couche d'implantation ionique d'arrêt de gravure (6).
PCT/JP2003/009006 2002-07-18 2003-07-16 Plaquette de silicium sur isolant et son procede de production WO2004010505A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2002-209911 2002-07-18
JP2002209866A JP2004055750A (ja) 2002-07-18 2002-07-18 Ｓｏｉウェーハの製造方法
JP2002209911A JP4147577B2 (ja) 2002-07-18 2002-07-18 Ｓｏｉウェーハの製造方法
JP2002-209866 2002-07-18
JP2002221724A JP4147578B2 (ja) 2002-07-30 2002-07-30 Ｓｏｉウエーハの製造方法
JP2002-221724 2002-07-30

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Cited By (8)

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Publication number Priority date Publication date Assignee Title
WO2005074033A1 (fr) 2004-01-30 2005-08-11 Sumco Corporation Procede pour la fabrication de tranches soi
WO2008004591A1 (fr) * 2006-07-04 2008-01-10 Sumco Corporation Procédé de production d'une tranche liée
EP1914799A1 (fr) * 2005-07-29 2008-04-23 Shanghai Simgui Technology Co., Ltd Procede de production de silicium sur isolant
US7646296B2 (en) 2006-08-11 2010-01-12 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
JP2010045148A (ja) * 2008-08-12 2010-02-25 Sumco Corp 貼り合わせウェーハの製造方法
US8102281B2 (en) 2006-08-11 2012-01-24 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US8134481B2 (en) 2006-08-11 2012-03-13 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
WO2021079745A1 (fr) 2019-10-24 2021-04-29 信越半導体株式会社 Procédé de fabrication de substrat semi-conducteur et substrat semi-conducteur

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JPH021914A (ja) * 1988-06-10 1990-01-08 Sony Corp 半導体基板の製法
JPH027468A (ja) * 1988-06-25 1990-01-11 Sony Corp 半導体装置の製造方法
JPH0479372A (ja) * 1990-07-23 1992-03-12 Nissan Motor Co Ltd 半導体基板の製造方法
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Cited By (18)

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Publication number Priority date Publication date Assignee Title
WO2005074033A1 (fr) 2004-01-30 2005-08-11 Sumco Corporation Procede pour la fabrication de tranches soi
EP1710836A1 (fr) * 2004-01-30 2006-10-11 SUMCO Corporation Procede pour la fabrication de tranches soi
US7867877B2 (en) 2004-01-30 2011-01-11 Sumco Corporation Method for manufacturing SOI wafer
EP1710836A4 (fr) * 2004-01-30 2010-08-18 Sumco Corp Procede pour la fabrication de tranches soi
EP1914799A1 (fr) * 2005-07-29 2008-04-23 Shanghai Simgui Technology Co., Ltd Procede de production de silicium sur isolant
EP1914799A4 (fr) * 2005-07-29 2010-03-17 Shanghai Simgui Technology Co Procede de production de silicium sur isolant
US8048769B2 (en) 2006-07-04 2011-11-01 Sumco Corporation Method for producing bonded wafer
JP2008016534A (ja) * 2006-07-04 2008-01-24 Sumco Corp 貼り合わせウェーハの製造方法
WO2008004591A1 (fr) * 2006-07-04 2008-01-10 Sumco Corporation Procédé de production d'une tranche liée
US7999703B2 (en) 2006-08-11 2011-08-16 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US7646296B2 (en) 2006-08-11 2010-01-12 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US8102281B2 (en) 2006-08-11 2012-01-24 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US8134481B2 (en) 2006-08-11 2012-03-13 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US8193951B2 (en) 2006-08-11 2012-06-05 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
US8193950B2 (en) 2006-08-11 2012-06-05 Honda Motor Co., Ltd. Method and system for receiving and sending navigational data via a wireless messaging service on a navigation system
JP2010045148A (ja) * 2008-08-12 2010-02-25 Sumco Corp 貼り合わせウェーハの製造方法
WO2021079745A1 (fr) 2019-10-24 2021-04-29 信越半導体株式会社 Procédé de fabrication de substrat semi-conducteur et substrat semi-conducteur
KR20220090506A (ko) 2019-10-24 2022-06-29 신에쯔 한도타이 가부시키가이샤 반도체기판의 제조방법 및 반도체기판

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