WO1998042010A1 - Galettes silicium sur isolant utilisant un implant a haute energie - Google Patents

Galettes silicium sur isolant utilisant un implant a haute energie Download PDF

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Publication number
WO1998042010A1
WO1998042010A1 PCT/US1998/004695 US9804695W WO9842010A1 WO 1998042010 A1 WO1998042010 A1 WO 1998042010A1 US 9804695 W US9804695 W US 9804695W WO 9842010 A1 WO9842010 A1 WO 9842010A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
accordance
type
stop layer
etch stop
Prior art date
Application number
PCT/US1998/004695
Other languages
English (en)
Inventor
John O. Borland
Original Assignee
Genus, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genus, Inc. filed Critical Genus, Inc.
Publication of WO1998042010A1 publication Critical patent/WO1998042010A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Definitions

  • the present invention relates to Silicon-On-Insulator (SOI) wafers, and to a method of manufacture thereof.
  • SOI Silicon-On-Insulator
  • Silicon-On-Insulator (SOI) technology is a well-known technology which has been disclosed various publications, such as the article by Subramanian S. Iyer, Thomas 0. Sedgwick, Philip M. Pitner and Manu J. Tejwani entitled "Silicon-on- Insulator Technology - Outlook for Bonded Wafers" appearing at pages 391-407 of J. Electrochem. Soc . , PV 94-10, 1994.
  • SOI Silicon-On-Insulator
  • the current method starts with a p- wafer 20 such as that shown in Fig. 1.
  • a blanket p+ etch stop layer is created in the p- wafer by one of the following two methods.
  • a thin p+ epilayer 24 (I0 19 /cm 3 ) is grown on the p- wafer 20.
  • a p+ layer 24 is produced on the p- wafer 20 by low energy/high dose boron implantation at less than 100 keV and I0 14 -l0 15 /cm 2 .
  • step 2 of the current method shown in Fig.
  • a buried p+ layer 24 and high quality SOI surface layer 26 is formed by growing a high quality p-epilayer 26 over the p+ etch stop layer 24 without autodoping and misfit dislocation.
  • the present invention provides alternatives to these steps 1 and 2.
  • step 3 wafer bonding, shown in Fig. 5
  • the wafer 20 with the buried p+ layer 24 is placed in direct contact with a wafer 30 having an SOI insulating layer 32 of Si0 2 , and annealing is performed to provide bonding.
  • the wafer 20 with the buried p+ layer 24 may have native oxide at its surface; if not, an oxide can be grown there.
  • step 4 shown in Fig. 6, a thin SOI layer 26 is formed by selective chemical etching and polishing the back of the p-wafer 20 to the p+ buried layer 24 and then to the p- SOI layer 26.
  • reference numerals 20, 24, 26 and 28 correspond to the "seed wafer" of Figs. 1 and 3 of said U.S. Patent No. 5,103,681; and reference numerals 30 and 32 correspond to the "handle wafer” of Figs. 2 and 3 of said U.S.
  • numeral 20 designates a silicon wafer, p- or n- doped
  • numeral 22 designates an optional silicon buffer layer
  • numeral 24 designates an etch stop layer
  • 26 designates a silicon cap layer (wherein the device to be fabricated is formed)
  • 28 designates the insulating layer which may be a native oxide or which may be grown.
  • Numeral 30 designates the oxide wafer (i.e. the "handle wafer") and numeral 32 designates the SOI insulating layer of Si0 2 _
  • p- means a p-type impurity concentration of I0 14 /cm 3 or less; the term “p” means a p-type impurity concentration of between I0 15 /cm 3 and I0 16 /cm 3 ; the term “p+” means a p-type impurity concentration of between I0 17 /cm 3 and I0 18 /cm 3 ; and the term “p++” means a p-type impurity concentration of I0 19 /cm 3 or more.
  • the present invention comprehends a new method of forming a p+ buried layer SOI wafer which eliminates the single epi growth of a p- surface layer over a p+ blanket implant according to the second of the aforementioned current methods, and eliminates the double epi growth of a first p+ epilayer and then a p- epilayer according to the first of the aforementioned current methods .
  • the present invention achieves a high-quality epi -equivalent bulk Czochralski (Cz) wafer SOI layer by using low oxygen wafer or by optimized denuding (such as with Ar, N 2 , H 2 or 0 2 ) .
  • Fig. 1 is a diagrammatic view of a p- wafer used in carrying out the current method
  • Fig. 2 is a diagram showing one manner of carrying out step 1 of the current method
  • Fig. 3 is a diagram showing another manner of carrying out step 1 of the current method
  • Fig. 4 is a diagram showing step 2 of the current method
  • Fig. 5 is a diagram showing step 3 of the current method
  • Fig. 6 is a diagram showing step 4 of the current method
  • Fig. 7 is a diagram showing step 1 of the method ot the present invention.
  • Fig. 8 is a diagram showing step 2 of the method of the present invention.
  • a high quality top surface region is formed on the p- wafer by denuding the wafer at 1000°C - 1200° C in an ambient of Ar, H 2 , N 2 or 0 2 to deplete the surface of oxygen and microdefects .
  • Suitable denuding methods are disclosed, for example, in J.O.Borland, Semiconductor International April 1989 pages 144-148 and May 1989 pages 154- 157 and references cited therein, such as J.O. Borland, J.Electrochem.Soc. , PV 83-9, 1983, p. 194; J.O.Borland, J. Electrochem. Soc .
  • a buried p+ etch stop layer is then formed by High Energy (0.2 to 2 MeV) implantation of boron at high dose (10 14 to I0 15 /cm 2 to form a uniform buried p+ layer 0.5 to 3 microns deep with a peak concentration of 10 19 - 10 20 /cm 3 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)

Abstract

Dans la production de substrats silicium sur isolant (SOI) destinés à la fabrication de circuits CMOS par l'approche de liaison et de gravure en retrait, on utilise une haute énergie à ions d'impuretés de couverture pour produire la couche d'arrêt de gravure (24).
PCT/US1998/004695 1997-03-17 1998-03-11 Galettes silicium sur isolant utilisant un implant a haute energie WO1998042010A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81892097A 1997-03-17 1997-03-17
US08/818,920 1997-03-17

Publications (1)

Publication Number Publication Date
WO1998042010A1 true WO1998042010A1 (fr) 1998-09-24

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Family Applications (1)

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PCT/US1998/004695 WO1998042010A1 (fr) 1997-03-17 1998-03-11 Galettes silicium sur isolant utilisant un implant a haute energie

Country Status (1)

Country Link
WO (1) WO1998042010A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004010505A1 (fr) * 2002-07-18 2004-01-29 Shin-Etsu Handotai Co.,Ltd. Plaquette de silicium sur isolant et son procede de production
WO2007012290A1 (fr) * 2005-07-29 2007-02-01 Shanghai Simgui Technology Co., Ltd Procede de production de silicium sur isolant
US8080482B2 (en) 2006-01-31 2011-12-20 Memc Electronic Materials, Inc. Methods for preparing a semiconductor structure for use in backside illumination applications

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4548654A (en) * 1983-06-03 1985-10-22 Motorola, Inc. Surface denuding of silicon wafer
US4666532A (en) * 1984-05-04 1987-05-19 Monsanto Company Denuding silicon substrates with oxygen and halogen
JPH01226167A (ja) * 1988-03-07 1989-09-08 Seiko Epson Corp 半導体装置基板の製造方法
US4897362A (en) * 1987-09-02 1990-01-30 Harris Corporation Double epitaxial method of fabricating semiconductor devices on bonded wafers
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5147808A (en) * 1988-11-02 1992-09-15 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US5462883A (en) * 1991-06-28 1995-10-31 International Business Machines Corporation Method of fabricating defect-free silicon on an insulating substrate

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4548654A (en) * 1983-06-03 1985-10-22 Motorola, Inc. Surface denuding of silicon wafer
US4666532A (en) * 1984-05-04 1987-05-19 Monsanto Company Denuding silicon substrates with oxygen and halogen
US4897362A (en) * 1987-09-02 1990-01-30 Harris Corporation Double epitaxial method of fabricating semiconductor devices on bonded wafers
JPH01226167A (ja) * 1988-03-07 1989-09-08 Seiko Epson Corp 半導体装置基板の製造方法
US5147808A (en) * 1988-11-02 1992-09-15 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5462883A (en) * 1991-06-28 1995-10-31 International Business Machines Corporation Method of fabricating defect-free silicon on an insulating substrate
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004010505A1 (fr) * 2002-07-18 2004-01-29 Shin-Etsu Handotai Co.,Ltd. Plaquette de silicium sur isolant et son procede de production
WO2007012290A1 (fr) * 2005-07-29 2007-02-01 Shanghai Simgui Technology Co., Ltd Procede de production de silicium sur isolant
US8080482B2 (en) 2006-01-31 2011-12-20 Memc Electronic Materials, Inc. Methods for preparing a semiconductor structure for use in backside illumination applications
US8865601B2 (en) 2006-01-31 2014-10-21 Sunedison Semiconductor Limited (Uen201334164H) Methods for preparing a semiconductor wafer with high thermal conductivity

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