WO2003098692A1 - Circuit integre avec protection par ingenierie inverse - Google Patents

Circuit integre avec protection par ingenierie inverse Download PDF

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Publication number
WO2003098692A1
WO2003098692A1 PCT/US2003/014058 US0314058W WO03098692A1 WO 2003098692 A1 WO2003098692 A1 WO 2003098692A1 US 0314058 W US0314058 W US 0314058W WO 03098692 A1 WO03098692 A1 WO 03098692A1
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WIPO (PCT)
Prior art keywords
layer
active region
metal
polysilicon
circuit structure
Prior art date
Application number
PCT/US2003/014058
Other languages
English (en)
Inventor
Lap-Wai Chow
Jr. William M. Clark
James P. Baukus
Original Assignee
Hrl Laboratories, Llc
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hrl Laboratories, Llc, Raytheon Company filed Critical Hrl Laboratories, Llc
Priority to GB0427115A priority Critical patent/GB2405531B/en
Priority to AU2003245265A priority patent/AU2003245265A1/en
Priority to JP2004506086A priority patent/JP4729303B2/ja
Publication of WO2003098692A1 publication Critical patent/WO2003098692A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to integrated circuits and semiconductor devices (ICs) in general and their methods of manufacture wherein the integrated circuits and semiconductor devices employ camouflaging techniques which make it difficult for a reverse engineer to discern how the semiconductor device is manufactured.
  • United States Patent Nos. 5,866,933; 5,973,375 and 6,294,816 teach how transistors in a CMOS circuit are connected by implanted (and therefore hidden and buried) lines between the transistors by modifying the p+ and n+ source/drain masks. These implanted interconnections are used to make 3-input AND and 3-input OR circuits look substantially identical to the reverse engineer. Also, buried interconnects force the reverse engineer to examine the IC in greater depth to try to figure out the connectivity between transistors and hence their function.
  • United States Patent Nos. 5,866,933; 5,973,375 and 6,294,816 teach how transistors in a CMOS circuit are connected by implanted (and therefore hidden and buried) lines between the transistors by modifying the p+ and n+ source/drain masks. These implanted interconnections are used to make 3-input AND and 3-input OR circuits look substantially identical to the reverse engineer. Also, buried interconnects force the reverse engineer to examine the IC in greater
  • 5,783,846; 5,930,663 and 6,064,110 teach a further modification in the source/drain implant masks so that the implanted connecting lines between transistors have a gap therein, the gap having a length approximating the minimum feature size of the CMOS technology being used. If this gap is "filled” with one kind of implant, the line conducts; but if it is "filled” with another kind of implant, the line does not conduct. The intentional gaps are called “channel blocks.” The reverse engineer is forced to determine connectivity on the basis of resolving the implant type at the minimum feature size of the CMOS process being used.
  • United States Patent No. 6,117,762 teaches a method and an apparatus for protecting semiconductor integrated circuits from reverse engineering.
  • Semiconductor active areas are formed on a substrate, and a suicide layer is formed over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting at least one active area with another area through the suicide area formed on the selected substrate area.
  • integrated circuits can include read only memories and/or EEPROMs into which software, in the form of firmware, is encoded.
  • integrated circuits are often used in applications involving the encryption of information, and therefore in order to keep such information confidential, it can be desirable to keep such devices from being reverse engineered.
  • One technique is to make the connections between transistors difficult to determine forcing the reverse engineer to carefully analyze each transistor (in particular, each CMOS transistor pair for CMOS devices). By camouflaging the connections between transistors, the reverse engineer is unable to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to carefully analyze each transistor in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
  • gate connections may utilize the polysilicon layer (typically the first polysilicon layer in a process having two or more polysilicon layers) and the reverse engineer, knowing that such gate contacts are typically the input to transistors and hence to a standard circuit, would look for these contacts.
  • the source and drain contacts are made to the substrate via metal interconnect.
  • One way in which the reverse engineer might work would be to look for cell boundaries by means of looking for silicon-to-gate poly metal lines as these suggest the possibilities for contacts between the output (the drain contact) from one transistor cell into the input (the gate contact) of a next transistor cell.
  • the reverse engineer can define cell boundaries by these silicon-gate poly lines. Then by noting the cell boundaries, the reverse engineer can find the cell characteristics (for example, size and number of transistors) and from this make reasonable assumptions as to the cell's function. This information can then be stored in a database for automatic classification of other similar cells.
  • Figure 1 is a plan view of a semiconductor device.
  • Figures 1 A, IB and IC are cross-sectional views of the semiconductor device shown in plan view in Figure 1.
  • a typical drain or source contact is shown in Figure 1A, while a typical gate contact is shown in Figure IB.
  • the drain, source and gate regions are formed on a semiconductor substrate, such as silicon substrate 10, and have active regions 12, 16, 18, as shown in Figure IC, formed therein, typically by implantation of a suitable dopant.
  • Field oxide (FOX) 20 is used to help isolate one semiconductor device from another, in the usual fashion.
  • FOX Field oxide
  • the drain contact structure as shown in Figure 1A, has a conventional suicide layer 26-1 formed over its active region 18.
  • a refractive metal contact 30 and plug 31 combination is formed on the suicide layer 26-1.
  • Suicide layer 26-1 provides a surface for a refractive metal gate contact 30 and plug 31 combination, the metal contact frequently including a plug of refractive metal 31 which extends through an opening in a dielectric layer 29, which may be deposited Si ⁇ 2-
  • the refractive metal gate contact 30 and metal plug 31 combination makes contact with the suicide layer 26-1.
  • the source structure is similar to the drain structure depicted in Figure 1 A, where the active region 18 is replaced by active region 16.
  • the gate structure has a relatively thin gate oxide layer 22 which is covered by a layer of polysilicon 24-1, which in turn is covered by a suicide layer 26-1 (suicide layer 26-1 is traditionally referred to as a "salicide" layer when used with a polysilicon layer 24-1 as is the case here).
  • Suicide layer 26-1 provides a surface for a refractive metal gate contact 30, the metal contact frequently including a plug of refractive metal 31 which extends through an opening in a dielectric layer 29, which may be deposited Si ⁇ 2- The metal plug 31 makes contact with the suicide layer 26-1.
  • Figure IC is a cross-sectional view through the active areas 16, 18 and gate area 12 of a semiconductor device.
  • the sidewall spacers 21 provide for the separation of the gate area 12 and active regions 16, 18 during processing.
  • the remaining details of Figure IC are the same as those found in Figures 1 A and IB. Those skilled in the art will appreciate other fabrication details are omitted from the drawings since their use is well known in the art.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • EEPROM electrically erasable programmable read-only memory
  • Such a process is currently used by many commercial IC chip manufacturers, especially smart card chip manufacturers.
  • the double-polysilicon (or simply double poly) process can be used to make a variety of devices, including CMOS transistor pairs, floating gate structures and even bipolar transistors. See, for example, US Patent No. 4,784,966 to Chen.
  • a double-polysilicon CMOS process also supports the manufacture of EEPROMs, which are commonly used in applications such as smart card chips and the like.
  • the present invention provides a camouflaged circuit structure, comprising: a semiconductor substrate; an implanted region in said substrate; a metal layer which is associated with said implanted region and which appears, in plan view, to be electrically coupled to said implanted region; and a dielectric layer disposed between said implanted region and said metal layer to thereby insulate said metal layer from said implanted region, the dielectric layer having dimensions such that when viewed in said plan view, said dielectric layer is at least partially hidden by a feature of the circuit structure.
  • a camouflaged circuit structure comprising: a semiconductor substrate; an active region in said substrate; a conductive layer which is associated with said active region and which appears, in plan view, to be arranged to influence conduction through said active region by an application of control voltages thereto; a control electrode which is associated with said conductive layer and which appears, in plan view, to be electrically connected to said conductive layer; and at least one dielectric layer disposed between said conductive layer and said control electrode for intentionally keeping said conductive layer from influencing conduction through said active region in response to an application of control voltages to said control electrode.
  • Another aspect of the present invention provides a method of deterring a reverse engineer comprising the steps of: associating at least one conductive contact with an active area; and preventing electrical conduction between said at least one conductive contact and said active area by inserting an intervening insulating layer.
  • a pseudo-transistor comprising: an active region disposed in a substrate; an insulating, non-electrically conductive layer disposed over at least a portion of said active region; a polysilicon layer disposed over at least a portion of said insulating, non-electrically conductive layer disposed over at least a portion of said active region, the insulating, non-electrically conductive layer electrically isolating the polysilicon layer from the active region; and a metal layer in electrical communication with said polysilicon layer and electrically isolated from the active region, the insulating, non-electrically conductive layer, the polysilicon layer and the the metal layer each having dimensions such that when viewed in a plan view, the metal layer appears to be in electrical communication with the active region.
  • a non-operational semiconductor gate contact comprising: a metal layer; a first polysilicon layer; a second polysilicon layer disposed at least between said metal layer and said first polysilicon layer; and an insulating, non-conductive layer disposed at least between said first polysilicon layer and said second polysilicon layer.
  • Another aspect of the present invention provides a method for manufacturing a pseudo- transistor comprising the steps of: implanting an active region in a substrate; placing a dielectric layer over at least a portion of said active region; and disposing a metal layer over said dielectric layer, wherein said dielectric layer prevents an electrical connection between said active region and said metal layer.
  • Another aspect of the present invention provides a method for confusing a reverse engineer comprising the steps of: implanting an active region in a substrate; associating a conductive layer with said active region; disposing at a dielectric layer over said conductive layer; and providing a control electrode, wherein said dielectric layer prevents said conductive layer from influencing conduction through said active region in response to an application of control voltages to said control electrode.
  • the present invention is compatible with the standard double-polysilicon CMOS process in which at least one of the polysilicon layers (typically the second or upper polysilicon layer) is deposited after active area implants, i.e., after the source and drain implants.
  • the prior art process is modified by placing a dielectric layer over an apparent contact area so as to defeat what would otherwise appear as a standard metal contact. This can be done in at least the following two contexts:
  • the second polysilicon area and oxide combination are deposited over a source or drain contact region to which a metal contact will be subsequently applied.
  • the metal contact is not electrically connected to the underlying source or drain region, and therefore that which appears to be a contact does not function as one.
  • the metal contact appears to be a normal metal contact and therefore the reverse engineer will assume that the transistor associated therewith is operable.
  • a structure that appears to the reverse engineer to be a transistor can be made to have a different function within a circuit than it appears to have by (i) rendering its gate non-functional, or (ii) rendering its drain contact non-functional or (iii) rendering its source contact non-functional or (iv) any combination of the foregoing.
  • the reverse engineer is apt to assume that each pseudo- transistor is a proper transistor when trying to copy the original integrated circuit, causing their copied circuit to function incorrectly. The true functionality of the circuit is hidden in the circuits in which the pseudo-transistors are used.
  • the reverse engineer may detect the techniques disclosed herein which render the pseudo-transistors inoperable.
  • the techniques which will be needed to detect the use of the present invention will be sufficiently time consuming to deter the reverse engineer.
  • a complex integrated circuit may comprise millions of CMOS transistors and if the reverse engineer must carefully analyze each CMOS transistor pair in order to determine whether or not the present invention has been used to disguise each CMOS transistor, the effort involved in reverse engineering such an integrated circuit will be tremendous.
  • the disclosed techniques can be utilized to render a circuit non-functional. However, it is believed that the disclosed techniques are better used in applications where, instead of rendering a circuit non-functional, the circuit still functions, but functions in an unintended way.
  • the reverse engineer ends up with a copy which "seems" to work, but does not really work to produce a useful or desired result.
  • Figure 1 is a plan view of a semiconductor device found in Figures 1A, IB and IC;
  • Figures 1A, IB and IC are side elevational views of a metal contact for an active area (see Figure 1A) and a metal contact for a gate region (see Figure IB) and cross section through the active areas and gate area (see Figure IC);
  • Figure 2 is a cross-sectional view through a gate region with conventional double poly processing;
  • Figure 3 is a plan view of a semiconductor device which is also depicted in Figures 3A, 3B and 3C;
  • Figure 3A is a side-sectional view along line 3A-3A depicted in Figure 3 through a drain or source contact of a CMOS transistor employing a silicide/salicide layer, wherein a layer of oxide is utilized to render the associated contact inoperable;
  • Figure 3B is a side-sectional view along line 3B-3B depicted in Figure 3 which is adjacent the gate region and shows how the silicide/salicide layer and the layer of oxide adjacent the gate region render the gate contact inoperable;
  • Figure 3C is a cross-sectional view along line 3C-3C depicted in Figure 3 depicting the layers through the source, gate and drain regions.
  • Figure 3 is a plan view of the semiconductor device which appears to be a field effect transistor (FET). However, as can be seen from the cross-sectional views depicted in Figures 3A, 3B, and 3C the semiconductor device is a pseudo-transistor.
  • Figure 3A depicts how the contact depicted in Figure 1A can be intentionally "broken” by the present invention to form the pseudo- transistor.
  • Figure 3B shows how the gate structure depicted in Figure IB can be intentionally “broken” by the present invention to form the pseudo-transistor.
  • Figure 3C is a cross-sectional of both the gate region 12 and active regions 16, 18, the contact to the active region 18 being intentionally “broken” by the present invention to form the pseudo-transistor.
  • the pseudo-transistor may also be a depletion mode device.
  • the gate, source or drain contacts are intentionally “broken” by the present invention.
  • the gate contact is "broken”
  • the device will be “ON” when a nominal voltage is applied to the control electrode.
  • the source or drain contact is "broken”
  • the pseudo- depletion mode transistor will essentially be "OFF” for a nominal voltage applied to the control electrode.
  • Figure 2 shows typical process dimensions used in modern double poly semiconductor processing.
  • the double-poly process preferably includes two layers of polysilicon 24-1, 24-2 and may also have two layers of salicide 26-1, 26-2.
  • the thicknesses represented are preferable thicknesses.
  • Double polysilicon processing may be used to arrive at the structures shown in Figures 3, 3A, 3B and 3C.
  • One skilled in the art will appreciate that the structures shown in Figures 3, 3A, 3B and 3C are not limited to the thickness dimensions shown in Figure 2.
  • Figure 3 shows a pseudo-FET transistor in plan view, but those skilled in the art will appreciate that the metal contact of a bipolar transistor is very similar to the source/drain contact depicted.
  • Figure 3A is a side elevation view of the pseudo-transistor in connection with what appears to the reverse engineer (viewing from the top, see Figure 3) as an active area metal layer 30, 31 of a CMOS FET.
  • the device could be a vertical bipolar transistor in which case the metal layer 30, 31 that the reverse engineer sees could be an emitter contact.
  • an active region 18 may be formed in a conventional manner using field oxide 20 as the region boundary.
  • the active region 18 is implanted through gate oxide 22 (see Fig 3C), which is later stripped away from over the active regions and optionally replaced with the suicide metal which is then sintered, producing a suicide layer 26-1.
  • a dielectric layer 28 is deposited.
  • the dielectric layer is a silicon dioxide (Si ⁇ 2) layer 28.
  • a polysilicon layer 24-2 may be deposited over the silicon dioxide layer 28.
  • Polysilicon layer 24-2 is preferably the second polysilicon layer in a double polysilicon process.
  • Optional suicide layer 26-2 is then formed over the polysilicon layer 24-2.
  • a second silicon dioxide (Si ⁇ 2) layer 29 is deposited and etched to allow a metal layer, including metal plug 31 and metal contact 30 to be formed over the optional silicide layer 26-2 or in contact with polysilicon layer 24-2 (if no silicide layer 26-2 is utilized).
  • the oxide layer 28 and oxide layer 29 are preferably comprised of the same material (possibly with different densities) and as such are indistinguishable from each othei to the reverse engineer when placed on top of each other.
  • a cross-section of the polysilicon layer 24-2 in a direction parallel to the major surface 11 of the semiconductor substrate 10 is preferably designed to be essentially the same size, within process alignment tolerances, as a cross-section of the metal plug 31 taken in the same direction.
  • the polysilicon layer 24-2 is at least partially hidden by the metal plug 31.
  • the polysilicon layer 24-2 is depicted as being much larger than metal plug 31; however, these figures are exaggerated simply for clarity.
  • the polysilicon layer 24-2 is designed to ensure that a cross-section of metal plug 31 is aligned with a cross-section of polysilicon layer 24-2, or a cross-section of optional silicide layer 26-2 if used, yet small enough to be very difficult to view under a microscope. Further, the bottom of metal plug 31 is preferably completely in contact with the polysilicon layer 24-2, or optional silicide layer 26-2 if used.
  • process alignment tolerances vary by process. For example, for a 0.5 ⁇ m process, typical alignment tolerances are in the range from 0.1 ⁇ m to 0.15 ⁇ m.
  • the reverse engineer cannot easily obtain an elevation view such as those shown in Figures 2, 3A, 3B or 3C. In fact, the typical manner in which the reverse engineer would obtain the elevation views would be via individual cross-sectional scanning electron micrographs taken at each possible contact or non-contact. The procedure of taking micrographs at each possible contact or non-contact is prohibitively time consuming and expensive.
  • the reverse engineer when looking from the top, will see the top of the metal contact 30, see Figure 3.
  • the contact- defeating layer of oxide 28 with polysilicon layer 24-2 and optional silicide layer 26-2 will be at least partially hidden by a feature of the circuit structure, i.e. metal contact 30 and metal plug 31.
  • the reverse engineering process usually involves delayering the semiconductor device to remove the layers down to the silicon substrate 10. and then viewing the semiconductor device from a direction normal to the major surface 11 of the silicon substrate 10. During this process, the reverse engineer will remove the traces of the oxide layer 28 which is used in the present invention to disable the contact.
  • a cross-section of polysilicon layer 24-2 is preferably essentially the same size, within process alignment tolerances, as a cross-section of metal plug 31.
  • the oxide layers 28, 29 are practically transparent, and the thicknesses of the optional silicide layer 26-2 and the polysilicon layer 24-2 are small.
  • a typical thickness of the optional silicide layer 26-2 is 100-200 angstroms, and a typical thickness of the polysilicon layer 24-2 is 2500-3500 angstroms.
  • the reverse engineer may be further confused when looking at the device once the metal plug 31 has been removed. Upon viewing the shiny reside left by the silicide layer 26-2, the reverse engineer will incorrectly assume that the shiny reside is left over by the metal plug 31. Thus, the reverse engineer will again incorrectly assume that the contact was operational.
  • Figure 3B is a side elevation view of a gate contact of the psuedo- transistor of Figure 3.
  • the view of Figure 3B which is taken along section line 3B-3B, is through a gate oxide layer 22, through a first polysilicon layer 24-1 and through a first a silicide layer 26-1 which are formed over the field oxide region 20 and gate region 12 in the semiconductor substrate 10 (typically silicon) between active regions 16 and 18 (see Figure 3C).
  • the first polysilicon layer 24-1 would act as a conductive layer which influences conduction through the gate region 12 by an application of control voltages, if this device functioned normally.
  • Active regions 16, 18 and 12, gate oxide 22, the first polysilicon layer 24-1, and the first silicide layer 26-1 are formed using conventional processing techniques.
  • a control electrode formed by metal layer 30, 31 would be in contact with the layer of silicide layer 26-1 over field oxide 20.
  • the silicide layer 26-1 would then act as a control layer for a normally functioning device.
  • at least one dielectric layer, for example a layer of oxide 28, is deposited.
  • a second polysilicon layer 24-2 and an optional second silicide layer 26-2 are deposited over the oxide layer 28.
  • the layer of silicide 26-2 depicted between the polysilicon layer 24-2 and metal plug 31 may be omitted in some fabrication processes, since some double-polysilicon processing techniques utilize only one layer of silicide (when such processing techniques are used only one layer of silicide 26-1 or 26-2 would be used). In either case, the normal functioning of the gate is inhibited by the layer of oxide 28.
  • a cross-section of the second polysilicon layer 24-2 in a direction parallel to the normal surface 11 of the semiconductor substrate 10 is preferably essentially the same size, within process alignment tolerances, as a cross-section of metal plug 31 taken in the same direction. As such, the second polysilicon layer 24-2 is partially hidden by metal plug 31.
  • the polysilicon layer 24-2 is depicted as being much larger than metal plug 31 ; however, these figures are exaggerated simply for clarity.
  • the polysilicon layer 24-2 is designed to ensure that the cross-section of metal plug 31 is completely aligned with the cross- section of polysilicon layer 24-2, or a cross-section of optional silicide layer 26-2 if used, yet small enough to be very difficult to view under a microscope. Further, the bottom of metal plug 31 is preferably completely in contact with the polysilicon layer 24-2, or the optional silicide layer 26-2 if used.
  • process alignment tolerances vary by process. For example, for a 0.5 ⁇ m process, typical alignment tolerances are in the range from 0.1 ⁇ to 0.15 ⁇ m.
  • the added oxide layer 28 and polysilicon layer 24-2 are placed such that they occur at the normal place for the metal to polysilicon contact to occur as seen from a plan view.
  • the placement provides for the metal layer 30, 31 to at least partially hide the added oxide layer 28 and/or polysilicon layer 24-2, so that the layout appears normal to the reverse engineer.
  • the reverse engineer will etch off the metal layer 30, 31 and see the polysilicon layer 24-2 and possible reside from optional silicide layer 26-2, if used.
  • the reverse engineer may incorrectly assume that the shiny reside is from the metal plug 31.
  • a reverse engineer would not have any reason to believe that the contact was not being made to polysilicon layer 24-1 or optional silicide layer 26-1.
  • oxide layer 28 and polysilicon layer 26-2 are not clearly seen when viewing the contact from a direction normal to the major surface 11 of the silicon substrate 10, and thus the reverse engineer will conclude he or she is seeing a normal, functional polysilicon gate FET transistor.
  • the reverse engineering protection techniques of Figure 3A, Figure 3B and/or Figure 3C need only be used sparingly, but are preferably used in combination with other reverse engineering techniques such as those discussed above under the subtitle "Related Art.”
  • the basic object of these related techniques and the techniques disclosed herein is to make it so time consuming to figure out how a circuit is implemented (so that it can be successfully replicated), that the reverse engineer is thwarted in his or her endeavors.
  • the pseudo-transistors described herein and depicted in Figures 3A, 3B and 3C to camouflage the circuit. Therefore, unless the reverse engineer is able to determine these pseudo-transistors, the resulting circuit determined by the reverse engineer will be incorrect.
  • the pseudo-transistors are preferably used not to completely disable a multiple transistor circuit in which they are used, but rather to cause the circuit to function in an unexpected or non-intuitive manner. For example, what appears to be an OR gate to the reverse engineer might really function as an AND gate. Or what appears as an inverting input might really be non-inverting. The possibilities are almost endless and are almost sure to cause the reverse engineer so much grief that he or she gives up as opposed to pressing forward to discover how to reverse engineer the integrated circuit device on which these techniques are utilized.
  • the reverse engineer when the reverse engineer etches away the metal 30, 31, he or she should preferably "see” the normally expected layer whether or not a contact is blocked according to the present invention. Thus, if the reverse engineer expects to see silicide after etching away metal, that is what he or she should see even when the contact is blocked. If he or she expects to see polysilicon after etching away metal, that is what he or she should see even when the contact is blocked.
  • silicide layers 26-1 and 26-2 are not required to be placed in the gate region. In modern semiconductor manufacturing processes, particularly where the feature size is less than 0.5 micrometers, a silicide layer is typically used to improve conductivity. However, the present invention is directed toward giving the appearance of a functioning transistor device to the reverse engineer where the contact is actually disabled. Since conductivity is not an issue, and in fact conductivity is prevented, silicide layers 26-1 and 26-2 are not required to be placed in the gate region when the contact is to be broken. However, silicide layers 26-1 and 26-2 may be placed over the gate region to simplify the number of masks required and thus the semiconductor manufacturing process and to further mislead the reverse engineer by the shiny residue which it leaves behind during some reverse engineering processes.
  • the present disclosure describes technique and structures for camouflaging an integrated circuit structure.
  • the integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses.
  • a layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.

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  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Non-Volatile Memory (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une technique et des structures de camouflage d'une structure de circuit intégré constituée d'une pluralité de couches de matériaux présentant des profils et des épaisseurs calibrés. Une couche d'un matériau diélectrique d'épaisseur calibrée est disposée parmi ladite pluralité de couches afin de rendre la structure de circuit intégré volontairement inexploitable.
PCT/US2003/014058 2002-05-14 2003-05-06 Circuit integre avec protection par ingenierie inverse WO2003098692A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0427115A GB2405531B (en) 2002-05-14 2003-05-06 Integrated circuit with reverse engineering protection
AU2003245265A AU2003245265A1 (en) 2002-05-14 2003-05-06 Integrated circuit with reverse engineering protection
JP2004506086A JP4729303B2 (ja) 2002-05-14 2003-05-06 リバースエンジニアリングに対する防御を有する集積回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37815502P 2002-05-14 2002-05-14
US60/378,155 2002-05-14

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WO2003098692A1 true WO2003098692A1 (fr) 2003-11-27

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AU (1) AU2003245265A1 (fr)
GB (1) GB2405531B (fr)
TW (1) TWI226697B (fr)
WO (1) WO2003098692A1 (fr)

Cited By (3)

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WO2006013507A1 (fr) * 2004-07-26 2006-02-09 Koninklijke Philips Electronics N.V. Puce a couche de protection contre la lumiere
FR3069370A1 (fr) * 2017-07-21 2019-01-25 Stmicroelectronics (Rousset) Sas Circuit integre contenant une structure de leurre
KR20210002347A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 집적 회로 레이아웃, 집적 회로, 및 그 제조 방법

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WO1998057373A1 (fr) * 1997-06-13 1998-12-17 Inside Technologies Procede de fabrication d'un circuit integre et circuit integre realise selon ce procede
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EP1193758A1 (fr) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Contacts pour rendre difficile le déchiffrage
EP1202353A1 (fr) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. ROM programmé par masque et son procédé de fabrication

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EP0186855A2 (fr) * 1984-12-25 1986-07-09 Kabushiki Kaisha Toshiba Dispositif semi-conducteur de mémoire morte et méthode de fabrication
US5895241A (en) * 1997-03-28 1999-04-20 Lu; Tao Cheng Method for fabricating a cell structure for mask ROM
WO1998057373A1 (fr) * 1997-06-13 1998-12-17 Inside Technologies Procede de fabrication d'un circuit integre et circuit integre realise selon ce procede
EP1193758A1 (fr) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Contacts pour rendre difficile le déchiffrage
EP1202353A1 (fr) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. ROM programmé par masque et son procédé de fabrication

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006013507A1 (fr) * 2004-07-26 2006-02-09 Koninklijke Philips Electronics N.V. Puce a couche de protection contre la lumiere
FR3069370A1 (fr) * 2017-07-21 2019-01-25 Stmicroelectronics (Rousset) Sas Circuit integre contenant une structure de leurre
US10804222B2 (en) 2017-07-21 2020-10-13 STMicrolectronics (Rousset) SAS Integrated circuit containing a decoy structure formed by an electrically insulated silicide sector
US11581270B2 (en) 2017-07-21 2023-02-14 Stmicroelectronics (Rousset) Sas Integrated circuit containing a decoy structure
KR20210002347A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 집적 회로 레이아웃, 집적 회로, 및 그 제조 방법
US11257769B2 (en) 2019-06-28 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout, integrated circuit, and method for fabricating the same
KR102450061B1 (ko) * 2019-06-28 2022-09-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 집적 회로 레이아웃, 집적 회로, 및 그 제조 방법
US11817402B2 (en) 2019-06-28 2023-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout, integrated circuit, and method for fabricating the same

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TW200400611A (en) 2004-01-01
TWI226697B (en) 2005-01-11
GB2405531B (en) 2006-04-12
AU2003245265A1 (en) 2003-12-02
GB2405531A (en) 2005-03-02
JP2005526401A (ja) 2005-09-02
JP4729303B2 (ja) 2011-07-20
GB0427115D0 (en) 2005-01-12

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