WO2003081681A1 - Element a semi-conducteurs et procede de fabrication de ce dernier - Google Patents

Element a semi-conducteurs et procede de fabrication de ce dernier Download PDF

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Publication number
WO2003081681A1
WO2003081681A1 PCT/JP2003/003181 JP0303181W WO03081681A1 WO 2003081681 A1 WO2003081681 A1 WO 2003081681A1 JP 0303181 W JP0303181 W JP 0303181W WO 03081681 A1 WO03081681 A1 WO 03081681A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor region
region
semiconductor
type region
junction
Prior art date
Application number
PCT/JP2003/003181
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English (en)
Japanese (ja)
Inventor
Jun Tateya
Original Assignee
Sanken Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Priority to JP2003579289A priority Critical patent/JP4247674B2/ja
Publication of WO2003081681A1 publication Critical patent/WO2003081681A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention belongs to a semiconductor device, in particular, a semiconductor device having a stable withstand voltage and a method of manufacturing the same.
  • the P type impurity source is diffused into the N 1 type region after forming the protective film, so the lateral diffusion causes the end of the PN junction region between the protective film and the N-type region. Since the part enters and the end part is not exposed, it is hardly affected by deposits, and the withstand voltage fluctuation of the diode hardly occurs.
  • the diode with a planar structure has a lower breakdown voltage and a higher breakdown voltage than the diode. The value can not be achieved.
  • there is also a problem that element design is difficult because it is difficult to obtain the withstand voltage theoretically calculated.
  • an object of the present invention is to provide a semiconductor device having a stable breakdown voltage without fluctuation in breakdown voltage and a method of manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which are close to a theoretical breakdown voltage value, can stably obtain a desired breakdown voltage, and can be easily designed. Disclosure of the invention
  • a semiconductor device comprises a first semiconductor region (1) and a first semiconductor region (1) having different conductivity types and disposed opposite to the first semiconductor region (1). Between the two semiconductor regions (2), the first semiconductor region (1) and the second semiconductor region (2), and the first semiconductor region (1) and the second semiconductor region (2) And a third semiconductor region (3) containing a lower concentration of impurities.
  • the first semiconductor region (1) and the second semiconductor region (2) having higher impurity concentration than any of the third semiconductor region (3) are directly bonded to each other and
  • An inner junction region (8) is formed to be an electric field concentration point (breakdown point).
  • the third semiconductor region (3) is annularly formed to surround the inner junction region (8) and is joined to the first semiconductor region (1) or the second semiconductor region (2).
  • FIG. 1 is a cross sectional view showing a diode according to a first embodiment of the present invention.
  • Figure 2 is a plan view of the diode shown in Figure 1
  • FIG. 3 is a process sectional view showing a method of manufacturing the diode shown in FIG.
  • FIG. 4 is a cross-sectional view showing a diode according to a second embodiment of the present invention.
  • FIG. 5 is a process sectional view showing a method of manufacturing the diode shown in FIG.
  • FIG. 6 is a cross-sectional view showing the diodes of the third, fourth and fifth embodiments according to the present invention.
  • FIG. 7 is a cross-sectional view of a diode showing the sixth and seventh embodiments according to the present invention
  • FIG. 8 is a cross-sectional view showing a diode of a conventional mesa structure.
  • FIG. 9 is a cross sectional view showing a conventional planar structure diode. BEST MODE FOR CARRYING OUT THE INVENTION
  • the diode 40 of the conventional mesa structure shown in FIG. 8 is a P + -type of the anode region formed on the N + -type region 21 and the N ⁇ -type region 23 of the force sort region and the N ⁇ -type region 23.
  • a semiconductor substrate 24 is formed of a region 22.
  • a pair of electrodes 25 and 26 are formed on the lower and upper surfaces of the semiconductor substrate 24.
  • the N-type region 23 contains impurities at a lower concentration than the N + -type region 21 and the P + -type region 22.
  • the PN junction region 28 between the P + -type region 22 and the N-type region 23 is formed in a planar shape, and diverges upward from the lower surface of the semiconductor substrate 24.
  • N-type region 1 and 2 showing the first embodiment of the present invention is formed opposite to the N + -type region 1 of the first semiconductor region and the N + -type region 1 and N + And P + -type region 2 of the second semiconductor region different in conductivity type, and disposed between N + -type region 1 and P + -type region 2 and N + -type and P + -type region 1, N-type region 3 of the third semiconductor region containing impurities lower than 2 is provided on semiconductor substrate 4, and a pair of electrodes 5 and 6 are provided on the outer surfaces of N + -type region 1 and P + -type region 2.
  • the zener diode is shown having a depression 6 a substantially in the center of the electrode 6.
  • the diode 50 of the conventional planar structure shown in FIG. 9 is a semiconductor having the N + -type region 2 1, the N ⁇ -type region 23 and the P + -type region 22 formed.
  • a PN junction region 38 between the P + -type and N-type regions 22 and 23 is formed on the upper surface of the semiconductor substrate 34 and covered with the protective film 37, and the PN junction Has a curved portion (suriferral portion) 3 8 b that is curved.
  • the entire top surface of the N-type region 23 is oxidized to form a protective film 37 of silicon dioxide (S i 0 2 ), and the protective film 37 is partially formed.
  • the end portion 38a is covered with the protective film 37 at all times during and after manufacture. It is possible to obtain a highly reliable diode without fluctuation in the withstand voltage due to a deposit.
  • the end 2 8 a of the PN junction region 8 is exposed, so the semiconductor substrate 2 4
  • the breakdown voltage is likely to fluctuate due to harmful substances such as sodium adhering to the side of the.
  • the end portion 2 8 a is covered with a protective film 27.
  • the impurity adheres to the end 2 8 a at the time of manufacturing before the formation of the protective film 27 to deteriorate the withstand voltage performance, and a highly reliable diode can not be obtained.
  • the diode 50 of the planar structure shown in FIG. 9 diffuses the P-type impurity source into the N-type region 23 after forming the protective film 37, the protective film 3 is formed by lateral diffusion. Since the end 3 8 a of the PN junction region 3 8 enters between the 7 and the N-type region 2 3 and the end 3 8 a is not exposed, it is hardly affected by the deposit, and the breakdown voltage of the diode is reduced. Is less likely to occur. However, since the local electric field concentration occurs and the critical electric field is easily reached as the curvature portion 3 8 b of the PN junction region 3 8 having a small curvature radius, the diode 50 of the planar structure of FIG. The breakdown voltage is lower than 8 diodes 40, and high breakdown voltage can not be achieved. In addition, there is also a problem that element design becomes difficult because it is difficult to obtain the theoretically calculated withstand voltage.
  • phosphorus is used as an impurity in the N + -type region 1 and the N-type region 3
  • boron is used as an impurity in the P + -type region 2.
  • a P + -type region 2 is formed on the N + -type region 1 with a substantially uniform thickness along the recess 7 formed on the upper surface of the diode 10. It has an inner bonding area 8 in which the flat bottom 2a and the curved inclined surface 2 of the area 2 and the dish-like recess 1a formed inside the N + type area 1 are directly PN-bonded.
  • the inner junction region 8 is formed by direct junction of the N + -type region 1 and the P + -type region 2 containing impurities higher in concentration than the N ⁇ -type region 3 to form a planar PN junction. A desired breakdown voltage calculated from the impurity concentration of P + -type region 2 is obtained.
  • the N-type region 3 forms, together with the P + -type region 2, an outer joint region 9 which is annularly formed surrounding the inner junction region 8 and is directly joined to the P + -type region 2.
  • the N-type region 3 has an annular inclined surface 3 a shown by a dotted line in FIG. 2 which is tapered toward the dished recess 1 a of the N + -type region 1 and a horizontal flat surface surrounding the inclined surface 3 a.
  • the flat surface 3 a and the flat surface 3 b have a PN junction with the P + -type region 2.
  • the outer bonding region 9 includes an outer end 9 a exposed from the side surface of the semiconductor substrate 4.
  • the depletion layer extending from the outer junction region 9 formed between the P + -type region 2 containing a high concentration of impurities and the N ⁇ -type region 3 containing a low concentration of impurities is formed widely. It is widely formed on the N-type region 3 side including. Therefore, when reverse bias is applied, Even if harmful substances adhere to the outer end 9a of the joint area 9, no breakdown voltage occurs.
  • the inclined surface 3a of the N-type region 3 and the inclined surface 2b of the P + -type region 2 are provided to increase the distance from the outer end portion 9a to the inner bonding region 8. Suppress pressure fluctuation due to attached material.
  • the semiconductor substrate 4 on which the N + -type region 1 containing high concentration of phosphorus is formed is prepared.
  • N-type region 3 is provided on N + -type region 1 by growing type region 3 or diffusing an impurity at the bottom of N-type region 3 to form N + -type region 1.
  • an epitaxial growth method is used to thinly stack an N-type region 3 containing low concentration impurities on the N + type region 1 containing high concentration impurities.
  • impurities can be doped in the growth process.
  • the semiconductor substrate 4 having the N + -type region 1 is disposed in a reaction container (not shown), and monosilane is applied at a high temperature of 1 100 to 1 200 0 C.
  • the inner surface of the N-type region 3 formed on the upper surface of the semiconductor substrate 4 is removed by etching to form a recess 7 reaching the N + -type region 1 as shown in FIG. 3 (b). As shown, it is formed in a circular shape inside the N-type region 3.
  • the lowermost part 7 a of the recess 7 may be provided either above or below the bonding surface between the N + -type region 1 and the N ⁇ -type region 3, but in the present embodiment, the P + -type region 2 is N + A lowermost portion 7 a is provided in the N + -type region 1 so as to be in contact with the mold region 1.
  • the side surface of the recess 7 is formed into a gently curved surface with a large radius of curvature, and the side surface of the recess 7 is surrounded by an N-type region 3 having a circular inner edge c.
  • the n + -type region 3 surrounding the recess 7 is diffused with a high concentration impurity such as boron different in conductivity type from the n + -type region 1 to form a p + -type region 2 containing high concentration boron as shown in FIG.
  • the second semiconductor region 2 and the N + -type region 1 are directly joined to form the inner junction region 8, and the P + -type region 2 and the N ⁇ -type region 3 are formed.
  • Direct bond to surround inner bond area 8 Forming an outer joint area 9.
  • the diffusion of boron is performed, for example, by a solid diffusion method or the like in which a solid thin film containing boron as an impurity source is formed in the N-type region 3 and the recess 7 and heat-treated.
  • a P + -type region 2 is formed along the N ⁇ -type region 3 and the recess 7, and the flat bottom surface 2 a of the P + -type region 2 along the bottom 7 a of the recess 7 is directly bonded to the N + -type region 1
  • N _ -type region 3 is disposed between N + -type region 1 and P + -type region 2 so as to surround inner junction region 8.
  • the inclined surface 3a and the flat surface 3b and the P + -type region 2 form a PN junction.
  • the thickness of the P + -type region 2 formed by diffusion is relatively deep in the N ⁇ -type region 3 because the impurity concentrations of the N + -type region 1 and the N ⁇ -type region 3 are different.
  • a slight step is generated between the inclined surface 2 b of the + type region 2 and the inclined surface 3 a of the N ⁇ type region 3.
  • the flat electrode 5 is connected to the lower surface of the N + -type region 1 and the electrode 6 having the recess 6 a is connected to the upper surface of the P + -type region 2 to form the diode 10 shown in FIG. .
  • a lead is connected to the pair of electrodes 5 and 6 and sealed with a resin or the like to provide a product.
  • the depletion layer is formed narrow in the inner junction region 8, and the depletion layer is formed wide in the outer junction region 9. Therefore, when a voltage in the reverse direction is applied to the diode 10 and the voltage exceeds the theoretical breakdown voltage determined by the impurity concentration of the N + -type and P + -type regions 1 and 2, etc. Current flow in the direction causes breakdown (breakdown).
  • the electric field is locally concentrated on the curvature portion 38 b and breakdown occurs in this portion, whereas in the present embodiment, N + having a high impurity concentration is used.
  • the semiconductor substrate is different from the mesa 40 of FIG. 8 in order to provide an inner junction region 8 which causes breakdown at a substantial center of the diode 10 apart from the exposed outer end 9a of the PN junction.
  • the breakdown voltage does not change because it is not affected by deposits on the side.
  • the present invention is not limited to the above embodiment, and various modifications can be made as shown in FIG. 4 to FIG. In the second to seventh embodiments shown in FIGS. 4 to 7, substantially the same effects as those of the first embodiment shown in FIG. 1 can be obtained.
  • the second embodiment shown in FIG. 4 is a diode in which the third semiconductor region 3 is formed thicker than in FIG. 1 and the cross section of the inclined surface 3 a of the third semiconductor region 3 is formed flat.
  • Indicates In the method of manufacturing the diode 20 shown in FIG. 4, first, phosphorus is diffused to the lower surface of the semiconductor substrate containing a low concentration of phosphorus, and as shown in FIG. 5 (a), N in the third semiconductor region is formed. The N + -type region 1 of the first semiconductor region containing a high concentration of phosphorus is partially formed at the bottom of the -type region 3. Next, as shown in FIG. 5 (b), the inside of the N-type region 3 is removed by etching to form a recess 7.
  • the lowermost portion 7 a of the recess 7 is formed above the bonding surface of the N + -type region 1 and the N ⁇ -type region 3.
  • boron of an impurity having a conductivity type different from that of the N + -type region 1 is diffused into the N 1 -type region 3 and the recess 7 to form the P + -type region 2 of the second semiconductor region containing a high concentration of impurities.
  • FIG. 5 (c) a flat inner junction region 8 where the N + region 1 and the P + region 2 are directly joined in the approximate center of the semiconductor substrate 14 and an inner junction region 8 are surrounded.
  • An outer junction region 9 is formed which joins between the P + and N ⁇ regions 2, 3. After the formation of the P + -type region 2, by forming the electrodes 5 and 6 in the same manner as the diode 10, the diode 20 shown in FIG. 4 is obtained.
  • the respective diodes 20a, 20b and 20c are shown in which the arrangement of the conductivity type of the semiconductor region is changed.
  • N + type, P + type and P type semiconductor regions are respectively formed in the first, second and third semiconductor regions 1, 2 and 3 of the diode 20a, and the first, second and third semiconductor regions of the diode 2O b are formed.
  • P + -type, N + -type and P ⁇ -type semiconductor regions are respectively formed, and the first, second and third semiconductor regions of the diode 20 c are formed.
  • the semiconductor regions of P + type, N + type and N- type are respectively formed in 1, 2 and 3.
  • the inner junction region 8 and the outer junction region 9 are formed in a substantially continuous planar shape, it is easy to increase the breakdown voltage. You can earn
  • the sixth embodiment shown in FIG. 7 (a) is different from the diode 20 of FIG. And a diode 3 0 a in which the shape of the outer junction region 9 between the third semiconductor regions 2 and 3 is modified. Further, in the seventh embodiment shown in FIG. 7 (b), the shape of the junction surface between the first and third semiconductor regions 1 and 3 is changed with respect to the diode 2 O b of FIG. 6 (b). Indicates the diode 3 0 b. Industrial applicability
  • the present invention it is possible to obtain an ideal breakdown voltage in which the breakdown voltage is close to the theoretical value, and to prevent breakdown due to the influence of deposits and the like, thereby suppressing fluctuation in breakdown voltage and providing a highly reliable semiconductor device. It can be formed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

Un élément à semi-conducteurs comprend une première zone de semi-conducteurs (1), une deuxième zone de semi-conducteurs (2) présentant un type de conductivité différent de celui de la première zone de semi-conducteurs (1) et une troisième zone de semi-conducteurs (3) placée entre la première zone de semi-conducteurs (1) et la deuxième zone de semi-conducteurs (2) qui contient les impuretés à de faibles concentrations. Une zone de jonction intérieure (8) est formée dans la jonction directe de la première zone de semi-conducteurs (1) et de la deuxième zone de semi-conducteurs (2) et une zone de jonction extérieure (9) est formée dans la jonction de la troisième zone de semi-conducteurs (3) entourant la zone de jonction intérieure (8) et la première zone de semi-conducteurs (1) ou la deuxième zone de semi-conducteurs (2). Etant donné que le claquage dû à l'adhérence d'impuretés à la zone de jonction extérieure (9) est supprimé, la tension de résistance de l'élément à semi-conducteurs augmente et la tension de claquage se stabilise.
PCT/JP2003/003181 2002-03-26 2003-03-17 Element a semi-conducteurs et procede de fabrication de ce dernier WO2003081681A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003579289A JP4247674B2 (ja) 2002-03-26 2003-03-17 半導体素子

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002-85979 2002-03-26
JP2002085979 2002-03-26

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WO2003081681A1 true WO2003081681A1 (fr) 2003-10-02

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TW (1) TWI221342B (fr)
WO (1) WO2003081681A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085663A (zh) * 2019-05-07 2019-08-02 无锡鸣沙科技有限公司 一种半导体pn结及制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS433573B1 (fr) * 1964-12-22 1968-02-09
JPS462707B1 (fr) * 1967-08-03 1971-01-22
JPS4624621B1 (fr) * 1967-08-25 1971-07-15
JPS5010980A (fr) * 1973-05-28 1975-02-04
JPS548982A (en) * 1977-06-23 1979-01-23 Mitsubishi Electric Corp Semiconductor device
JPH02111079A (ja) * 1988-06-16 1990-04-24 Hyundai Electron Ind Co Ltd 高電圧用半導体素子およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS433573B1 (fr) * 1964-12-22 1968-02-09
JPS462707B1 (fr) * 1967-08-03 1971-01-22
JPS4624621B1 (fr) * 1967-08-25 1971-07-15
JPS5010980A (fr) * 1973-05-28 1975-02-04
JPS548982A (en) * 1977-06-23 1979-01-23 Mitsubishi Electric Corp Semiconductor device
JPH02111079A (ja) * 1988-06-16 1990-04-24 Hyundai Electron Ind Co Ltd 高電圧用半導体素子およびその製造方法

Also Published As

Publication number Publication date
JPWO2003081681A1 (ja) 2005-07-28
TWI221342B (en) 2004-09-21
JP4247674B2 (ja) 2009-04-02
TW200305297A (en) 2003-10-16

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