200305297 Ο) 玖、發明說明 【發明所屬之技術領域】 本發明是有關半導體元件，特別是關於耐壓値安定的 半導體元件及其製法。 【先前技術】 第8圖所示以往的台面型構造的二極體（4〇 )具備半 導體基板（24 )，該半導體基板（24 )是由陰極領域的 N +型領域（21)及N-型領域（23)與形成於N-型領域（ 23 )上的陽極領域的P +型領域（22 )所構成，且於半導 體基板（24 )的下面及上面形成有一對的電極（25,26 ) 。N-型領域（23 )含有比N +型領域（21 )及P +型領域（ 22)還要低濃度的雜質。在第8圖的二極體（40)中，P + 型領域（22 )與N-型領域（23 )之間的PN接合領域（2S )會被形成平面狀，在由半導體基板（24)的下面往上方 擴張的傾斜側面形成有PN接合領域（28 )的端部（28a )。在半導體基板（24 )具有傾斜側面的台面型構造的二 極體（40)中，形成於N型半導體領域與P型半導體領 域之間的空乏層（未圖示）會從P +型領域（22 )與N-型 領域（23 )的PN接合領域（2S )擴展至半導體基板（24 )的端部（28a )。因此，在第8圖的二極體（40 )中， 可取得與由構成平面PN接合的P +型領域（22)及N-型 領域（23 )的雜質濃度所理論性算出的値同等的耐壓値， 達成高耐壓化。 -5- (2) (2)200305297 第9圖所示以往的平面型構造的二極體（50)與第8 圖的二極體（40)同樣的’具備：形成有N +型領域（21 )，N-型領域（23 )及P +型領域（22 )的半導體基板（ ，以及分別形成於N +型領域（21)及P +型領域（22 )的外面之一對的電極（25,26 )，且除上面以外，會藉 由N-型領域（23 )來包圍P +型領域（22 ) 。P +型及N-型 領域（22,23 )間的PN接合領域（38 )具備：形成於半導 體基板（34)的上面，且藉由保護膜（37)來予以覆蓋的 端部（3Sa)，及PN接合彎曲的曲率部（3Sb )。在製造 第9圖的二極體（5〇)時，會藉由對N-型領域（23 )的 全面進行氧化來形成二氧化矽（Si02)的保護膜（37)， 且部份蝕刻去除保護膜（37 )，而於N-型領域（23 )的 露出部份，藉由擴散來形成P +型領域（22 )，因此無論 是在製造中或者製造後，端部（38a)會一直藉由保護膜 (37)來予以覆蓋，不會因附著物而造成耐壓變動，可取 得可靠度高的二極體。 【發明內容】 【發明所欲解決之課題】 就第8圖所示台面型構造的二極體（40 )而言，雖可 如上述一般取得理論性算出的高耐壓値，但因爲PN接合 τιΙ域（28)的端部（28a)露出，所以擊穿（break down )電壓會因附著於半導體基板（24 )的側面之鈉等的有害 物質而容易變動。如第8圖所示，即使藉由保護膜（27 ) -6- (3) (3)200305297 來覆蓋端部（28a)，雜質還是會在保護膜（27)形成前 的製造時附著於端部（28a )，而導致耐壓性能劣化，無 法取得可靠度高的二極體。 相對的，第9圖所示平面型構造的二極體（50)是在 形成保護膜（37)之後，將P型的雜質源擴散於N-型領 域（23 )，因此PN接合領域（38 )的端部（38a )會藉 由橫方向的擴散來進入保護膜（37)與N-型領域（23) 之間，而使得端部（3 8 a )不會露出，所以幾乎不會受到 附著物的影響，二極體的耐壓變動不易產生。但，由於曲 率半徑小的PN接合領域（3S )的曲率部（38b )會局部 產生電場集中，而使容易達到臨界電場，因此第9圖之平 面型構造的二極體（50)與第8圖的二極體（40)相較下 ’擊穿電壓較低，無法達成高耐壓値。又，因爲難以取得 理論性算出的耐壓値，所以會有不易設計元件的問題發生 〇 因應於此，本發明的目的是在於提供一種擊穿電壓不 會變動具有安定的耐壓値之半導體元件及其製法。又，本 發明的目的是在於提供一種可取得接近理論性的擊穿電壓 値之所望的安定耐壓，且元件設計容易的半導體元件及其 製法。 【用以解決課題之手段】 本發明之半導體元件，係具備：第1半導體領域（1 )，及具有與該第1半導體領域（1)不同的導電型，且 (4) (4)200305297 對向於上述第1半導體領域（1)而配置之第2半導體領 域（2)，及配置於上述第1半導體領域（1)與第2半導 體領域（2 )之間，且含比上述第1半導體領域（1 )及第 2半導體領域（2 )還要低濃度的雜質之第3半導體領域 (3 )。皆比第3半導體領域（3 )的雜質濃度高的第1半 導體領域（1 )與第2半導體領域（2 )係形成彼此直接接 合，且形成電場集中點（break down point )的內側接合 領域（8 )。又，第3半導體領域（3 )係包圔內側接合領 域（8 )而形成環狀，並形成對第1半導體領域（1 )或第 2半導體領域（2 )接合的外側接合領域（9 )，且在外側 接合領域（9)形成有寬廣的空乏層，因此在施加逆方向 的偏壓時，難以產生電場集中，即使在外側接合領域（9 )附著有雜質，擊穿電壓也不會產生變動。 本發明之半導體元件的製法係包含： 在含高濃度的雜質的第1半導體領域（1)上設置含 低濃度的雜質的第3半導體領域（3 )之過程；及 在第3半導體領域（3 )的內側形成到達第1半導體 領域（1 )的凹部（7 )之過程；及 在露出第1半導體領域（〇的凹部（7 )上及包圍該 凹部（7)的第3半導體領域（3)上形成包含與第1半導 體領域（1)不同導電型的高濃度雜質之第2半導體領域 (2 )，直接使該第2半導體領域（2 )與第1半導體領域 (1 )接合，而形成內側接合領域（8 )，且直接使第2半 導體領域（2)與第3半導體領域（3)接合’而形成包圍 -8- (5) (5)200305297 內側接合領域（8 )的外側接合領域（9 )之過程。 【實施方式】 以下，根據第1〜7圖來說明將半導體元件適用於二 極體之本發明的實施形態。 顯示本發明的第1實施形態之第1圖及第2圖的二極 體（10)爲齊納二極體（Zener diode)，亦即在半導體基 板（4 )上具備：第1半導體領域的N +型領域（1 )，及 對向於N +型領域（1 )，且與N +型領域（1 )不同導電型 的第2半導體領域的P +型領域（2 )，及配置於N +型領 域（1 )與P +型領域（2 )之間，且含比N +型及P +型領域 (1，2)還要低濃度雜質的第3半導體領域的N-型領域（3 )，又，在N +型領域（1 )與P +型領域（2 )的各外面形 成有一對的電極（5,6)，在電極（6)的約中央具有凹陷 (6a) ° 在本實施形態中，N +型領域（1 )及N-型領域（3 ) 的雜質爲使用磷，P +型領域（2 )的雜質爲使用硼。沿著 形成於二極體（10)上面的凹部（7) ，P +型領域（2)會 以約均一的厚度來形成於N +型領域（1 )上，在半導體基 板（4 )的內部約中央具備：P +型領域（2 )的平坦底面（ 2a)及彎曲狀的傾斜面（2b)與形成於N +型領域（1)內 側的碟狀凹部（1 a )會直接進行PN接合之內側接合領域 (8 )。由於內側接合領域（8 )是直接接合含有比N-型 領域（3 )還要高濃度雜質的N +型領域（1 )與P +型領域 -9 - (6) (6)200305297 (2 )，而形成平面PN接合，因此可取得所期望的耐壓 〇 N-型領域（3)係包圍內側接合領域（8)而形成環狀 ，且使對P +型領域（2 )直接接合的外側接合領域（9 ) 與P +型領域（2 ) —起形成。又，N-型領域（3 )具備： 朝向N +型領域（1)的碟狀凹部（la)而成前面變窄的環 狀傾斜面（3 a )(第2圖的虛線所示者），及包圍傾斜面 (3 a )的水平平坦面（3 b )。並且，傾斜面（3 a )及平坦 面（3b )會PN接合於P +型領域（2 )。又，外側接合領 域（9 )具備：由半導體基板（4 )的側面露出的外端部（ 9a)。又，從形成於含高濃度雜質的P +型領域（2)與含 低濃度雜質的N-型領域（3 )之間的外側接合領域（9 ) 擴展的空乏層會寬廣地形成，特別是會擴展於含低濃度雜 質的N-型領域（3 )側。因此，在施加逆方向的偏壓時， 即使在外側接合領域（9 )的外端部（9a )附著有害物質 ，照樣不會產生擊穿電壓。並且，在本實施形態中設有 N-型領域（3)的傾斜面（3a)及P +型領域（2)的傾斜 面（2a )，而來拉長從外端部（9a )到內側接合領域（8 )的距離，抑止因附著物而造成的耐壓變動。 如第3圖所示，在製造二極體（10)時，首先準備一 形成有含高濃度磷的N +型領域（1 )之半導體基板（4 ) ，且使N-型領域（3 )成長於N +型領域（1 )上，或使雜 質擴散於N-型領域（3 )的底部，而形成N +型領域（1 ) ，藉此於N +型領域（1 )上設置N-型領域（3 )。在第3 -10- (7) (7)200305297 (a )圖中，藉由外延成長法來使含低濃度雜質的型 領域（3 )薄薄地層疊於含高濃度雜質的Ν +型領域（1 ) 上。在半導體基板上維持結晶性來使其他結晶層成長的外 延成長法，可於成長過程中摻雜雜質。就本實施形態而言 ，是在反應容器（未圖示）內配置具有Ν +型領域（1 )的 半導體基板（4 )，在1 1 0 0〜1 2 0 0 °C的高溫下流入甲矽烷 (SiH4 )氣體及氫氣，而使矽原子連續層疊於半導體基板 (4 )的底層矽的結晶格子。同時，混合磷化氫（PH3 )等 含雜質磷的摻雜劑氣體，在N +型領域（1 )上層疊N-型 領域（3 )。 其次，藉由鈾刻來去除形成於半導體基板（4)上的 N-型領域（3 )的內側表面，如第3 ( b )圖所示，使到 達N +型領域（1 )的凹部（7 )像第2圖所示那樣在N·型 領域（3 )內側形成圓形狀。在此，雖可將凹部（7 )的最 下部（7a)設置於比N +型領域（1 )與N-型領域（3 )的 接合面還要靠上方或下方，但在本實施形態中是將最下部 (7a)設置於N +型領域（1)內，而使P +型領域（2)能 夠確實地接觸於N +型領域（1 )。並且，使凹部（7 )的 側面形成曲率半徑大之緩和的曲面狀，藉由具有圓形內緣 的N-型領域（3 )來包圍凹部（7 )的側面。 接著，在露出N +型領域（1 )的凹部（7 )上及包圍 凹部（7 )的N-型領域（3 )上，使和N +型領域（1 )不 同導電型的高濃度雜質（例如，硼）擴散，而如第3 ( c )圖所示，形成含高濃度硼的P +型領域（2 )，且使P + -11 - (8) (8)200305297 型領域（2 )與N +型領域（1 )直接接合來形成內側接合 領域（8 )，以及直接接合P +型領域（2 )與N-型領域（3 )來形成包圍內側接合領域（8 )的外側接合領域（9 )。 在此’硼的擴散是例如藉由進行加熱處理的固體擴散法等 來將含雜質源的硼的固體薄膜形成於N-型領域（3)及凹 部（7 )。又，沿著N-型領域（3 )及凹部（7 )來形成P + 型領域（2 )，且使沿著凹部（7 )的最下部（h )的P + 型領域（2 )的平坦底面（2a )直接接合於N +型領域（1 )。藉由P +型領域（2 )的形成，在N +型領域（1 )與P + 型領域（2 )之間，包圍內側接合領域（8 )來配置N-型 領域（3 )，且N-型領域（3 )的傾斜面（3a)及平坦面 (3b)與P +型領域（2)會進行PN接合。又，藉由擴散 來形成的P +型領域（2 )的厚度會因爲N +型領域（1 )與 N-型領域（3 )的雜質濃度不同，而於N-型領域（3 )形 成較厚，所以在P +型領域（2 )的傾斜面（2b )與N-型領 域（3 )的傾斜面（3b )之間會產生若干的落差。 最後，在N +型領域（1 )的下面連接平坦的電極（5 )，且於P +型領域（2)的上面連接具有凹陷（6a)的電 極（6)，而形成第1圖所示的二極體（10)。並且，在 一對的電極（5,6 )結合導線，以樹脂等來封裝後形成製 品。 就二極體（1 0 )而言，在內側接合領域（8 )中，空 乏層會狹窄地形成，在外側接合領域（9 )中，空乏層會 寬廣地形成。因此，若在上述二極體（10)中施加逆方向 -12- 200305297 (9) ?二 Ρ 側 C 1內穿僅m擊 N-則之 據，流 依壓電 過耐的 超論向 壓理方 電的逆 且定動 ，而流 壓等速 電度急 的濃生 域 領 域 領 合200305297 〇). Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a withstand voltage and stability and a manufacturing method thereof. [Prior art] A conventional mesa-type structure (40) shown in FIG. 8 is provided with a semiconductor substrate (24). The semiconductor substrate (24) is an N + -type field (21) and N- And a pair of electrodes (25, 26) formed on the lower surface and upper surface of the semiconductor substrate (24). ). The N-type region (23) contains impurities at a lower concentration than the N + -type region (21) and the P + -type region (22). In the diode (40) of FIG. 8, the PN junction region (2S) between the P + -type region (22) and the N-type region (23) is formed into a planar shape, and the semiconductor substrate (24) An end portion (28a) of the PN junction area (28) is formed on the inclined side surface that is extended upward from the lower side. In a semiconductor substrate (24) having a mesa-type structure (40) with an inclined side surface, an empty layer (not shown) formed between the N-type semiconductor field and the P-type semiconductor field is changed from the P + type field ( 22) The PN junction area (2S) with the N-type area (23) is extended to the end portion (28a) of the semiconductor substrate (24). Therefore, in the diode (40) of FIG. 8, it is possible to obtain a value equivalent to 値 calculated theoretically from the impurity concentration of the P + -type region (22) and the N-type region (23) constituting the planar PN junction. Withstands pressure and achieves high pressure resistance. -5- (2) (2) 200305297 The diode (50) of the conventional planar structure shown in FIG. 9 is the same as the diode (40) of FIG. 21), a semiconductor substrate () of the N-type region (23) and the P + -type region (22), and an electrode pair formed on the outside of the N + -type region (21) and the P + -type region (22), respectively ( 25,26), and in addition to the above, the P + -type field (22) is surrounded by the N-type field (23). The PN junction field between the P + -type and N-type fields (22,23) (38 ) Includes: an end portion (3Sa) formed on the upper surface of the semiconductor substrate (34) and covered with a protective film (37), and a curvature portion (3Sb) of PN junction bending. The diode is manufactured in FIG. 9 When the body (50) is formed, the protective film (37) of silicon dioxide (Si02) is formed by comprehensively oxidizing the N-type region (23), and the protective film (37) is partially etched and removed. The exposed part of the N-type region (23) forms the P + -type region (22) by diffusion, so the end portion (38a) will always be protected by the protective film (37) whether during or after manufacturing. Cover it The diode with high pressure resistance caused by the attachment can obtain a highly reliable diode. [Summary of the Invention] [Questions to be Solved by the Invention] The diode (40) of the mesa structure shown in FIG. A theoretically calculated high withstand voltage can be obtained as described above, but since the end portion (28a) of the PN junction τιΙ domain (28) is exposed, a breakdown voltage may be caused by adhesion to the side surface of the semiconductor substrate (24). As shown in Figure 8, even if the end portion (28a) is covered by the protective film (27) -6- (3) (3) 200305297, impurities will remain in the protective film ( 27) It is attached to the end portion (28a) during manufacturing before formation, which deteriorates the pressure resistance performance and cannot obtain a highly reliable diode. In contrast, the planar structure diode (50) shown in Figure 9 After the protective film (37) is formed, the P-type impurity source is diffused in the N-type region (23), so the end portion (38a) of the PN junction region (38) will enter the protective film by lateral diffusion. (37) and N-type area (23), so that the end portion (3 8 a) will not be exposed, so it will hardly Due to the influence of attachments, the diode's withstand voltage change is not easy to occur. However, the curvature portion (38b) of the PN junction area (3S) with a small curvature radius locally generates an electric field concentration, which makes it easy to reach the critical electric field. Compared with the diode (50) of the planar structure of FIG. 9 and the diode (40) of FIG. 8, the breakdown voltage is lower and a high withstand voltage cannot be achieved. Furthermore, it is difficult to obtain a theoretical calculation. A problem occurs in that it is difficult to design a device due to a breakdown voltage. Accordingly, an object of the present invention is to provide a semiconductor device having a stable breakdown voltage without a breakdown voltage and a manufacturing method thereof. It is another object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device which can achieve the desired breakdown voltage close to the theoretical breakdown voltage 且, and have easy device design. [Means for solving the problem] The semiconductor element of the present invention includes: a first semiconductor field (1); and a conductivity type different from that of the first semiconductor field (1); and (4) (4) 200305297 pairs The second semiconductor field (2) disposed toward the first semiconductor field (1), and between the first semiconductor field (1) and the second semiconductor field (2), the ratio is greater than the first semiconductor field. In the field (1) and the second semiconductor field (2), the third semiconductor field (3) has a low concentration of impurities. The first semiconductor region (1) and the second semiconductor region (2), each having a higher impurity concentration than the third semiconductor region (3), form an inner junction region that directly joins each other and forms an electric field concentration point (break down point) ( 8 ). Moreover, the third semiconductor field (3) is formed into a loop including the inner bonding field (8), and the outer bonding field (9) joined to the first semiconductor field (1) or the second semiconductor field (2), In addition, a wide empty layer is formed in the outer bonding area (9). Therefore, it is difficult to generate electric field concentration when a reverse bias is applied. Even if impurities are attached to the outer bonding area (9), the breakdown voltage does not change. . The method for manufacturing a semiconductor device of the present invention includes: a process of providing a third semiconductor field (3) containing a low concentration of impurities on a first semiconductor field (1) containing a high concentration of impurities; and a third semiconductor field (3) ) To form a recess (7) reaching the first semiconductor region (1); and a third semiconductor region (3) that exposes the recess (7) of the first semiconductor region (0) and surrounds the recess (7) A second semiconductor field (2) containing a high-concentration impurity of a conductivity type different from that of the first semiconductor field (1) is formed thereon, and the second semiconductor field (2) and the first semiconductor field (1) are directly joined to form an inner side. The bonding area (8), and the second semiconductor area (2) and the third semiconductor area (3) are directly bonded to form an outer bonding area that surrounds -8- (5) (5) 200305297 (8) 9). [Embodiment] Hereinafter, embodiments of the present invention in which a semiconductor element is applied to a diode will be described with reference to Figs. 1 to 7. Figs. 1 and 2 showing a first embodiment of the present invention (10) is a Zener diode ), That is, provided on the semiconductor substrate (4): the N + type field (1) in the first semiconductor field, and the N + type field (1), which is different from the N + type field (1) in conductivity type P + type field (2) of the second semiconductor field, and is disposed between the N + type field (1) and the P + type field (2), and contains N + type and P + type fields (1,2 ) The N-type region (3) of the third semiconductor region with a low concentration of impurities, and a pair of electrodes (5, 6) are formed on each of the N + -type region (1) and the P + -type region (2). ), With a depression (6a) at about the center of the electrode (6) ° In this embodiment, the impurities in the N + type area (1) and the N-type area (3) are phosphorus, and the P + type area (2) The impurity used is boron. Along with the recess (7) formed on the diode (10), the P + -type region (2) will be formed on the N + -type region (1) with a uniform thickness. The inside of the substrate (4) is approximately at the center: a flat bottom surface (2a) and a curved inclined surface (2b) of the P + type region (2) and a dish-shaped recess (1 a) formed inside the N + type region (1). ) Will be directly inside the PN joint Domain (8). Since the inner junction domain (8) is a direct junction between the N + -type domain (1) and the P + -type domain containing higher concentrations of impurities than the N-type domain (3) -9-(6) (6 ) 200305297 (2) to form a planar PN junction, so that the desired pressure resistance can be achieved. The N-type region (3) surrounds the inner joint region (8) to form a ring, and the P + -type region (2 ) The directly joined outer joint area (9) is formed together with the P + -type area (2). Further, the N-type region (3) is provided with a ring-shaped inclined surface (3a) having a narrowed front surface toward the dish-shaped recess (1a) of the N + -type region (1) (shown by a dotted line in FIG. 2). , And a horizontal flat surface (3b) surrounding the inclined surface (3a). The inclined surface (3a) and the flat surface (3b) are PN-bonded to the P + -type region (2). The outer bonding area (9) includes an outer end portion (9a) exposed from a side surface of the semiconductor substrate (4). In addition, the empty layer extended from the outer junction region (9) formed between the P + -type region (2) containing a high-concentration impurity and the N-type region (3) containing a low-concentration impurity is broadly formed, especially It will expand to the N-type area (3) side with low concentration of impurities. Therefore, when a reverse bias is applied, even if a harmful substance is attached to the outer end portion (9a) of the outer joint region (9), a breakdown voltage will not be generated. Moreover, in this embodiment, the inclined surface (3a) of the N-type area (3) and the inclined surface (2a) of the P + type area (2) are provided to stretch from the outer end portion (9a) to the inner side. The distance of the bonding area (8) suppresses the pressure fluctuation caused by the attachment. As shown in FIG. 3, when manufacturing the diode (10), first, a semiconductor substrate (4) formed with an N + -type region (1) containing a high concentration of phosphorus is prepared, and the N-type region (3) is prepared. Grow on the N + -type region (1), or make the impurities diffuse at the bottom of the N-type region (3) to form the N + -type region (1), thereby setting N- on the N + -type region (1) Type field (3). In Fig. 3-10- (7) (7) 200305297 (a), the epitaxial growth method is used to thin the type field containing low concentration impurities (3) on the N + type field containing high concentration impurities ( 1) Up. An epitaxial growth method that maintains crystallinity on a semiconductor substrate to grow other crystal layers can be doped with impurities during the growth process. In this embodiment, a semiconductor substrate (4) having an N + -type region (1) is arranged in a reaction container (not shown), and flows into the substrate at a high temperature of 1 1 0 to 12 0 ° C. Silane (SiH4) gas and hydrogen, so that silicon atoms are continuously stacked on the crystal lattice of the bottom silicon of the semiconductor substrate (4). At the same time, a dopant gas containing impurity phosphorus such as phosphine (PH3) is mixed, and an N-type region (3) is laminated on the N + -type region (1). Next, the inner surface of the N-type region (3) formed on the semiconductor substrate (4) is removed by uranium engraving. As shown in FIG. 3 (b), the concave portion (1) reaching the N + -type region (1) is removed ( 7) A circular shape is formed inside the N-type area (3) as shown in FIG. 2. Here, although the lowermost portion (7a) of the recessed portion (7) can be provided above or below the joint surface of the N + -type area (1) and the N-type area (3), in this embodiment, The lowermost part (7a) is provided in the N + -type region (1), and the P + -type region (2) can be reliably contacted with the N + -type region (1). Further, the side surface of the recessed portion (7) is formed into a gently curved surface with a large curvature radius, and the side surface of the recessed portion (7) is surrounded by an N-type region (3) having a circular inner edge. Next, on the recess (7) exposing the N + -type region (1) and the N-type region (3) surrounding the recess (7), a high-concentration impurity having a conductivity type different from that of the N + -type region (1) ( For example, boron) diffuses, and as shown in Fig. 3 (c), a P + type field (2) containing a high concentration of boron is formed, and P + -11-(8) (8) 200305297 type field (2) It is directly joined with the N + -type region (1) to form the inner joint region (8), and directly joined with the P + -type region (2) and the N-type region (3) to form the outer joint region surrounding the inner joint region (8). (9 ). Here, the diffusion of boron is performed by forming a solid thin film of boron containing an impurity source in the N-type region (3) and the recessed portion (7) by, for example, a solid diffusion method in which heat treatment is performed. The P + -type region (2) is formed along the N-type region (3) and the recess (7), and the P + -type region (2) along the lowermost portion (h) of the recess (7) is made flat. The bottom surface (2a) is directly bonded to the N + type region (1). With the formation of the P + -type region (2), the N--type region (3) is arranged between the N + -type region (1) and the P + -type region (2) to surround the inner joint region (8), and N The inclined surface (3a) and the flat surface (3b) of the -type region (3) are PN-bonded to the P + type region (2). In addition, the thickness of the P + -type region (2) formed by diffusion may be different from that of the N + -type region (1) and the N-type region (3). It is thick, so there will be some gaps between the inclined surface (2b) of the P + type area (2) and the inclined surface (3b) of the N-type area (3). Finally, a flat electrode (5) is connected below the N + type area (1), and an electrode (6) with a recess (6a) is connected above the P + type area (2), so as to form the figure 1 Of the diode (10). Then, a pair of electrodes (5, 6) are combined with a lead wire, and then sealed with resin or the like to form a product. In the case of the diode (10), in the inner junction region (8), the empty layer is formed narrowly, and in the outer junction region (9), the empty layer is formed widely. Therefore, if the reverse direction of -12-200305297 (9) is applied to the above diode (10), the inner side of the two P-sides C1 penetrates only m and strikes N-, and the flow depends on the super-theoretical pressure of piezoelectric over-resistance. Li Fangdian's inverse and fixed movement, and the flow pressure constant velocity electric energy concentration of the concentration field domain cooperation
η W 質產在 雜會。 的中象 \ϊ/ ) 現 第9圖所示的平面型構造的半導體元件（50)中，電場會 局部集中於曲率部（3 8b )，在該部份產生擊穿現象，相 對的在本實施形態中，由於是使電場集中於雜質濃度較高 的N +型領域（1 )與P +型領域（2 )之間的平面狀內側接 合領域（8 )，因此可取得接近理論値的擊穿電壓。因此 ，可容易進行二極體（1 〇 )的設計。另一方面，在外側接 合領域（9)中，寬廣形成的空乏層會緩和電場集中，而 不會產生擊穿現象。因此，即使有害物質附著於露出後的 外端部（9a )，照樣不會產生擊穿現象。又，由於在離開 露出PN接合的外端部（9a )，亦即在二極體（1 〇 )的約 中央處設有產生擊穿現象的內側接合領域（8 )，因此與 第8圖的台面型構造的二極體（40)有所不同，不會受到 半導體基板（4 )側面的附著物等的影響，擊穿電壓不會 變動。 本發明並非只限於上述實施形態，亦可如第4〜7圖 所示進行各種的變更。在第4〜7圖所示的第2〜7實施形 態中，大致可取得與第1圖所示的第1實施形態相同的作 用效果。 首先，與第1圖相較下，第4圖所示之第2實施形態 的二極體（20 )係形成較厚的第3半導體領域（3 )，且 使第3半導體領域（3 )的傾斜面（3 a )的剖面平坦形成 -13 - (10) (10)200305297 。就第4圖所示之二極體（20 )的製法而言，首先使磷擴 散於含低濃度磷的半導體基板的下面，然後如第5 ( a ) 圖所示，在第3半導體領域的N-型領域（3 )的底部部份 形成含高濃度磷的第1半導體領域的N +型領域（1 )。其 次，如第5 ( b )圖所示，藉由蝕刻來去除N _型領域（3 )的內側，而形成凹部（7 )。在本實施形態中，係將凹 部（7 )的最下部（7a)形成於比N +型領域（i )與N-型 領域（3 )的接合面還要靠上方。接著，使與n +型領域（ 1)不同導電型的雜質硼擴散於N-型領域（3 )及凹部（7 )，而於半導體基板（14)的上面形成含高濃度雜質的第 2半導體領域的P +型領域（2 )。藉此，如第5 ( c )圖 所示，在半導體基板（14 )的約中央處形成有：N +型領 域（1 )與P +型領域（2 )直接接合的平坦內側接合領域 (8 )，及包圍內側接合領域（8 )來接合於P +及N-型領 域（2,3)之間的外側接合領域（9)。在P +型領域（2) 的形成後，與上述二極體（10 )同樣的形成電極（5,6 ) ，藉此來取得第4圖所示的二極體（20 )。 又，第6 ( a )〜（c )圖的第3〜5實施形態係顯 示變更半導體領域的導電型配置之各二極體（20 a，20b，20c )。其中，在二極體（20a)的第1，第2及第3半導體 領域（1，2,3 )中分別形成有N +型，P +型及P-型的半導體 領域，在二極體（20b )的第1，第2及第3半導體領域 (1,2,3 )中分別形成有P +型，N +型及P-型的半導體領域 ，在二極體（20c)的第1，第2及第3半導體領域（ -14- (11) (11)200305297 1，2,3)中分別形成有P +型，N +型及N-型的半導體領域。 就第6(a)及（c)圖所示的二極體（20a，20c)而言’ 由於內側接合領域（8 )與外側接合領域（9 )會形成約連 續的平面狀，因此可取得容易高耐壓化的二極體。 第7 ( a )圖所示之第6實施形態的二極體（3 0 )係 顯示對第4圖的二極體（20 )變更第2及第3半導體領域 (2,3 )間的外側接合領域（9 )的形狀者。又，第7 ( b )圖所示之第7實施形態的二極體（3 〇b )係顯示對第6 (b )圖的二極體（20b )變更第1及第3半導體領域（ 1，3 )間的接合面的形狀者。 【發明之效果】 如以上所述，本發明可取得擊穿電壓接近理論値之理 想的耐壓，且可防止因附著物等的影響而造成的擊穿現象 ，而形成一種能夠抑止耐壓變動之可靠度高的半導體元件 【圖式簡單說明】 第1圖係表示本發明之第1實施形態的二極體的剖面 圖。 第2圖係表示第1圖之二極體的平面圖。 第3圖係表示第1圖之二極體的製法的過程剖面圖。 第4圖係表示本發明之第2實施形態的二極體的剖面 圖0 -15- (12) 200305297 第5圖係表示第4圖之二極體的製法的過程剖面圖。 第6圖係表示本發明之第3，4及5實施形態的二極 體的剖面圖。 第7圖係表示本發明之第6及7實施形態的二極體的 剖面圖。 第8圖係表示以往的台面型構造的二極體的剖面圖。 第9圖係表示以往的平面型構造的二極體的剖面圖。 [$要元件對照表】 (1 ) ••第1半導體領域（N +型領域） (1 〇 ··碟狀凹部 (2 ) ••第2半導體領域（p +型領域） (2 a ) ··底面 (3 ) ••第3半導體領域（N-型領域） (5,6 ):電極 (6a):凹陷 (7 ):凹部 (8 ):內側接合領域 (9 ):外側接合領域 (10 ):二極體η W is produced at the conference. The medium image \ ϊ /) In the semiconductor device (50) of the planar structure shown in Fig. 9, the electric field is locally concentrated in the curvature portion (38b), and a breakdown phenomenon occurs in this portion. In the embodiment, since the electric field is concentrated in the planar inner junction region (8) between the N + -type region (1) and the P + -type region (2) with a higher impurity concentration, it is possible to obtain a near-theoretical attack. Wear voltage. Therefore, the design of the diode (100) can be easily performed. On the other hand, in the outer joint area (9), the widely formed empty layer can relax the electric field concentration without causing a breakdown phenomenon. Therefore, even if a harmful substance adheres to the exposed outer end portion (9a), breakdown does not occur. In addition, since the outer end portion (9a) leaving the PN junction is exposed, that is, at the center of the diode (10), the inner junction area (8) is formed which causes a breakdown phenomenon, so it is the same as that of FIG. 8 The diode (40) of the mesa structure is different, and is not affected by the attachments on the side surface of the semiconductor substrate (4), and the breakdown voltage does not change. The present invention is not limited to the above-mentioned embodiment, and various changes can be made as shown in Figs. 4 to 7. In the second to seventh embodiments shown in Figs. 4 to 7, approximately the same effects as those of the first embodiment shown in Fig. 1 can be obtained. First, compared with FIG. 1, the diode (20) of the second embodiment shown in FIG. 4 forms a thicker third semiconductor region (3), and makes the third semiconductor region (3) thicker. The cross section of the inclined surface (3 a) is flat to form -13-(10) (10) 200305297. In the manufacturing method of the diode (20) shown in FIG. 4, firstly, phosphorus is diffused under the semiconductor substrate containing a low concentration of phosphorus, and then as shown in FIG. 5 (a), in the third semiconductor field, The bottom portion of the N-type region (3) forms the N + -type region (1) of the first semiconductor region containing a high concentration of phosphorus. Next, as shown in FIG. 5 (b), the inside of the N_-type region (3) is removed by etching to form a recess (7). In this embodiment, the lowermost portion (7a) of the recessed portion (7) is formed above the joint surface of the N + -type region (i) and the N-type region (3). Next, an impurity boron having a conductivity different from that of the n + -type region (1) is diffused in the N- -type region (3) and the recess (7), and a second semiconductor containing a high concentration of impurities is formed on the semiconductor substrate (14). Field of P + type field (2). Thereby, as shown in FIG. 5 (c), a flat inner bonding region (8) where N + type region (1) and P + type region (2) are directly bonded is formed at approximately the center of the semiconductor substrate (14). ), And the outer joint region (9) which surrounds the inner joint region (8) to join between the P + and N-type regions (2, 3). After the formation of the P + -type region (2), the electrodes (5, 6) are formed in the same manner as the diode (10), thereby obtaining the diode (20) shown in FIG. 4. In addition, the third to fifth embodiments of FIGS. 6 (a) to (c) show the diodes (20a, 20b, 20c) that change the conductive type arrangement in the semiconductor field. Among them, N + -type, P + -type, and P-type semiconductor fields are formed in the first, second, and third semiconductor fields (1,2,3) of the diode (20a), respectively. (20b) In the first, second, and third semiconductor fields (1,2,3), P +, N +, and P-type semiconductor fields are formed, respectively. In the first field of the diode (20c), In the second and third semiconductor fields (-14- (11) (11) 200305297 1, 2, 3), P + -type, N + -type and N-type semiconductor fields are formed, respectively. With respect to the diodes (20a, 20c) shown in Figs. 6 (a) and (c), 'the inner joining area (8) and the outer joining area (9) form a substantially continuous planar shape, so it can be obtained. Diodes that tend to withstand high pressure. The diode (30) of the sixth embodiment shown in Fig. 7 (a) shows the change of the outer side between the second and third semiconductor fields (2, 3) of the diode (20) of Fig. 4 Join the shape of the field (9). The diode (30b) of the seventh embodiment shown in FIG. 7 (b) shows a modification of the diode (20b) of FIG. 6 (b) in the first and third semiconductor fields (1 , 3) the shape of the joint surface. [Effects of the Invention] As described above, the present invention can achieve an ideal withstand voltage with a breakdown voltage close to the theoretical value 且, and can prevent breakdown phenomena caused by the influence of attachments, etc., and can form a type that can suppress the withstand voltage variation Highly Reliable Semiconductor Element [Brief Description of Drawings] FIG. 1 is a cross-sectional view showing a diode according to a first embodiment of the present invention. Fig. 2 is a plan view showing the diode of Fig. 1; Fig. 3 is a cross-sectional view showing a process of manufacturing the diode of Fig. 1; Fig. 4 is a cross-sectional view showing a diode of a second embodiment of the present invention. Fig. 0-15- (12) 200305297 Fig. 5 is a cross-sectional view showing a process of manufacturing the diode of Fig. 4. Fig. 6 is a sectional view showing a diode according to the third, fourth and fifth embodiments of the present invention. Fig. 7 is a sectional view showing a diode according to the sixth and seventh embodiments of the present invention. Fig. 8 is a sectional view showing a diode of a conventional mesa structure. Fig. 9 is a sectional view showing a diode having a conventional planar structure. [$ Required component comparison table] (1) •• 1st semiconductor field (N + type field) (1 0 ·· disc recess (2)) •• 2nd semiconductor field (p + type field) (2 a) · Bottom surface (3) •• Third semiconductor field (N-type field) (5,6): Electrode (6a): Depression (7): Recess (8): Inner bonding area (9): Outer bonding area (10 ): Diode
-16--16-