JPS63166268A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To stabilize dielectric strength of a semiconductor device, by forming deep P<+> regions reaching an N<+> buried layer so that the P<+> regions provide a part of the base region of an NPN transistor to be formed in an island region of an epitaxial layer on a P-type substrate having the N<+> buried layer, or provide emitter and collector regions of a lateral PNP transistor. CONSTITUTION:An N<+> buried layer 2 and a P<+> buried layer are formed in a P-type silicon substrate 1 and an N<-> epitaxial layer 3 is deposited thereon. In the wafer thus constructed, a P<+> isolation region 4 is formed by diffusion so deep as to reach the P<+> buried layer. Simultaneously therewith, a P<+> region 6 is formed by diffusion in an island region 5 for an NPN transistor while P<+> regions 8 and 9 are formed in an island region 7 for a lateral PNP transistor such that they all reach the N<+> buried layer 2. A P-type region 10 is then formed by diffusion such that it is joined with the P<+> region 6. Then an N<+> region 11 for a collector electrode is formed by diffusion in the island region 5 and an N<+> region 12 for an emitter region is formed in the P region 10. Simultaneously therewith, N<+> region 13 for a base electrode is formed by diffusion in the island region 7. Accordingly, the semiconductor device is allowed to have increased and stable dielectric strength without increasing sizes of elements.

Description

Detailed Description of the Invention [Objective of the Invention (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly a bipolar transistor in which a pie is formed in an integrated circuit and a method for forming the same. Regarding.

(Prior Art) FIG. 3 shows a conventional bipolar integrated circuit 7'? ．．
NPN } transistor and lateral PNP } The cross-sectional structure of the transistor is shown. That is, 31 is a P type silicon substrate, 32 is an anti-buried layer, 33 is a P+ isolation region, and 34 is a P type silicon substrate.
is an N- type island region which becomes the collector region of the NPN transistor; 35 is a P-type base region formed in the island region 34; 36 is an N+-type emitter region formed in the base region 35; The N+ region 38 for the collector electrode formed in the island region 34 is an N- type island region which becomes the base region of a lateral PNP transistor, and 39 is the N+ region 4 for the base electrode formed in the island region 38.
0 and 4 are P-type emitter regions and collector regions formed in the island region 38.

The above NPN transistor and lateral PNP transistor each have electric field concentration due to the curvature of the P region (diffusion region) within the N− island region 34, 38 or the adjacent P+
Since the breakdown voltage was determined by the extension of the depletion layer to the isolation region 33, there was a problem in that the breakdown voltage varied widely. In addition, since the diffusion in the P-type diffusion region is shallow, the depletion layer tends to extend laterally, and in order to increase the withstand voltage, a sufficient distance must be provided between the P-type diffusion region and the P isolation region. , there was a problem that the transistor size became large. In addition, in the NPN) Lancet star, if the diffusion of the P-type head region (base region) is shallow, the ASO (safe operating area) characteristics will deteriorate. Further, in the above-mentioned lateral PNP transistor, when the diffusion of the P-type head region (emitter region, collector region) is shallow, h2ゎ (current amplification factor) becomes low.

Conventionally, in order to improve the ASO characteristics of the above-mentioned NPN) lannostar, P+ diffusion has been carried out to surround the emitter region 36, but this has the problem of increasing the number of processes. Further, in order to improve the adhesiveness of the lateral PNP transistor, P+ diffusion is sometimes performed in the emitter region before the collector diffusion, but this increases the number of processes.

(Problems to be Solved by the Invention) As described above, the present invention has a large variation in breakdown voltage, and when trying to increase the breakdown voltage, the element size increases, and the ASO
This was developed to solve the problem of poor hFl characteristics, and the withstand voltage is stable and it is possible to increase the withstand voltage without increasing the element size.
It is an object of the present invention to provide a semiconductor device having a bipolar transistor with good characteristics and a method for manufacturing the semiconductor device by a simple process.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor device of the present invention provides a base region of an NPN transistor formed in an island region of an epitaxial growth layer on the surface of a P-type semiconductor substrate having an N+ buried layer. It is characterized in that the P region is formed deeply to reach the N+ buried layer as a part or the emitter region and collector region of the lateral PNP transistor.

Further, the method for manufacturing a semiconductor device of the present invention includes forming an NPN transistor or a lateral PN transistor on a wafer in which an N+ buried layer and an epitaxial growth layer are formed on a P-type semiconductor substrate.
When forming a P transistor, at the same time as forming a P isolation region, a P region is formed deep as part of the base region within the island region for an NPN transistor, or deep enough to reach the N+ buried layer, or within the island region for a lateral PNP transistor. P+ region t as emitter region and collector region
? It is important to form the layer deeply until it reaches the N+ buried layer.

(Function) According to the bipolar transistor in the semiconductor device described above, since a deep P+ region reaching the buried layer is formed, electric field concentration is reduced and the extension of the depletion layer in the lateral direction is suppressed, and the withstand voltage is increased as described above. It is stably determined by the concentration of the region and the N+ buried layer, and a sufficient breakdown voltage can be obtained even if the distance between the P+ region and the P+ isolation region is made small (the element size is made small). Furthermore, in the case of the NPN transistor, the ASiO characteristics are improved because a part of the base region has a deep P+ region. Furthermore, in the case of a bichiral PNP transistor, the emitter region and collector region each have a deep P+ region, so that the h0% property is improved.

Furthermore, according to the method for manufacturing a semiconductor device, by forming the P+ region deeply at the same time as the P isolation region, a bipolar transistor having the above-mentioned features can be manufactured with a simple process.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings. First, a G wafer as shown in FIG. 1 (&) is made. This wafer is obtained by forming an N+ buried layer 2 and a P+ buried layer on a P type silicon substrate 1, and then growing an N- epitaxial layer 3 thereon. Next, as shown in FIG. 1(b), a P isolation region 4 is formed by deep diffusion until it reaches the P buried layer, and at the same time, an NPN
) In the island region 5 for the runnostar, a P region 6 which will become a part of the base region is deeply diffused until it reaches the N+ buried layer 2, and at the same time, the island region 2 for the lateral PNP transistor is formed.
Inside, a P+ region 8 for an emitter region and a P region 9 for a collector region are formed in enlarged numbers until they reach the N+ buried layer 2, respectively. Next, as shown in FIG. 1(C), the N
A P region 10, which will become an effective base region, is formed by diffusion within the island region 5 of the PN transistor so as to be continuous with the P+ region 6. Next, as shown in FIG. 1(d), an N+ region 1 for the collector electrode is placed within the island region 5 for the NPN transistor.
At the same time, the resisting region 12 for the emitter region is formed by diffusion in the P region 10 for the base region, and at the same time, the lateral P region 12 is formed by diffusion.
A breakdown region 13 for a base electrode is formed by diffusion in the island region 7 for an NP transistor.

According to the bipolar transistor of FIG. 1(d) manufactured as described above, since it has the deep P+ diffusion region 6,8°9 that impinges on the buried-proof layer 2 with a fairly high impurity concentration, electric field concentration is reduced. The extension of the depletion layer in the lateral direction is suppressed, and the breakdown voltage is stably determined by the concentration of the N+ buried layer 2 and the P diffusion region 6.8.9. Therefore, the deep P diffusion region 6,
Even if the distance 4+12 between 8 and the P isolation region 4 is made small, that is, the element size is made small, a sufficient withstand voltage can be obtained.

Furthermore, since the NPN transistor has the deep P diffusion region 6 in a part of the base region, the ASO characteristics are improved.

Furthermore, since the lateral PNP transistor has deep P+ diffusion regions 8 and 9 in the emitter region and collector region, respectively, the hFK characteristics are improved.

Nao, N for the collector electrode of the NPN transistor.
The diffusion region 11 is N+ in order to lower the collector resistance.
In some cases, it is formed deep enough to reach the buried layer 2. In addition, in the VG sea urchin/1 shown in FIG. 1 (,), P
The + buried layer may not be provided when the N- epitaxial layer 3 is thin.

On the other hand, according to the method for manufacturing a transistor as described above, a P region 6 which becomes a part of the base region of the NPN transistor, P regions 8 and 9 which become the emitter region and collector region of the lateral PNP transistor, and a P+ isolation region 4
By simultaneously deeply diffusing and forming a bipolar transistor having the above-described features, it is possible to manufacture a bipolar transistor with the above-mentioned features through a simple process. Note that the deep P region 6,
8.9 If the diffusion of the P isolation region 4 and the subsequent P diffusion for the effective base region of the NPN transistor are performed by ion implantation, it becomes possible to align the cell 7 with the oxide film, further reducing the device size. can do.

Note that FIG. 2 shows a transistor according to another embodiment, and compared to the transistor shown in FIG. 1(d), (1) In the NPN transistor, a collector electrode is 1 region 21 is deeply diffused until it reaches the N+ buried layer 2, and a deep P+ diffused region 22, which becomes a part of the base region, is formed at a position surrounding the emitter region 12 as a countermeasure against ASO. )
Lateral PNP) Parasitic PNP in Orchid Nosta
In order to reduce the hFE of the transistor, the diffusion resistant region 23 for the base electrode is deep enough to reach the N+ buried layer 2.
The difference is that the emitter region and the collector region are formed so as to surround them, and the rest are the same, so they are similar to FIG. 1 (d).
) are given the same symbols as in the middle.

[Effects of the Invention] As described above, according to the present invention, the withstand voltage is stable, it is possible to increase the withstand voltage without increasing the element size, and the NPN transistor with good ASO characteristics or the lateral PNP transistor with good hFK characteristics It is possible to realize a semiconductor device having the following and a method for manufacturing the semiconductor device that can be manufactured by a simple process.

[Brief explanation of the drawing]

FIGS. 1(-) to 1(d) are views showing cross-sections of the wafer at the main parts of the bipolar transistor forming process in an embodiment of the semiconductor device manufacturing method of the present invention, and FIGS.
) shows one embodiment of the semiconductor device of the present invention;
The figure is a sectional view showing a semiconductor device according to another embodiment, and FIG. 3 is a sectional view showing a conventional semiconductor device. J...P-type substrate, 2...N+ buried layer, 3...N-
Evitayashal layer, 4...P separation region, 5...NP
N transistor island area, 6, 22...NPN)
Part of Tungista's base dream area, 7...Lateral P
NP transistor island region, 8, 9...lateral P
Emitter region and collector region of NP transistor, JO...effective base region of NPN transistor. Applicant's agent Patent attorney Takeshi Suzue Onden 1 Figure

Claims (3)

[Claims] (1) Part of the base region of an NPN transistor formed in an island region of an epitaxial growth layer on the surface of a P-type semiconductor substrate having an N^+ buried layer, or as the emitter region and collector region of a lateral PNP transistor.
A semiconductor device characterized in that the ^+ region is formed deep enough to reach the N^+ buried layer. (2) When forming an NPN transistor or a lateral PNP transistor on a wafer in which an N^+ buried layer and an epitaxial growth layer are formed on a P-type semiconductor substrate,
At the same time as forming the ^+ isolation region, a P^+ region is formed as part of the base region in the island region for the NPN transistor.
+ Deeply formed to reach the buried layer, or lateral P
1. A method of manufacturing a semiconductor device, comprising forming a P^+ region as an emitter region and a collector region deep within an island region for an NP transistor until it reaches an N^+ buried layer. (3) When forming an NPN transistor, the step of forming a P^+ region as a part of the base region and the step of forming the P^+ region as a part of the base region;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming a P region as an effective base region so as to be continuous with the ^+ region is performed by ion implantation.