WO2003054929A2 - Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat - Google Patents
Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat Download PDFInfo
- Publication number
- WO2003054929A2 WO2003054929A2 PCT/EP2002/012869 EP0212869W WO03054929A2 WO 2003054929 A2 WO2003054929 A2 WO 2003054929A2 EP 0212869 W EP0212869 W EP 0212869W WO 03054929 A2 WO03054929 A2 WO 03054929A2
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- iii
- substrate
- layers
- particular according
- Prior art date
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Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Definitions
- the invention relates to a method for depositing III-V semiconductor layers, for example gallium arsenide, aluminum arsenide, gallium indium arsenide or gallium indium aluminum arsenide phosphide, on a light III-V substrate, for example silicon, by introducing gaseous starting materials into the process chamber of a reactor.
- III-V semiconductor layers for example gallium arsenide, aluminum arsenide, gallium indium arsenide or gallium indium aluminum arsenide phosphide
- III-V layers are deposited according to the invention in the MOCVD
- silicon substrates have the advantage of being less expensive than III-V substrates and also suitable for integration into silicon component structures.
- One possibility of improving the layer quality is the deposition of thick semiconductor layers. However, this is limited by the thermal mismatch of the layers. These thermal mismatches lead to lattice tension and strong tension
- Another problem is the combination of Ill-V layer structures or electronic components made from such layer structures with silicon Components on a substrate.
- the invention is based on the object of crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the disadvantageous lattice stresses occurring.
- the invention is also based on the abe to combine on a Sustrat III-V components with silicon components.
- the object is achieved by the invention specified in the claims, claim 1 initially and essentially aimed at depositing a thin intermediate layer between two III-V layers at a reduced growth temperature.
- the reduced growth temperature for the intermediate layer should, if possible, be at least 100 ° C. below the growth temperature for the III-V layers.
- the lattice constant of the intermediate layer is preferably smaller than the lattice constant of the III-V layers.
- a multiplicity of intermediate layers, each separated by a III-V layer is deposited. Multiple thin intermediate layers are thus deposited on one III-N layer each.
- the intermediate layer is preferably deposited untensioned.
- the intermediate layer can contain boron or silicon.
- the thickness of the intermediate layer is in the annometer range.
- the III-N layers deposited between the intermediate layers can be considerably thicker. They can be a few micrometers thick.
- the III-V layer grows on the at low temperatures different intermediate layer on pseudomorph. This leads to tension.
- a compressive prestress is preferably achieved.
- the compressive pre-tension is achieved with the low-temperature intermediate layer.
- the method according to the invention enables the growth of essentially unstressed III-V semiconductor layers in the system (AI, Ga, In) (As, PN, Sb) by the growth of low-temperature layers between III-V layers, the low temperature always showing a clear temperature , is at least 100 ° C below the usual growth temperature.
- the preferred compressive tension is created by the tensile stress during cooling. In the case of an indium phosphite system, this can be carried out by means of a GaAs, AlAs, AlInAs or GalnAlAsPN low-temperature layers.
- aluminum arsenide, boron aluminum arsenide and also boron arsenite are considered as compressively tensioning low-temperature layers. However, it can also be used for materials in the nitridic system.
- the thermal stress but also the strain induced by lattice mismatch, can be reduced again and again to such an extent that layers of any thickness can be deposited, which are then essentially unstressed overall.
- the second task mentioned at the outset is achieved by first depositing a III-V semiconductor layer on a non-III-V substrate, in particular on a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor.
- This III-V semiconductor layer is deposited on a first substrate which has an orientation which is optimized for the deposition of the III-V layer.
- a GaN layer is particularly suitable for a silicon substrate with an (III) orientation.
- this semiconductor layer is detached from the substrate together with a thin film of the first substrate.
- the thickness of the detached film is, for example, 50 ⁇ m.
- the detached layer is applied to a second substrate together with the thin film of the first substrate.
- This second substrate can be a silicon substrate with a (100) orientation.
- the detached layer is preferably applied by gluing.
- a masking step can follow this bonding.
- it is provided that lateral areas of the applied layer are removed as far as the area of the second substrate. This removal is preferably done by etching.
- a layer sequence with silicon technology is then applied to the (100) silicon crystal which then forms the surface.
- These layers, which are adjacent to the III-V layer structures, can be insulation layers, electrically conductive layers or p- or n-doped silicon layers.
- the deposited III-N layer is preferably a gallium nitride layer.
- a seed layer made of gallium arsenide is first deposited on a silicon substrate.
- a gallium arsenide buffer layer is deposited on this seed layer at the typical growth temperatures known in the literature for the deposition of high quality gallium arsenide layers in the MOCVD or VPE process or MBE.
- a low-temperature intermediate layer is then deposited on this first III-V layer.
- the temperature inside the process chamber i.e. the substrate temperature
- the gases required for the growth of the intermediate layer are then introduced into the process chamber. Trimethylaluminium nium and arsine or a boron compound.
- the intermediate layer is deposited at this reduced temperature until the desired layer thickness, which is between 5 and 50 nm, is reached.
- the layer thickness is preferably between 10 and 20 nm.
- the temperature inside the process chamber is raised again. This is done by heating the substrate holder accordingly. Then another gallium arsenide layer is pseudomorphically deposited on the low-temperature intermediate layer. This gallium arsenide layer is considerably thicker than the low-temperature intermediate layer. Their thickness can be a few ⁇ m.
- a further low-temperature intermediate layer can be deposited on the last described gallium arsenide layer, which also has a smaller lattice constant than gallium arsenide.
- Gallium arsenide can be deposited again on this intermediate layer. Overall, the process leads to a thick gallium arsenide layer with few dislocations.
- FIG. 1 schematically shows in cross section a first substrate with an ( ⁇ ll) crystal orientation optimized for the deposition of a III-V layer
- 2 shows the substrate with III-V layers deposited thereon
- 3 shows the substrate with a III-V layer structure detached therefrom, together with a thin film of the first substrate
- FIG. 5 shows an illustration according to FIG. 4 after a lateral structuring by etching.
- a (III) silicon substrate is shown in regions and in cross section in FIG. 1.
- Two III-V layers 2, 3 are deposited on this silicon substrate (see FIG. 2) in the exemplary embodiment.
- These layers 2, 3 can be gallium arsenide, gallium nitride, indium phosphide or any other III-V composition.
- This layer sequence 2, 3 is removed together with a thin film V of the first substrate 1.
- the detached layer system V, 2, 3 is then glued onto a second substrate (see FIG. 4).
- the second substrate is preferably a (100) silicon substrate.
- the (100) silicon surface is suitable for the deposition of further, in particular silicon
- the intermediate product shown in FIG. 4 is structured laterally; this can be done, for example, by masking. Then the glued layer sequence Y, 2, 3 is etched away. This layer sequence is removed as far as into the second substrate 4, so that the exposed surface is in it etched area 5 is a (100) silicon surface on which CMOS structures can be deposited.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002366856A AU2002366856A1 (en) | 2001-12-21 | 2002-11-16 | Method for depositing iii-v semiconductor layers on a non-iii-v substrate |
JP2003555558A JP2006512748A (ja) | 2001-12-21 | 2002-11-16 | Iii−v半導体皮膜を非iii−v基板に沈積する方法 |
EP02790389A EP1459362A2 (de) | 2001-12-21 | 2002-11-16 | Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat |
KR10-2004-7009466A KR20040070239A (ko) | 2001-12-21 | 2002-11-16 | 비 ⅲ-ⅴ 기판상에 ⅲ-ⅴ 반도체층을 증착하는 방법 |
US10/872,905 US7078318B2 (en) | 2001-12-21 | 2004-06-21 | Method for depositing III-V semiconductor layers on a non-III-V substrate |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10163718 | 2001-12-21 | ||
DE10163718.7 | 2001-12-21 | ||
DE10206753.8 | 2002-02-19 | ||
DE10206753 | 2002-02-19 | ||
DE10219223A DE10219223A1 (de) | 2001-12-21 | 2002-04-30 | Verfahren zum Abscheiden von III-V-Halbleiterschichten auf einem Nicht-III-V-Substrat |
DE10219223.5 | 2002-04-30 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/872,905 Continuation US7078318B2 (en) | 2001-12-21 | 2004-06-21 | Method for depositing III-V semiconductor layers on a non-III-V substrate |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2003054929A2 true WO2003054929A2 (de) | 2003-07-03 |
WO2003054929A3 WO2003054929A3 (de) | 2004-04-08 |
WO2003054929B1 WO2003054929B1 (de) | 2004-06-10 |
Family
ID=27214692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/012869 WO2003054929A2 (de) | 2001-12-21 | 2002-11-16 | Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat |
Country Status (6)
Country | Link |
---|---|
US (1) | US7078318B2 (de) |
EP (1) | EP1459362A2 (de) |
JP (1) | JP2006512748A (de) |
AU (1) | AU2002366856A1 (de) |
TW (1) | TWI265558B (de) |
WO (1) | WO2003054929A2 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7244630B2 (en) * | 2005-04-05 | 2007-07-17 | Philips Lumileds Lighting Company, Llc | A1InGaP LED having reduced temperature dependence |
US8012592B2 (en) * | 2005-11-01 | 2011-09-06 | Massachuesetts Institute Of Technology | Monolithically integrated semiconductor materials and devices |
US20070262051A1 (en) * | 2006-05-12 | 2007-11-15 | Advanced Chip Engineering Technology Inc. | Method of plasma etching with pattern mask |
US8362503B2 (en) | 2007-03-09 | 2013-01-29 | Cree, Inc. | Thick nitride semiconductor structures with interlayer structures |
US7825432B2 (en) * | 2007-03-09 | 2010-11-02 | Cree, Inc. | Nitride semiconductor structures with interlayer structures |
US20080314311A1 (en) * | 2007-06-24 | 2008-12-25 | Burrows Brian H | Hvpe showerhead design |
US20090149008A1 (en) * | 2007-10-05 | 2009-06-11 | Applied Materials, Inc. | Method for depositing group iii/v compounds |
CN101802254B (zh) | 2007-10-11 | 2013-11-27 | 瓦伦斯处理设备公司 | 化学气相沉积反应器 |
US8183132B2 (en) * | 2009-04-10 | 2012-05-22 | Applied Materials, Inc. | Methods for fabricating group III nitride structures with a cluster tool |
US8491720B2 (en) * | 2009-04-10 | 2013-07-23 | Applied Materials, Inc. | HVPE precursor source hardware |
WO2010124261A2 (en) * | 2009-04-24 | 2010-10-28 | Applied Materials, Inc. | Substrate pretreatment for subsequent high temperature group iii depositions |
US8110889B2 (en) * | 2009-04-28 | 2012-02-07 | Applied Materials, Inc. | MOCVD single chamber split process for LED manufacturing |
JP2012525718A (ja) * | 2009-04-29 | 2012-10-22 | アプライド マテリアルズ インコーポレイテッド | HVPEにおいてその場プレ−GaN堆積層を形成する方法 |
DE102009051520B4 (de) | 2009-10-31 | 2016-11-03 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit Schichtstrukturen zur Integration von III-V Halbleiterbauelementen |
FR2953328B1 (fr) * | 2009-12-01 | 2012-03-30 | S O I Tec Silicon On Insulator Tech | Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques |
US20110256692A1 (en) | 2010-04-14 | 2011-10-20 | Applied Materials, Inc. | Multiple precursor concentric delivery showerhead |
DE102010046792A1 (de) | 2010-09-28 | 2012-03-29 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und Verfahren zu dessen Herstellung |
TWI534291B (zh) | 2011-03-18 | 2016-05-21 | 應用材料股份有限公司 | 噴淋頭組件 |
US9299560B2 (en) * | 2012-01-13 | 2016-03-29 | Applied Materials, Inc. | Methods for depositing group III-V layers on substrates |
WO2013120960A1 (de) | 2012-02-15 | 2013-08-22 | Ursula Kastner | Vorrichtung und verfahren zur analyse und transfektion von zellen oder partikeln |
US8603898B2 (en) | 2012-03-30 | 2013-12-10 | Applied Materials, Inc. | Method for forming group III/V conformal layers on silicon substrates |
US9941295B2 (en) | 2015-06-08 | 2018-04-10 | Sandisk Technologies Llc | Method of making a three-dimensional memory device having a heterostructure quantum well channel |
US9425299B1 (en) | 2015-06-08 | 2016-08-23 | Sandisk Technologies Llc | Three-dimensional memory device having a heterostructure quantum well channel |
US20160376191A1 (en) * | 2015-06-24 | 2016-12-29 | United States Gypsum Company | Composite gypsum board and methods related thereto |
US9721963B1 (en) | 2016-04-08 | 2017-08-01 | Sandisk Technologies Llc | Three-dimensional memory device having a transition metal dichalcogenide channel |
WO2017222513A1 (en) * | 2016-06-22 | 2017-12-28 | Intel Corporation | Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors |
US9818801B1 (en) | 2016-10-14 | 2017-11-14 | Sandisk Technologies Llc | Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof |
KR102369676B1 (ko) | 2017-04-10 | 2022-03-04 | 삼성디스플레이 주식회사 | 표시 장치의 제조장치 및 표시 장치의 제조방법 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0377940A2 (de) * | 1989-01-13 | 1990-07-18 | Kabushiki Kaisha Toshiba | Verbindungshalbleiter, denselben anwendendes Halbleiter-Bauelement und Herstellungsverfahren des Halbleiter-Bauelementes |
EP0468814A2 (de) * | 1990-07-27 | 1992-01-29 | Kabushiki Kaisha Toshiba | Ultraviolett-Halbleiterlaser und Verfahren zur Herstellung desselben |
WO2000033364A1 (en) * | 1998-11-27 | 2000-06-08 | Agilent Technologies, Inc. | Epitaxial aluminium-gallium nitride semiconductor substrate |
US6242324B1 (en) * | 1999-08-10 | 2001-06-05 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating singe crystal materials over CMOS devices |
WO2001043174A2 (en) * | 1999-12-13 | 2001-06-14 | North Carolina State University | Fabrication of gallium nitride layers on textured silicon substrates |
US20010009134A1 (en) * | 1998-10-15 | 2001-07-26 | Lg Electronics Inc. | GaN system compound semiconductor and method for growing crystal thereof |
US6303405B1 (en) * | 1998-09-25 | 2001-10-16 | Kabushiki Kaisha Toshiba | Semiconductor light emitting element, and its manufacturing method |
WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
WO2001095380A1 (fr) * | 2000-06-09 | 2001-12-13 | Centre National De La Recherche Scientifique | Procede de preparation d'une couche de nitrure de gallium |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268327A (en) * | 1984-04-27 | 1993-12-07 | Advanced Energy Fund Limited Partnership | Epitaxial compositions |
US4891329A (en) * | 1988-11-29 | 1990-01-02 | University Of North Carolina | Method of forming a nonsilicon semiconductor on insulator structure |
JP2669368B2 (ja) * | 1994-03-16 | 1997-10-27 | 日本電気株式会社 | Si基板上化合物半導体積層構造の製造方法 |
US5838029A (en) * | 1994-08-22 | 1998-11-17 | Rohm Co., Ltd. | GaN-type light emitting device formed on a silicon substrate |
JP3491492B2 (ja) * | 1997-04-09 | 2004-01-26 | 松下電器産業株式会社 | 窒化ガリウム結晶の製造方法 |
US5966622A (en) * | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
-
2002
- 2002-11-16 WO PCT/EP2002/012869 patent/WO2003054929A2/de not_active Application Discontinuation
- 2002-11-16 EP EP02790389A patent/EP1459362A2/de not_active Withdrawn
- 2002-11-16 AU AU2002366856A patent/AU2002366856A1/en not_active Abandoned
- 2002-11-16 JP JP2003555558A patent/JP2006512748A/ja active Pending
- 2002-12-12 TW TW091135979A patent/TWI265558B/zh not_active IP Right Cessation
-
2004
- 2004-06-21 US US10/872,905 patent/US7078318B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0377940A2 (de) * | 1989-01-13 | 1990-07-18 | Kabushiki Kaisha Toshiba | Verbindungshalbleiter, denselben anwendendes Halbleiter-Bauelement und Herstellungsverfahren des Halbleiter-Bauelementes |
EP0468814A2 (de) * | 1990-07-27 | 1992-01-29 | Kabushiki Kaisha Toshiba | Ultraviolett-Halbleiterlaser und Verfahren zur Herstellung desselben |
US6303405B1 (en) * | 1998-09-25 | 2001-10-16 | Kabushiki Kaisha Toshiba | Semiconductor light emitting element, and its manufacturing method |
US20010009134A1 (en) * | 1998-10-15 | 2001-07-26 | Lg Electronics Inc. | GaN system compound semiconductor and method for growing crystal thereof |
WO2000033364A1 (en) * | 1998-11-27 | 2000-06-08 | Agilent Technologies, Inc. | Epitaxial aluminium-gallium nitride semiconductor substrate |
US6242324B1 (en) * | 1999-08-10 | 2001-06-05 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating singe crystal materials over CMOS devices |
WO2001043174A2 (en) * | 1999-12-13 | 2001-06-14 | North Carolina State University | Fabrication of gallium nitride layers on textured silicon substrates |
WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
WO2001095380A1 (fr) * | 2000-06-09 | 2001-12-13 | Centre National De La Recherche Scientifique | Procede de preparation d'une couche de nitrure de gallium |
Also Published As
Publication number | Publication date |
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TW200301515A (en) | 2003-07-01 |
AU2002366856A8 (en) | 2003-07-09 |
US20050026392A1 (en) | 2005-02-03 |
WO2003054929B1 (de) | 2004-06-10 |
JP2006512748A (ja) | 2006-04-13 |
US7078318B2 (en) | 2006-07-18 |
EP1459362A2 (de) | 2004-09-22 |
WO2003054929A3 (de) | 2004-04-08 |
TWI265558B (en) | 2006-11-01 |
AU2002366856A1 (en) | 2003-07-09 |
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