WO2003043219A1 - Appareil et procede d'estimation de serie a plus grande vraisemblance - Google Patents

Appareil et procede d'estimation de serie a plus grande vraisemblance Download PDF

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Publication number
WO2003043219A1
WO2003043219A1 PCT/JP2002/011920 JP0211920W WO03043219A1 WO 2003043219 A1 WO2003043219 A1 WO 2003043219A1 JP 0211920 W JP0211920 W JP 0211920W WO 03043219 A1 WO03043219 A1 WO 03043219A1
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WIPO (PCT)
Prior art keywords
expected value
bit
calculating
maximum likelihood
delayed wave
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PCT/JP2002/011920
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English (en)
Japanese (ja)
Inventor
Ryutaro Yamanaka
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Matsushita Electric Industrial Co., Ltd.
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Publication of WO2003043219A1 publication Critical patent/WO2003043219A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03292—Arrangements for operating in conjunction with other apparatus with channel estimation circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03375—Passband transmission
    • H04L2025/03401—PSK

Definitions

  • the present invention relates to a maximum likelihood sequence estimation device and a maximum likelihood sequence estimation method, and more particularly to a maximum likelihood sequence estimation device and a maximum likelihood sequence estimation method used in a mobile communication device such as a mobile station device.
  • the size and weight of the mobile station device can be reduced.
  • the number of transistors used is reduced, the chip area is reduced, and the unit cost of the chip can be kept low. Also, if the number of transistors used is small, power consumption can be reduced and battery life can be maintained for a long time.
  • a maximum likelihood sequence estimation method is sometimes applied as a method for adaptively equalizing a received signal in order to improve transmission quality.
  • This maximum likelihood sequence estimation apparatus performs a filtering process using a channel estimation coefficient (type coefficient) on each bit of a state indicating a state of a communication channel to create a repliability of a received signal, and The branch metric, which is the square error between the received signal and the replica, is calculated. Then, add / compare / select: ACS) calculation to calculate the path metric, which is the cumulative value of the branch metric, and select the surviving path. As a result, the adaptive equalization of the received signal is performed, and the path metric stored for each state is updated. Since the path metric is stored for each state, when the N-channel channel estimation coefficient is used, in other words, the delayed wave component of 1 to (N-1) symbol delay included in the received signal is compensated. In this case, when performing modulation such as BPSK or GMSK where the modulation level is 2, it is necessary to store 2N-1 path metrics.
  • modulation such as BPSK or GMSK where the modulation level is 2N-1 path metrics.
  • the number of taps normally required is N
  • a delayed wave component of 1 to N symbol delay is to be compensated due to, for example, a design change of a mobile communication system.
  • the (N + 1) type is required, the number of states is doubled and the number of path metrics that must be stored doubles, so the memory size for storing path metrics is doubled. Increases. Therefore, there is a problem that the number of transistors integrated in the LSI increases and the chip area increases. Disclosure of the invention
  • An object of the present invention is to perform adaptive equalization of a received signal while minimizing the increase in circuit scale even when the number of necessary taps increases.
  • the subject of the present invention is that when an (N + 1) -type channel estimation coefficient is used, an expected value for one additional tap is calculated by another circuit, and the same calculation as that for the N-type channel estimation coefficient is performed. Is performed in two stages, the first half 2N-1 state and the second half 2N-1 state. In addition, when the channel estimation coefficient is N sets, the channel estimation coefficient of this separate circuit is set to 0 so as not to affect the overall calculation result.
  • the maximum likelihood sequence estimation apparatus includes: a storage unit that stores a path metric; and (N + 1) pieces of (N + 1) -th to N-th delay waves included in the received signal.
  • First calculating means for calculating an expected value of a bit corresponding to the N delayed wave components of the delayed wave components; and a first calculating means corresponding to the remaining one delayed wave component of the (N + 1) delayed wave components
  • a second calculating means for calculating an expected value of each value of the bit, and for each expected value calculated by the second calculating means, adding the expected value and the expected value calculated by the first calculating means.
  • Generating means for generating a replica of the received signal; a received signal; a replica generated by the generating means; and a maximum likelihood sequence estimating means for estimating the maximum likelihood sequence of the received signal based on the path metric stored in the storage means.
  • a mobile station device is a mobile station device having a maximum likelihood sequence estimation device, wherein the maximum likelihood sequence estimation device has a storage unit for storing a path metric, First calculating means for calculating an expected value of a bit corresponding to N delayed wave components among (N + 1) delayed wave components from the 0 delayed wave to the N delayed wave included, and the (N + 1) ) Second delay means for calculating an expected value of each value of a bit corresponding to the remaining one of the delayed wave components, and for each expected value calculated by the second calculating means.
  • the base station device is a base station device having a maximum likelihood sequence estimation device, wherein the maximum likelihood sequence estimation device stores a path metric, First calculating means for calculating an expected value of a bit corresponding to N delayed wave components of (N + 1) delayed wave components from 0 delayed wave to N delayed wave included in the signal; + 1) second calculating means for calculating an expected value of each value of a bit corresponding to the remaining one delayed wave component among the delayed wave components; and a second calculating means for each expected value calculated by the second calculating means.
  • the maximum likelihood sequence estimation method comprises: N delay waves of (N + 1) delay wave components from 0 delay waves to N delay waves included in a received signal.
  • the maximum likelihood sequence estimation program is a maximum likelihood sequence estimation program executed by a computer, wherein the computer outputs the maximum likelihood sequence estimation program from a 0-delay wave included in a received signal to an N-delay A first calculation step of calculating an expected value of a bit corresponding to N delayed wave components of the (N + 1) delayed wave components up to the wave; and (N + 1) delayed wave components A second calculating step of calculating an expected value of each value of a bit corresponding to the remaining one delayed wave component, and calculating the expected value and the first calculating step for each expected value calculated in the second calculating step Generating a replica of the received signal by adding the expected value to the received signal, a maximum likelihood sequence of the received signal based on the received signal, the replica generated in the generating step, and a path metric stored in advance. And a step of estimating the maximum likelihood sequence to be estimated.
  • FIG. 1 is a block diagram showing a configuration of a maximum likelihood sequence estimation device according to one embodiment of the present invention
  • FIG. 2 is a diagram showing state transitions in the case of three taps of the maximum likelihood sequence estimation device shown in FIG. 1,
  • FIG. 3 is a diagram showing correspondences between states, read and write addresses, and estimated transmission signal sequences in the case of three taps of the maximum likelihood sequence estimation device shown in FIG.
  • FIG. 4 is a diagram showing state transitions of the maximum likelihood sequence estimation device shown in FIG. 1 in the case of 4 taps, and
  • FIG. 5 is a diagram showing correspondences between states, read and write addresses, and estimated transmission signal sequences in the case of the maximum likelihood sequence estimation device shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a diagram showing a configuration of a maximum likelihood sequence estimation device according to one embodiment of the present invention.
  • an (N-1) -bit signal generation unit 1000 generates a signal sequence of all the patterns that an (N-1) -bit signal can take.
  • the 1-bit signal generation unit 200 simultaneously generates two possible values of a 1-bit signal, that is, “0” and “1”.
  • the binary generated by the 1-bit signal generation unit 200 corresponds to the delayed wave component assumed to be transmitted the oldest among the delayed wave components included in the received signal.
  • the channel estimation coefficient obtaining unit 300 converts each bit generated by the (N-1) bit signal generating unit 100 and “0” and “1” generated by the 1-bit signal generating unit 200 Obtain the corresponding channel estimation coefficients.
  • the expected value generation unit 400 multiplies the channel estimation coefficient corresponding to each bit of the signal generated by the (N-1) bit signal generation unit 100 and the 1-bit signal generation unit 200 by By adding the results, the direct wave component in the case of using the channel estimation coefficient of N Generate expected value.
  • extended expected value generating section 500 generates an expected value when an additional delayed wave component for one tap is received.
  • Adders 600-1 and 600-2 add the expected value generated by expected value generating section 400 and the expected value generated by extended expected value generating section 500 to generate a replica of the received signal.
  • Maximum likelihood sequence estimation section 700 uses the received signal and a replica of the received signal to perform adaptive equalization of the received signal by the video and video algorithm, and updates the path metric.
  • the storage section 800 has storage areas corresponding to each of the (N-1) -bit signals generated by the (N-1) -bit signal generation section 100, and each storage area has (N-1) -bit data. The path metric corresponding to this signal is stored.
  • the (N-1) bit signal generator 100 is composed of digital signal generators 110-1 to 110- (N-1), and each digital signal generator 110-1 to L10- (N-1 ) Generates “0” or “1”, so that the (N ⁇ 1) -bit signal generation unit 100 generates 2 N ⁇ 1 signal sequences.
  • the channel estimation coefficient obtaining unit 300 includes individual channel estimation coefficient obtaining units 310-1 to 310— (N ⁇ 1) and an individual channel estimation coefficient obtaining unit 320.
  • the individual channel estimation coefficient acquisition units 310-1 to 310- (N-1) calculate the channel estimation coefficients corresponding to the signals generated by the digital signal generators 110-1 to 110- (N-1), respectively.
  • the individual channel estimation coefficient acquiring unit 320 acquires the channel estimation coefficient corresponding to the binary value generated by the 1-bit signal generation unit 200.
  • the expected value generation unit 400 includes multipliers 410—1 to 410— (N—1), multipliers 420—1, 420—2, an adder 430, and adders 440-1 and 440-2.
  • the multipliers 410—1 to 410— (N ⁇ 1) are respectively associated with the corresponding digital signal generators 110—1 to 110— (N—1) and the individual channel estimation coefficient acquisition unit 310-1-310— (N— 1) 1-bit signal output from And the channel estimation coefficient.
  • the multiplier 4 2 0—1 multiplies “0” of the value generated by the 1-bit signal generation unit 2 0 0 by the channel estimation coefficient obtained by the individual channel estimation coefficient obtaining unit 3 2 0, and performs multiplication.
  • the unit 420-2 multiplies "1" of the value generated by the 1-bit signal generation unit 200 by the channel estimation coefficient obtained by the dedicated channel estimation coefficient obtaining unit 320. .
  • the adder 430 adds all the results of the multiplication by the multipliers 411 to 411— (N-1).
  • Adder 4440—1 adds the addition result of adder 4330 and the multiplication result of multiplier 4220—1, and transmits the oldest delayed wave component among the received signals. If the component assumed to be zero is “0”, it generates an expected value when the direct wave component and the delayed wave component are received (hereinafter, referred to as “first expected value”).
  • first expected value is the sum of the addition result of the adder 4330 and the multiplication result of the multiplier 4220-2, and is assumed to be the oldest transmitted delay wave component in the received signal.
  • second expected value an expected value when the direct wave component and the delayed wave component are received
  • the extended expected value generation unit 500 includes a digital signal generator 5100, a channel estimation coefficient acquisition unit 5200, and a multiplier 5330.
  • Digital signal generator 510 generates a 1-bit signal corresponding to one delayed wave component included in the received signal.
  • the channel estimation coefficient acquisition unit 520 acquires a channel estimation coefficient corresponding to the signal generated by the digital signal generator 510.
  • the multiplier 530 multiplies the 1-bit signal output from the digital signal generator 510 and the channel estimation coefficient acquisition unit 520 by the channel estimation coefficient.
  • N type 1 to (N ⁇ 1) symbol delay components to be compensated
  • case of (N + 1) tap 1 to (N + 1) symbol delay components to be compensated
  • the (N-1) bit signal generated by the (N-1) bit signal generator 100 Channel estimation coefficients and the channel estimation coefficients corresponding to each bit of the (N-1) -bit signal obtained by the individual channel estimation coefficient acquisition unit 3 1 0—1 to 3 1 O ⁇ (N ⁇ l) Are multiplied by multipliers 4 1 0—1 to 4 10— (N—1), and the result of the multiplication is added by adder 430.
  • “0” and “1” generated by the 1-bit signal generation unit 200 and the channel estimation coefficients acquired by the individual channel estimation coefficient acquisition unit 320 are respectively multipliers 4 2 0—1, Multiplied by 4 2 0-2
  • the addition result of the adder 4330 and the multiplication result of the multiplier 4220-1 are added by the adder 4440-1, and "0" generated by the 1-bit signal generation unit 200 is added.
  • the expected value of the corresponding received signal that is, the expected value (first expected value) when the component assumed to be transmitted the oldest among the delayed wave components included in the received signal is “0” is calculated. Is done.
  • the addition result of the adder 4330 and the multiplication result of the multiplier 4220-2 are added by the adder 4440-2, and "1" generated by the 1-bit signal generation unit 200 is added to "1".
  • the expected value of the corresponding received signal that is, the expected value (second expected value) when the component assumed to be transmitted the oldest among the delayed wave components included in the received signal is “1” is calculated Is done.
  • the channel estimation coefficient acquired by channel estimation coefficient acquiring section 520 is set to 0 so that the output of extended expected value generating section 500 is set to 0.
  • the first expected value and the second expected value are added to the output 0 of the extended expected value generation unit 500 by the adders 600-0-1 and 600-0-2, and the first expected value and the second expected value are added. Two replicas of the received signal corresponding to the second expected value are generated.
  • the maximum likelihood sequence estimating section 700 calculates a branch metric which is a vector difference between the received signal and a replica of the received signal. Also, of the past path metrics stored in the storage unit 800, two paths stored in the storage area corresponding to the signal sequence (state) generated by the (N-1) -bit signal generation unit. The metric is output to maximum likelihood sequence estimation section 700. And the maximum likelihood Sequence estimation section 700 adds the corresponding output path metric and the calculated branch metric, and selects the smaller one of the two addition results and stores it as a new path metric in storage section 800. 0 is stored in the corresponding storage area. Also, the surviving path is determined from the selected path metric, and adaptive equalization of the received signal is performed.
  • the above process is repeated for all possible patterns of the (N-1) -bit signal sequence generated by the (N-1) -bit signal generation unit 100, and 2N_l (N — 1)
  • the path metric stored in the storage unit 800 is updated for each bit signal sequence (state).
  • the storage unit 800 at the start of the processing stores a path metric corresponding to a case where the one-bit signal generated by the digital signal generator 510 is “0” in an external device such as a DSP (not shown). It is assumed that it is called from the device.
  • (N + 1) tap as in the case of N taps, (N-1) bit signal generation unit 100, 1-bit signal generation unit 200, channel estimation coefficient acquisition unit 30
  • the first expected value and the second expected value corresponding to the direct wave component and the (N ⁇ 1) delayed wave components are generated by 0 and the expected value generation unit 400.
  • the digital signal generator 5110 generates a 1-bit signal “0” corresponding to the delayed wave component of one symbol delay, and the generated 1-bit signal and the channel estimation coefficient obtaining unit 5200
  • the obtained channel estimation coefficient is multiplied by a multiplier 530.
  • the result of the multiplication is output from extended expected value generating section 500 as an extended expected value corresponding to a delayed wave component of one symbol delay.
  • the first expected value, the second expected value, and the extended expected value are added by adders 600-1 and 600-2, respectively, to generate replicas of the two received signals.
  • adaptive equalization of the received signal is performed by maximum likelihood sequence estimation section 700, and the path metric stored in storage section 800 is updated.
  • the above process is performed with the signal generated by the digital signal generator 510 fixed at “0” and the (N ⁇ 1) bit signal generated by the (N ⁇ 1) bit signal generator 100 This is repeated for all possible patterns of the signal sequence. Thereby, the path metric stored in the storage unit 800 is updated for each of the 2 N ⁇ 1 (N ⁇ 1) bit signal sequences.
  • the updated path metric is output from the storage unit 800 to an external device such as a DSP (not shown) and stored, and at the same time, the storage unit 800 is generated by the digital signal generator 501.
  • the corresponding path metric is called from a DSP (not shown) or the like.
  • the signal generated by the digital signal generator 5100 fixed to "1"
  • the signal is generated by the (N-1) -bit signal generator 100 (N-1) in the same manner as described above.
  • Adaptive equalization of the received signal is performed for all the patterns that the bit signal sequence can take, and the path metric stored in the storage unit 800 is updated.
  • Figure 2 is a diagram showing all paths that can transition from the state in the previous process (corresponding to node A) to the state in the current process (corresponding to node B) in the case of three taps.
  • the state that can transition to the state “0 0” at the node B is the state “0 0” or the state “01” of the node A.
  • the transition from state “0 0” to state “0 0” occurs when the delay wave component of the two-symbol delay included in the received signal is “0”, from state “0 1” to state “0 0”.
  • a transition is made when the delay wave component of the two-symbol delay included in the received signal is “1”.
  • the multiplication results of multipliers 410-1 and 410-2 are added by adder 430, and the addition result of adder 430 and the multiplication results of multipliers 420-1 and 420-2 are added to adders 440-1 respectively. , 440-2 to generate the first expected value and the second expected value.
  • the channel estimation coefficient acquired by the channel estimation coefficient acquisition unit 520 is set to 0, and the first expected value and the second expected value are added to 0 by the adders 600-1 and 600-2. Are added to generate the repli- cation power of the two received signals.
  • the storage areas “00” and “01” corresponding to the signal sequence “00” generated by the (N ⁇ 1) -bit signal generation unit 100 store the data.
  • the obtained path metric is read out to maximum likelihood sequence estimation section 700.
  • the maximum likelihood sequence estimation section 700 adds the difference between the replica corresponding to the first expected value and the received signal to the path metric read from address “00”, and at the same time, adds the replica corresponding to the second expected value to the replica.
  • the difference from the received signal is added to the path metric read from the address “01”, the addition results are compared, the smaller one is selected, and “00” in the storage unit 800 is selected as a new path metric. It is stored at the address. Also, by selecting the addition result, the surviving path that transits to the state “00” is determined. The above operation is performed for state “01”, state “10”, and state “1 1”. 0
  • the state of the node B generated by the (N-1) -bit signal generation unit 100 the read address of the storage unit 800 that reads the path metric corresponding to each state, and the updated path Storage unit for writing metrics 8 0
  • Fig. 3 shows a summary of the write address of 0 and the estimated transmission signal sequence when transitioning from node A to node B.
  • the storage unit 800 at the start of the processing includes a path metric corresponding to a case where the one-bit signal generated by the digital signal generator 510 is “0”, such as a DSP (not shown). It is assumed that it is called from an external device.
  • a path metric corresponding to a case where the one-bit signal generated by the digital signal generator 510 is “0”, such as a DSP (not shown). It is assumed that it is called from an external device.
  • Fig. 4 is a diagram showing all paths that can transition from the state in the previous process (corresponding to node A) to the state in the current process (corresponding to node B) in the case of 4 taps.
  • the most significant and least significant two bits of each state of node B correspond to the signal sequence generated by the (N-1) -bit signal generation unit 100, and the middle 1 The bits correspond to the signals generated by the digitized signal generator 5110.
  • a state that can transition to the state “0 0 0” at the node B is the state “0 0 0” or the state “0 0 1” of the node A.
  • the transition from state “0 0 0” to state “0 0 0” occurs when the delay wave component of the 3-symbol delay included in the received signal is “0”, from state “0 0 1” to state “0 0”.
  • the transition to “0” occurs when the delay component of the 3-symbol delay included in the received signal is “1”.
  • a signal indicating the middle one bit of each state generated by the digital signal generator 510 is fixed to “0”, and For the two most significant bits of the state, The same operation as in the above case is performed, and the state “0 0 0”, the state “0 0 1”, the state “1 0 0”, and the state “1 0 1” of the node B are stored in the storage means 800. Update the path metric and determine the surviving path.
  • the updated path metric is output from the storage unit 800 to an external device such as a DSP (not shown), and a 1-bit signal generated by the digital signal generator 510 for the middle of each state is output. If it is “1”, the corresponding path metric is called into the storage unit 800.
  • an external device such as a DSP (not shown)
  • a 1-bit signal generated by the digital signal generator 510 for the middle of each state is output. If it is “1”, the corresponding path metric is called into the storage unit 800.
  • the 1-bit signal generated by the digital signal generator 510 is used as a unit of processing, and the surviving path is determined by dividing the processing into the first half and the second half, thereby performing adaptive equalization of the received signal.
  • FIG. 5 shows a summary of the read address of 0, the write address of the storage unit 800 to which the updated path metric is written, and the estimated transmission signal sequence when transitioning from node A to node B.
  • the maximum likelihood sequence estimating apparatus of the present embodiment in the case of (N + 1) sunset, the replica of the received signal By dividing the generation into the first half and the second half, and repeating the process of calculating the expected value for N steps, the number of necessary taps increases without increasing the number of path metrics that need to be stored during processing. Even in this case, adaptive equalization of the received signal can be performed while minimizing the increase in the circuit scale.
  • the circuit size can be increased by appropriately increasing the extended expected value generation unit 500 when two or more taps are added.
  • the adaptive equalization of the received signal can be performed while minimizing the increase in the signal.
  • the maximum likelihood sequence estimation device of the present invention can be used for a mobile station device and a base station device in wireless mobile communication.
  • the present invention can be applied to a maximum likelihood sequence estimation device and a maximum likelihood sequence estimation method, and particularly to a maximum likelihood sequence estimation device and a maximum likelihood sequence estimation method used in a mobile communication device such as a mobile station device. Can be.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La présente invention concerne un appareil et un procédé d'estimation de série à plus grande vraisemblance. Ledit appareil et ledit procédé permettent de mettre en oeuvre l'adaptation d'un signal de réception tout en supprimant l'augmentation de la taille de circuit même lorsque le nombre de dérivations nécessaires est augmenté. Une unité de génération de valeurs attendues (400) multiplie un coefficient d'estimation de voie correspondant à chacun des bits des signaux générés par une unité de génération de signaux à (N - 1) bits (100) et une unité de génération de signaux à 1 bit (200) et additionne les résultats de la multiplication, générant ainsi une valeur attendue lorsqu'une composante d'onde directe et une composante d'onde de retard pour les N dérivations sont reçues. Lorsqu'un coefficient d'estimation de voie de dérivation (N + 1) est utilisé, une unité de génération de valeurs attendues étendues (500) génère une valeur attendue lorsqu'une composante d'onde de retard d'une dérivation ajoutée est reçue. Des sommateurs (600-1, 600-2) additionnent les valeurs attendues générées et génèrent une réplique d'un signal de réception. Une unité d'estimation de série à plus grande vraisemblance (700) met en oeuvre l'adaptation du signal de réception à l'aide du signal de réception et de la réplique du signal de réception.
PCT/JP2002/011920 2001-11-16 2002-11-15 Appareil et procede d'estimation de serie a plus grande vraisemblance WO2003043219A1 (fr)

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JPH05130079A (ja) * 1991-10-31 1993-05-25 Nec Corp 系列推定方法および装置
JPH09266458A (ja) * 1996-03-27 1997-10-07 Kokusai Electric Co Ltd 適応等化器
JPH11289258A (ja) * 1997-07-23 1999-10-19 Mitsubishi Electric Corp 系列推定方法及び系列推定装置
JP2003032153A (ja) * 2001-07-18 2003-01-31 Matsushita Electric Ind Co Ltd 最尤系列推定法を用いた演算処理装置

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