Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/48—After-treatment of electroplated surfaces
  • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole

Definitions

• the present invention relates to a method of manufacturing semiconductor devices with accurately formed sub-micron features.
• the present invention has particular applicability in manufacturing high density, multi-level flash-memory semiconductor devices with reliable, low resistance contacts/vias.
• Conventional semiconductor devices comprise a semiconductor substrate in which various elements are formed, such as transistors, and a plurality of overlying sequentially formed interlayer dielectrics and conductive patterns in which an interconnect system is formed comprising conductive lines.
• conductive patterns on different levels i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region.
• a conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive level comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques and filling the opening with a conductive material. Excess conductive material or the overburden on the surface of the ILD is typically removed by chemical- mechanical polishing (CMP).
• CMP chemical- mechanical polishing
• One such method is known damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with an upper conductive line.
• An advantage of the present invention is a method of manufacturing a semiconductor device having features in the deep sub-micron regime with highly reliability vias and contacts exhibiting low and stable contact resistance distribution and improved electromigration performance.
• a method of manufacturing a semiconductor device comprising: forming an opening in a dielectric layer; depositing tungsten (W) to fill the opening; and laser thermal annealing the W in the opening.
• Embodiments of the present invention comprise forming an opening in an oxide dielectric layer, such as a boron-phosphorus-doped silicated glass (BPSG) or a composite oxide layer comprising a BPSG layer with a silicon oxide layer derived from tetraethyl orthosilicate (TEOS) thereon, depositing an initial barrier layer of titanium (Ti) and then depositing at least one layer, e.g., three layers, of titanium nitride on the titanium layer. The opening is then filled with W.
• an oxide dielectric layer such as a boron-phosphorus-doped silicated glass (BPSG) or a composite oxide layer comprising a BPSG layer with a silicon oxide layer derived from tetraethyl orthosilicate (TEOS) thereon
• TEOS tetraethyl orthosilicate
• laser thermal annealing is conducted by impinging a laser light beam on the deposited W directed at the filled opening, typically at a radiant fluence of about 0.78 to about 1.10 joules/cm 2 , for a brief period of time, e.g., about 10 to about 100 nanoseconds, in nitrogen (N 2 ), to elevate the temperature of the W in the opening thereby melting and reflowing the W in the filled opening, e.g., at a temperature of about 3,000°C to about 3,600°C.
• Chemical mechanical polishing CMP is then conducted.
• CMP is conducted prior to laser thermal annealing.
• FIG. 1 schematically illustrates a W plug void problem addressed and solved by the present invention.
• FIGS. 2 through 5 schematically illustrate sequential phases of a method in accordance ith an embodiment of the present invention.
• Figs. 6 through 8 schematically illustrate sequential phases of a method in accordance with another embodiment of the present invention.
• the present invention addresses and solves W contact/via reliability problems stemming from the undesirable formation of holes, with attendant high and unstable contact resistance distribution and poor electromigration performance, particularly as device geometries are reduced into the deep sub-micron regime.
• the width of a contact/via opening is reduced to about 0.225 to about 0.257 microns, e.g., about 0.25 microns, and the depth of the contact/via opening is extended to about 0.81 to about 0.99 micron, e.g., about 0.90 micron, or greater, and aspect ratios approach 4:1 and greater, it becomes extremely difficult to fill the contact/via openings without generating voids.
• the present invention addresses and solves that problem by proceeding in a conventional manner to fill the contact/via openings having high aspect ratios in a conventional manner to form a W plug having voids.
• the present invention departs from conventional practices by providing efficient methodology enabling the removal of the voids formed upon filling a contact/via opening having a high aspect ratio, thereby reducing contact resistance, providing a tighter resistance distribution and improving electromigration performance.
• a contact/via opening is formed in a dielectric layer, such as an oxide layer, e.g., BPSG or silicon oxide derived from TEOS.
• a barrier layer composite is then formed lining the opening.
• an initial thin Ti layer is deposited to line the opening and a titanium nitride layer is deposited on the initial Ti layer. W is then deposited in a conventional manner forming an overburden. At this point the W filling the contact/via opening contains undesirable voids or pores adversely impacting device performance, including electromigration performance.
• the W filling the opening is subjected to laser thermal annealing by impinging a pulsed laser light beam directed toward the W in the opening, as at a radiant fluence of about 0.78 to about 1.10 joules/cm 2 , while flowing N 2 as at a flow rate of about 200 to about 2,000 seem.
• W in the opening is elevated to a temperature of about 3,000°C to about 3,600°C causing melting and reflowing, thereby eliminating the voids.
• CMP can be inducted in a conventional manner such that the upper surface of the W filling the opening is substantially co-planar with the upper surface of the dielectric layer.
• CMP is conducted prior to laser thermal annealing.
• laser thermal annealing in accordance with embodiments of the present invention to reduce interconnect voiding and to decrease contact resistance offers several advantages.
• laser thermal annealing enables pinpoint accuracy in targeting the W filling the opening, thereby avoiding unnecessarily elevating the temperature of other portions of the wafer causing various problems, such as undue impurity diffusion.
• any of various commercially available laser tools may be employed, such as those utilizing a laser source capable of operating at energies of about 10 to about 2,000 mJ/cm 2 /pulse, e.g., about 100 to about 400 mj/cm 2 /pulse.
• Commercially available tools exist which can perform such laser annealing, either with or without mask.
• the Verdant Technologies laser anneal tool is but an example and operates at an exposure wavelength of 308 nm.
• Fig. 1 A W plug voiding problem addressed by the present invention is illustrated in Fig. 1 wherein transistors are formed on substrate 10.
• the transistors can comprise MOS transistors and/or dual gate memory cell transistors comprising floating and control gates with an interpoly (ONO) dielectric layer therebetween.
• the transistors can comprise a tunnel oxide 13, a floating gate electrode 14, an ONO stack interpoly dielectric 15, and a control gate 16.
• a layer of metal suicide 17A is formed on the upper surface of the gate electrode stack, while a layer of metal suicide 17B is formed on the source/drain regions 11, 12.
• a dielectric layer 100 such as BPSG, or a composite of BPSG and silicon oxide derived from TEOS thereon, is deposited, as at a thickness of about 7,500 A to about 8,500 A, e.g., about 8,000 A.
• Conventional photolithographic and etching techniques are then implemented to form a contact opening in dielectric layer 100 exposing source/drain region 12. W is then deposited to fill the contact opening forming an overburden and CMP is then conducted leaving W plug 101 having an undesirable degree of porosity 102.
• the present invention effectively solves this particular problem in an efficient manner, thereby significantly reducing or eliminating such voids with an attendant improvement in electromigration performance and device reliability.
• transistors are formed on substrate 20.
• the transistor can comprise MOS transistors and/or dual gate memory cell transistors comprising floating and control gates with an interpoly (ONO) dielectric layer therebetween.
• the transistor can comprise a tunnel oxide 23, a floating gate electrode 24, and ONO stack interpoly dielectric 25 and a control gate 26.
• a layer of metal suicide 27A, e.g., nickel suicide, is formed on the upper surface of the gate electrode stack, while a layer metal suicide 27B, e.g., nickel suicide, is formed on the source/drain regions 21, 22.
• a composite barrier layer 201 is then deposited to line the opening, such as an initial layer of Ti and a layer of titanium nitride thereon. W is then deposited to fill the opening and form an overburden 202. Due to the high aspect ratio of the contact opening, significant voiding 203 is generated in the W plug.
• laser thermal annealing is conducted by impinging a pulsed laser light beam on the deposited W directed toward the filled contact, as schematically illustrated by arrows 30, typically at a radiant fluence of about 0.78 to about 1.10 joules/cm 2 , for a period of time of about 10 to about 100 nanoseconds, thereby elevating at a temperature of W in the plug to about 3,000°C to about 3,600°C, causing melting and reflowing to eliminate the voids, as schematically illustrated in Fig. 4.
• CMP is then conducted resulting in the structure illustrated in Fig. 5 wherein tungsten plug 50 does not exhibit voids.
• CMP is conducted prior to laser thermal annealing.
• Adverting to Fig. 6, the depicted structure is that resulting from performing CMP on the structure schematically illustrated in Fig. 2.
• Laser thermal annealing is then conducted, as illustrated in Fig. 7, by impinging a pulsed laser light beam 70 directed at the W plug causing reflowing and void elimination.
• the resulting structure is schematically illustrated in Fig. 8 and comprises W plug 80 without voids.
• the present invention provides methodology enabling the formation of interconnects having W contacts and/or vias with large aspect ratios, e.g., 4 or greater, with no or significantly reduced voids, thereby reducing contact resistance and stabilizing contact resistance distribution to provide a tighter resistance distribution, improving device reliability and improving electromigration performance.
• the present invention enjoys industrial applicability in manufacturing any of various types of semiconductor devices with improved reliability and increased circuit speed.
• the present invention has particular applicability in manufacturing semiconductor devices with design features in the deep sub-micron regime, such as flash memory devices, e.g., EEPROMs, with a design rule of about 0.12 micron and under, with significantly improved reliability, increased circuit speed, improved electromigration performance and improved manufacturing throughput.

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• 2001
  • 2001-11-08 US US09/986,263 patent/US6638861B1/en not_active Expired - Fee Related
• 2002
  • 2002-11-08 JP JP2003542676A patent/JP2005508573A/ja active Pending
  • 2002-11-08 CN CNA02821997XA patent/CN1582345A/zh active Pending
  • 2002-11-08 KR KR1020047007012A patent/KR100892401B1/ko not_active Expired - Fee Related
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