DE60203319D1 - Verfahren zur entfernung von hohlräumen in wolframstiften - Google Patents

Verfahren zur entfernung von hohlräumen in wolframstiften

Info

Publication number
DE60203319D1
DE60203319D1 DE60203319T DE60203319T DE60203319D1 DE 60203319 D1 DE60203319 D1 DE 60203319D1 DE 60203319 T DE60203319 T DE 60203319T DE 60203319 T DE60203319 T DE 60203319T DE 60203319 D1 DE60203319 D1 DE 60203319D1
Authority
DE
Germany
Prior art keywords
sticks
tungsten
hollow spaces
removing hollow
spaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60203319T
Other languages
English (en)
Other versions
DE60203319T2 (de
Inventor
Van Ngo
Eric Paton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60203319D1 publication Critical patent/DE60203319D1/de
Publication of DE60203319T2 publication Critical patent/DE60203319T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE60203319T 2001-11-08 2002-11-08 Verfahren zur entfernung von hohlräumen in wolframstiften Expired - Lifetime DE60203319T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/986,263 US6638861B1 (en) 2001-11-08 2001-11-08 Method of eliminating voids in W plugs
US986263 2001-11-08
PCT/US2002/035910 WO2003040436A1 (en) 2001-11-08 2002-11-08 Method of eliminating voids in w plugs

Publications (2)

Publication Number Publication Date
DE60203319D1 true DE60203319D1 (de) 2005-04-21
DE60203319T2 DE60203319T2 (de) 2006-03-16

Family

ID=25532246

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60203319T Expired - Lifetime DE60203319T2 (de) 2001-11-08 2002-11-08 Verfahren zur entfernung von hohlräumen in wolframstiften

Country Status (7)

Country Link
US (1) US6638861B1 (de)
EP (1) EP1442161B1 (de)
JP (1) JP2005508573A (de)
KR (1) KR100892401B1 (de)
CN (1) CN1582345A (de)
DE (1) DE60203319T2 (de)
WO (1) WO2003040436A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7651910B2 (en) * 2002-05-17 2010-01-26 Micron Technology, Inc. Methods of forming programmable memory devices
US6746944B1 (en) * 2003-01-14 2004-06-08 Advanced Micro Devices, Inc. Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing
GB0330010D0 (en) * 2003-12-24 2004-01-28 Cavendish Kinetics Ltd Method for containing a device and a corresponding device
US7339230B2 (en) * 2006-01-09 2008-03-04 International Business Machines Corporation Structure and method for making high density mosfet circuits with different height contact lines
US20070210448A1 (en) * 2006-03-10 2007-09-13 International Business Machines Corporation Electroless cobalt-containing liner for middle-of-the-line (mol) applications
KR101477661B1 (ko) * 2008-07-17 2014-12-31 삼성전자주식회사 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법
KR20100031962A (ko) * 2008-09-17 2010-03-25 삼성전자주식회사 카본계막 식각 방법 및 이를 이용한 콘택홀 형성방법
KR101534678B1 (ko) * 2009-02-12 2015-07-08 삼성전자주식회사 텅스텐 콘택 플러그를 산소 분위기에서 ｒｔａ 처리하고, ｒｔｏ 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법
KR101525130B1 (ko) * 2009-08-03 2015-06-03 에스케이하이닉스 주식회사 수직채널형 비휘발성 메모리 소자 및 그 제조 방법
KR101858521B1 (ko) * 2011-06-13 2018-06-28 삼성전자주식회사 비휘발성 메모리 장치의 제조 방법
CN103311176B (zh) * 2012-03-16 2015-04-29 中芯国际集成电路制造(上海)有限公司 金属连线的制作方法、半导体结构的制作方法
KR102298605B1 (ko) * 2015-01-14 2021-09-06 삼성전자주식회사 수직형 메모리 장치 및 이의 제조 방법
CN106128996A (zh) * 2016-06-24 2016-11-16 武汉新芯集成电路制造有限公司 一种无缝多晶硅插塞的形成方法
CN108987347B (zh) * 2017-05-31 2020-10-09 联华电子股份有限公司 半导体结构的制作方法
US10438846B2 (en) 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
KR102208545B1 (ko) * 2018-10-04 2021-01-28 (주)알엔알랩 반도체 디바이스 제조 방법
KR20220014500A (ko) 2020-07-29 2022-02-07 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166143A (ja) * 1985-01-18 1986-07-26 Matsushita Electronics Corp 半導体装置の製造方法
US5780908A (en) * 1995-05-09 1998-07-14 Matsushita Electric Industrial Co., Ltd. Semiconductor apparatus with tungstein nitride
US5885896A (en) * 1996-07-08 1999-03-23 Micron Technology, Inc. Using implants to lower anneal temperatures
US6143650A (en) 1999-01-13 2000-11-07 Advanced Micro Devices, Inc. Semiconductor interconnect interface processing by pulse laser anneal
EP1069213A3 (de) 1999-07-12 2004-01-28 Applied Materials, Inc. Optimale Wärmebehandlungstechnik zur Steuerung von Mikrohohlräumenbildung und zur Selbst-Wärmebehandlungsverwaltung von Elektroplattiertem Kupfer
US6399486B1 (en) 1999-11-22 2002-06-04 Taiwan Semiconductor Manufacturing Company Method of improved copper gap fill
US6261963B1 (en) 2000-07-07 2001-07-17 Advanced Micro Devices, Inc. Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

Also Published As

Publication number Publication date
KR100892401B1 (ko) 2009-04-10
DE60203319T2 (de) 2006-03-16
CN1582345A (zh) 2005-02-16
JP2005508573A (ja) 2005-03-31
EP1442161B1 (de) 2005-03-16
US6638861B1 (en) 2003-10-28
KR20050044376A (ko) 2005-05-12
WO2003040436A1 (en) 2003-05-15
EP1442161A1 (de) 2004-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY