Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/002—Switching arrangements with several input- or output terminals
  • H03K17/007—Switching arrangements with several input- or output terminals with several outputs only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
  • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/16—Modifications for eliminating interference voltages or currents
  • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
  • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

• the present invention relates to analog demultiplexer for distributing signals from a single input line to one of multiple output lines.
• the present invention relates to an analog demultiplexer for distributing a video input signal to one of several video display column drivers, with the analog demultiplexer having minimal offset due to its amplifiers, and having a minimal amplifier settling time.
• Fig. 1 shows one conventional configuration for an analog demultiplexer.
• the analog demultiplexer allows a multiplexed analog input voltage N !N received at input 2 to be demultiplexed using a switch S t to provide an output voltage Nou ⁇ -Nou ⁇ at a respective one of outputs 4J.-4N.
• the logic control driving switch S toggles switch Si to direct an input voltage N ⁇ to one specific output buffer AMP ⁇ AMP ⁇ . i this way, an input voltage provided at input V I N can be demultiplexed to one of numerous output buffers AMPi-
• the hold capacitor retains the sampled voltage, and thus, the voltage at Nou ⁇ remains constant for a period of time.
• the input voltage V I ⁇ at input 2 can be connected using switch Si to sample and hold the input voltage N ⁇ -j using another one of the capacitors C 2 -C ⁇ and its corresponding amplifier AMP 2 -AMP ⁇ .
• FIG. 2 A first improvement over the analog demultiplexer of Fig. 1 is shown in Fig. 2.
• switch Si closes and connects the output of amplifier Ai to capacitor Ci and the non-inverting input of amplifier AMPi.
• amplifier Ai Before switch S 2 of Fig. 2 closes, amplifier Ai would be in an open loop configuration. Thus, its output will be in an undetermined voltage state. Amplifier Ai is "saturated”. Amplifier Ai returns into its "active" region by glitching and ringing its output before it settles. (Settling time depends on the
• FIG. 4 A second improvement over the analog demultiplexer of Fig. 1 is shown in Fig. 4.
• a hold capacitor Ci, C 2 , etc. is placed between the inverting input and output of each of the output amplifiers AMPi, AMP 2 , etc.
• Switches Si and S 2 operate as a pair to connect one of the output amplifiers AMPi, AMP , ... between the output of amplifier Ai and its non-inverting input.
• a switch S 3 connects the output of Ai to a reference voltage V REF when the switches Si and S are not connected.
• the non-inverting input of the output amplifiers AMPi, AMP 2 ,... are likewise connected to the reference V REF -
• an analog demultiplexer is provided with the voltage offset and gain error of amplifiers AMP I -AMPN and Ai divided down to a minimal value. Further, the analog demultiplexer has a minimal settling time, and charge injection from switch Si to the output generates a minimal offset error.
• the analog demultiplexer in accordance with the present invention includes an input amplifier A ls and a plurality of output amplifiers AMP I -AMPN, similar to Fig. 2.
• the output and inverting (-) input of amplifiers AMPI-AMPN are connected by a respective capacitor C I -CN, as in Fig. 2.
• a switch Si in the case of Fig. 6 multiple switches S la , Si b , etc. serve to connect the output of amplifier Ai to the inverting input of a respective one of amplifiers AMP I -AMPN.
• a switch S 2 (in the case of Fig.
• switches S 2a , S 2b , etc. serve to connect the output of one of amplifiers AMP I -AMPN to the non-inverting input of the amplifier Ai.
• switches S 2a , S b, etc. can function to switch together with respective ones of switches S ⁇ a , Si , etc.
• the gain as well as the offset of any of AMIVAMP N is divided down by the gain of Ai.
• the amplifier Ai has a capacitor Csi connected to its non-inverting input and another capacitor Cs 2 connected to its inverting input.
• a switch S 50 connects the inverting input of amplifier Ai to its output, and a switch S 40 connects the non-inverting input of amplifier Ai to a voltage reference V R E F matching a voltage reference VR EF applied to the non- inverting input of amplifier AMP 2 .
• a switch S 30 connects the capacitor Csi to receive the demultiplexer input 2, while a switch S 35 connects the capacitor Cs 2 to the demultiplexer input 2. In operation, switches S 40 , S 50 , S 30 and S 35 are initially closed, while switches S 2a , S 2 , etc.
• Switch S 50 provides feedback to assure gain errors and offset of Ai are divided down.
• Switches S 30 , S 35 , S 40 and S 50 are then open, while one of switches S 2a , S 2 , etc. is closed in correspondence with a switch Si a , i b , etc. Since the inputs and output of both Ai and the corresponding amplifier AMP I -AMPN will initially be at V R E F , very little settling time will be required to stabilize the respective output voltage V O U TI -V OUTN -
• the switches S ⁇ a , Sib, etc. are formed from as a CMOS switch made from a combined PMOS and NMOS transmission gate.
• the NMOS transistor enables the circuit to switch fast, while the PMOS transistor being on after the circuit settles removes voltage offset typically existing with only an NMOS transistor.
• a dummy switch can be added in series with the
• CMOS switch which is half the size to cancel any charge offset produced by the active switch.
• the gate size of transistors for switches Si a , Si b etc. are reduced to limit any offset due to these switches.
• Fig. 1 shows one conventional configuration for an analog demultiplexer
• Fig. 2 shows a first improvement over the analog demultiplexer of Fig. i;
• Fig. 3 shows an equivalent circuit for the switch state of Fig. 2;
• Fig. 4 shows a second improvement over the analog demultiplexer of
• Fig. 5 shows an equivalent circuit for the switch state of Fig. 4.
• Fig. 6 shows an analog demultiplexer in accordance with the present invention
• Fig. 7 shows the analog demultiplexer of Fig. 7 with connections only between the input amplifier Ai and output amplifier AMPi.
• Fig. 8 shows an equivalent circuit for the switch state of Fig. 7.
• Fig. 9 shows the equivalent circuit for Fig. 7 with switches S 40 and S 50 changing to an open state
• Fig. 10 shows the equivalent circuit for Fig. 7 with the S 40 and S 50 of
• Fig. 11 shows an equivalent circuit for Fig. 7 with the switches S 30 , S 40 , S 5 0 remaining open, but switches S 2a and S la closing
• Fig. 12 shows an equivalent circuit with switches S 30 , S 40 , S 50 remaining open, and switch S 2a remaining closed, but S la reopening;
• Fig. 13 shows transistors used to create a switch Sla, and voltages applied to reduce any offset due to charge injection; and Fig. 14 shows components for an embodiment of the input amplifier Al .
• FIG. 6 An approach for an analog demultiplexer in accordance with the present invention is shown in Fig. 6.
• control logic can guide V ⁇ to be sampled and held on a specific one of the output buffers AMP AMP N -
• Fig. 6 shows use of multiple switches S la , Si ••• etc. and S 2a , S 2b ... etc., as an alternative, a single switch could be used for all of switches S la , Si b ••• etc. or S 2a , S b ... etc..
• switches such as S ⁇ a and S 2a typically open and close together simultaneously in prior art designs, in the present invention the switches may or may not close simultaneously.
• the connection of switches in Fig. 7 enable the value V REF to be maintained at the inputs and output of amplifiers Ai and AMP I -AMPN prior to connection of the amplifier Al to one of amplifiers AMP I -AMP N is described to follow with equivalent circuits shown for each stage.
• VX(1+A1) Al(VREF + Nos ⁇ )
• switches S 40 and S 50 are opened creating a circuit as shown in Fig.
• switches S 30 and S 35 are opened creating a circuit as shown in Fig. 10.
• switch Six can be closed, connecting Vx to V R E F , so Vx is clamped to V REF - Switch Si x is then opened before stage 4.
• switch S la is reopened as shown in Fig. 12, as the amplifier AMPi has sampled and will hold the value V IN at the output V OUT I-
• switch S 2a is reopened, to prepare for a subsequent sampling since V I N has been sampled and held by output amplifier AMPi.
• the control logic can now start to sample V I to a different amplifier (for example AMP 2 ). With sampling to AMP 2 , all the stages explained herein are then performed again, but with AMP 2 replacing AMPi. After VI N is sampled to AMP 2 , the control logic samples V I to another amplifier and so on. To overcome voltage droop, the output amplifiers AMPi- AMP are refreshed repetitively by a subsequent sampling of V I -
• CMOS designs enables reduction in charge injection since it uses
• the CMOS design still includes an NMOS transistor to which turns on initially much faster than the PMOS transistor, h CMOS high voltage designs, charge injection will still produce an offset in the hold capacitors of the output amplifiers.
• the offset is caused by the charge under the gate injecting into the hold capacitor when the switch opens. The amount of offset is determined by: (1) the control voltage swing of the switch; and (2) the size of the switch.
• a low voltage CMOS switch 10 used for switch S la includes PMOS and NMOS transistors 11 and 12 as shown in Fig. 13.
• the source-drain path of the NMOS transistor 11 and PMOS transistor 12 are connected in parallel between the output of amplifier Ai and an input of amplifier AMP ! .
• the gates of transistors 11 and 12 receive complementary control signals ⁇ and ⁇ bar.
• Vld low voltage
• Vld output of amplifier Al can swing between Vssl and Vld; Note: Vssl and
• the dummy switch 15 has transmission gates half the size of the transmission gates of transistors 11 and 12 forming the low voltage switch 10.
• the transmission gates of the dummy switch 10 are driven by a signal ⁇ and bar, similar to switch 10. Signals ⁇ and bar swing between voltages of Vld and Vssl.
• the output of amplifier Ai is prevented from going above Vld so that a low voltage switch 10 and dummy switch 15 can be used for switch Si a .
• the offsets caused by charge injection and clock feedthrough can be further minimized.
• the dummy switch 15 that is half the size of switch 10 is used to cancel the charge produced by switch 10.
• Another improvement is having the value of V REF between Vld and Vss.
• V REF V REF - V REF
• V REF (Vld + Vss)/2.
• Amplifier Ai includes two PMOS transistors 21 and 22 connected in a differential fashion.
• Transistor 21 has a gate forming the inverting (-) input of amplifier Ai, while the gate of transistor 22 forms the non-inverting (+) input of amplifier Ai.
• the sources of transistors 21 and 22 are fed from a current sink 20 connected to Vdd. Drains of transistors 21 and 22 are connected through respective NMOS transistors 24 and 25 to Vss. Note Vss and Vssl are the same voltage.
• Transistors 24 and 25 are then connected in a current mirror configuration with respective NMOS transistors 27 and 28.
• Transistor 27 has a source-drain path connected in series with transistor 30 between Vld and Vssl, while transistor 28 has a source-drain path connected in series with transistor 31 between Vld and Vssl.
• the connection between the source-drain paths of transistors 28 and 31 form the output of the amplifier Ai.

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• 2002
  • 2002-09-04 TW TW091120153A patent/TW569536B/zh not_active IP Right Cessation
  • 2002-09-05 WO PCT/US2002/028198 patent/WO2003021779A1/en not_active Ceased
  • 2002-09-05 KR KR1020047003403A patent/KR100910481B1/ko not_active Expired - Fee Related
  • 2002-09-05 JP JP2003525995A patent/JP4111915B2/ja not_active Expired - Fee Related
  • 2002-09-05 US US10/236,340 patent/US6897800B2/en not_active Expired - Lifetime
• 2005
  • 2005-04-11 US US11/102,962 patent/US7002498B2/en not_active Expired - Fee Related

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