WO2023026350A1

WO2023026350A1 - Fast start-up sample-and-hold switched capacitor circuit

Info

Publication number: WO2023026350A1
Application number: PCT/JP2021/030934
Authority: WO
Inventors: Paul Vincent; Brent Quist
Original assignee: Alps Alpine Co., Ltd.
Priority date: 2021-08-24
Filing date: 2021-08-24
Publication date: 2023-03-02
Also published as: KR20240035588A; CN117546418A

Abstract

A switched capacitor circuit for a capacitive sensor system includes an amplifier having a first input terminal, a second input terminal, and an output coupled to the second input terminal. The first input terminal is a non-inversion input terminal and the second input terminal is an inversion input terminal. The switched capacitor circuit further includes a first capacitor, a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor, a second switch configured to selectively couple the first capacitor to the first input terminal, a second capacitor, a third switch configured to selectively couple the second capacitor to the first input terminal, and a fourth switch configured to selectively couple the second capacitor to the output of the amplifier.

Description

FAST START-UP SAMPLE-AND-HOLD SWITCHED CAPACITOR CIRCUIT

The present disclosure relates to capacitive sensors, and more particularly to a switched capacitor circuit configured as a filter for a capacitive sensor.

The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

An electronic device may implement a capacitive sensor configured to sense contact between an object (e.g., a finger) and a surface, such as a surface of the electronic device, and generate a sensed signal indicative of the sensed contact. For example, a reference signal generator (e.g., a waveform generator) is configured to generate and output a control signal to the capacitive sensor. In some examples, the control signal is sinusoidal (i.e., the control signal is a sine wave). The sensed signal corresponds to changes in an amplitude and/or phase of the control signal based on whether an object is contacting the sensor. Accordingly, the presence or absence of an object contacting the sensor can be determined based on the amplitude or phase of the sensed signal.

The sensed signal may be provided to and sampled by an analog-to-digital circuit (ADC) via a sample-and-hold circuit configured to generate an output voltage according to a weighted average of an input voltage corresponding to the sensed signal. For example, the sample-and-hold circuit may include a switched capacitor circuit. An example implementation of a switched capacitor circuit is described in PTL 1.

United States Patent No. 4,769,612

A technical problem associated with conventional switched capacitor circuits is a requirement for multiple switched capacitor sampling cycles (and an associated delay or startup time) for the output voltage to reach an average of the input voltage. A switched capacitor circuit according to the present disclosure provides a solution to this technical problem by presetting capacitors of the switched capacitor circuit to an initial sample value and incrementally increasing to the value to reduce the startup time and reduce a number of sampling cycles required for the output voltage (e.g., an output voltage average) to reach the input voltage average.

In other features, the amplifier is an operational amplifier configured as a unity gain buffer. Capacitances of the first capacitor and the second capacitor are substantially equal. Capacitances of the first capacitor and the second capacitor are different. The output of the amplifier corresponds to an average of respective charges of the first capacitor and the second capacitor. The fourth switch is configured to couple the second capacitor to the output of the amplifier during a first sampling period and the third switch is configured to couple the second capacitor to the first input terminal during a second sampling period.

In other features, the switched capacitor circuit further includes a third capacitor. The third switch and the fourth switch are configured to selectively couple the third capacitor to the first input terminal. A fifth switch configured to selectively couple the third capacitor to the output of the amplifier. The switched capacitor circuit further includes a fourth capacitor. The third switch, the fourth switch, and the fifth switch are configured to selectively couple the fourth capacitor to the first input terminal. A sixth switch configured to selectively couple the fourth capacitor to the output of the amplifier. The switched capacitor circuit further includes a fifth capacitor. The third switch, the fourth switch, the fifth switch, and the sixth switch are configured to selectively couple the fifth capacitor to the first input terminal. A seventh switch is configured to selectively couple the fifth capacitor to the output of the amplifier.

In other features, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are configured to couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a first sampling period, couple the second capacitor to the first input terminal and couple the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a second sampling period, couple the second capacitor and the third capacitor to the first input terminal and couple the fourth capacitor and the fifth capacitor to the output of the amplifier during a third sampling period, couple the second capacitor, the third capacitor, and the fourth capacitor to the first input terminal and couple the fifth capacitor to the output of the amplifier during a fourth sampling period, and couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the first input terminal during a fifth sampling period.

In other features, the switched capacitor circuit further includes a sampling control module configured to control timing of opening and closing of the first switch, the second switch, the third switch, and the fourth switch. A capacitive sensing system includes the switched capacitor circuit and further includes an analog-to-digital converter coupled to the output of the amplifier. The capacitive sensing system further includes a sensor module configured to generate a sensed signal indicative of at least one of contact with and proximity to an object. The input voltage corresponds to the sensed signal.

A switched capacitor circuit for a capacitive sensor system includes an amplifier configured as a unity gain buffer and having a first input terminal, a second input terminal, and an output coupled to the second input terminal, a first capacitor, a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor, a second switch configured to selectively couple the first capacitor to the first input terminal, a plurality of second capacitors, and a plurality of switches configured to selectively couple selected ones of the plurality of second capacitors to either the first input terminal or the output of the amplifier.

In other features, capacitances of the first capacitor and each of the plurality of second capacitors are substantially equal. Capacitances of the first capacitor and at least one of the plurality of second capacitors are different. The first input terminal is a non-inversion input terminal and the second input terminal is an inversion input terminal. The switched capacitor circuit further includes a sampling control module configured to control timing of opening and closing of the first switch, the second switch, and the plurality of switches. The sampling control module is configured to selectively connect each of the plurality of second capacitors to the output of the amplifier and selectively connected each of the plurality of second capacitors to the first input terminal.

Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

According to an embodiment of the present disclosure, the startup time and a number of sampling cycles required for the output voltage to reach the input voltage average can be reduced.

The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
FIG. 1 is an example electronic device including a capacitive sensor. FIG. 2A is an example reference signal generators for a capacitive sensor. FIG. 2B is an example reference signal generators for a capacitive sensor. FIG. 3 is an example capacitive sensor system implementing a switched capacitor circuit for a capacitive sensor according to the present disclosure. FIG. 4A is an example switched capacitor circuits according to the prior art. FIG. 4B is an example switched capacitor circuits according to the prior art. FIG. 5 illustrates example sample and hold averaging using the circuits of FIG. 4A or 4B. FIG. 6A is an example switched capacitor circuits according to the present disclosure. FIG. 6B is an example switched capacitor circuits according to the present disclosure.

In the drawings, reference numbers may be reused to identify similar and/or identical elements.

A change in a signal supplied to a capacitive sensor (corresponding to a sensed signal) in response to a contact with an object is typically small relative to a supplied signal (i.e., a control or drive signal) and may be difficult to detect. Accordingly, different methods may be implemented to improve detection of the change. For example, a reference signal generator that provides the signal to the sensor may also supply a duplicate of the signal or a second reference signal generator can be provided to supply the duplicate of the signal. The duplicated signal is subtracted from the supplied signal and the result, which can be amplified to improve detection, corresponds to the sensed signal.

In some examples, the reference signal generator is a sinewave generator such as a Wien bridge oscillator. In other examples, the reference signal generator may be configured to supply a digital sine wave to a digital-to-analog converter (DAC) and the output of the DAC is filtered and/or amplified. In some examples, an offset control module is configured to generate an offset signal that is a duplicate of the sensed signal when there is no contact between an object and the capacitive sensor.

In some examples, an electronic device including the capacitive sensor may include a regulator circuit (e.g., a voltage-controlled current mode regulator) coupled to an output of the capacitive sensor. The regulator circuit is configured to regulate an output voltage of the capacitive sensor (corresponding to the sensed signal) and generate an output current indicative of the sensed signal.

In some examples, the sensed signal (or an output signal indicative of the sensed signal) is sampled by an analog-to-digital converter (ADC). The output signal may be provided to the ADC via a sample-and-hold circuit configured to generate an output according to a weighted average of the sensed signal. For example, the sample-and-hold circuit may include a switched capacitor circuit, such as a switched capacitor, single-pole low pass filter (LPF) circuit.

A switched capacitor circuit is configured to receive (e.g., sample) an input voltage and generate an output voltage corresponding to an average of sampled values of the input voltage (i.e., an input voltage average). The output voltage may start at an initialized value (e.g., a reference voltage, ground, etc.) and gradually reach a value correspond to the input voltage average. Typically, multiple switched capacitor sampling cycles (and an associated delay or startup time) are required for the output voltage to reach the input voltage average.

A switched capacitor circuit according to the present disclosure is configured to reduce a number of sampling cycles required for the output voltage (e.g., an output voltage average) to reach the input voltage average. For example, filter capacitors of the switched capacitor circuit may be preset to an initial sample value and incrementally increased to the value of the input voltage to reduce the startup time as described below in more detail.

Referring now to FIG. 1, an example electronic device 100 including a sensor module 104 corresponding to a capacitive sensor is shown. A reference signal generator (e.g., a waveform generator) 108 supplies a reference or control signal (e.g., a square wave, a sinewave, etc.) 110 to the sensor module 104. The reference signal generator 108 may supply the control signal 110 to an offset control module 112 or an optional second reference signal generator 116 may provide a duplicate of the control signal 110 to the offset control module 112.

The sensor module 104 modifies the control signal 110 and generates a sensed signal 118 based on the control signal 110 and proximity or contact with a sensed object. In other words, the sensed signal 118 corresponds to the control signal 110 as modified in accordance with detection of (e.g., contact with and/or proximity of) an object. The sensed signal 118 is indicative of whether an object (e.g., a finger) is in contact with the sensor module 104. In some examples, the sensed signal 118 indicates a proximity of the object to the sensor module 104. The sensed signal 118 may differ (e.g., in amplitude and/or phase) from the control signal 110 regardless of whether an object is in contact with the sensor module 104.

In one example, the offset control module 112 is configured to generate an offset signal 120 that is a duplicate of the sensed signal 118 without contact between an object and the sensor module 104. In other words, the offset control module 112 is configured to modify the control signal 110 in the same manner as the sensor module 104 when there is no contact between an object and the sensor module 104 (and/or, in some examples, when the object is not sufficiently near the sensor module 104 to affect the sensed signal 118). As such, when there is no contact with an object, the sensed signal 118 and the offset signal 120 will be essentially the same (e.g., in magnitude, phase, and/or both magnitude and phase) and a difference between the sensed signal 118 and the offset signal 120 will approach zero. In other examples, the offset signal 120 may be configured to have an opposite polarity relative to the control signal 110 and may simply be summed with the sensed signal 118.

Conversely, when there is contact between an object and the sensor module 104, the offset signal 120 and the sensed signal 118 will be different. A regulator circuit 124 outputs and amplifies a difference between the offset signal 120 and the sensed signal 118. The regulator circuit 124 is further configured to regulate a voltage provided to the sensor module 104 (e.g., a voltage of the control signal 110). For example, the regulator circuit 124 may be a voltage-controlled current mode regulator implemented as a current conveyor.

An output signal 128 (e.g., an output current) of the regulator circuit 124 indicative of the sensed signal 118 may then be processed to detect contact between the sensor module 104 and an object. For example, contact may be determined based on whether an amplitude and/or a phase of the output signal 128 exceeds a respective threshold. In some examples, the sensed signal 118 may be indicative of a proximity of the object to the sensor module 104 regardless of whether the object is in direct contact with the sensor module 104. In these examples, the sensed signal 118 may be further indicative of a distance between the object and the sensor module 104.

The output signal 128 is provided to an output signal path (e.g., an output signal path of a capacitive sensor system of the electronic device 100). For example, the output signal 128 is provided to an ADC via a switched capacitor sample-and-hold circuit according to the principles of the present disclosure (as described below in more detail).

In some examples, the reference signal generator 108 implements a Wien bridge oscillator, which may be difficult to tune and/or to modulate amplitude. In other examples, the reference signal generator 108 may generate a digital sinewave that is subsequently converted to an analog sinewave. For example, as shown in FIGS. 2A and 2B, the reference signal generator 108 may include a digital sinewave generator 200. In FIG. 2A, an analog DAC 204 converts the digital sinewave to an analog signal, which is then filtered and amplified (or, in some examples, attenuated) using an LPF 208 having gain control capabilities. For example, an amplitude control signal is provided to the LPF 208 to control the gain. The LPF 208 may be a first order filter to reduce cost or, in some examples, may be a second, third, or higher order filter. In other examples, a band pass filter may be used.

Conversely, in FIG. 2B, a multiplier 212 is provided between the digital sinewave generator 200 and the analog DAC 204. The amplitude control signal is provided to the multiplier 212 to control the gain. The output of the multiplier (corresponding to the amplified digital sinewave) is provided to the analog DAC 204. The analog signal output by the analog DAC 204 is filtered using an LPF 216 without gain control.

Referring now to FIG. 3, an example capacitive sensor system 300 (e.g., a capacitive sensor system 300 for the electronic device 100) including a sensor module 304 (e.g., a capacitive sensor) and implementing a sample-and-hold circuit 308 according to the present disclosure is shown. A reference signal generator 312 outputs a reference or control signal 316 (e.g., a modulated waveform such as a square wave, an analog sinewave, a digital waveform such as a digital sinewave that is converted to an analog sinewave, etc.). The control signal 316 is supplied to the sensor module 304 via a regulator circuit 318 and, in some examples, to an offset control module 320. The offset control module 320 is configured to generate an offset signal 324 based on the control signal 316. The offset signal 324 is provided to the regulator circuit 318.

The sensor module 304 corresponds to a capacitive sensor (e.g., a capacitive touch circuit) including one or more parasitic capacitances (e.g., parasitic capacitance Crg) that modify an amplitude and phase of the control signal 316 provided to the regulator circuit 318. In some examples, the control signal 316 is coupled to the one or more sensing electrodes through a capacitance Crs. When an object (e.g., a finger 332) approaches (i.e., becomes within a proximity of) and/or contacts the one or more sensing electrodes of the sensor module 304, a capacitance 336 of the finger 332 further modifies the amplitude and phase of a sensed signal 340 that is based on the control signal 316. Accordingly, the sensor module 304 generates, as an output voltage, the sensed signal 340 indicative of whether an object such as the finger 332 is in contact with the sensor module 304 or, in some examples, a proximity of the finger 332 to the sensor module 304. More specifically, the sensed signal 340 is modified in accordance with the detected capacitance 336.

The regulator circuit 318 detects and outputs an indication of the sensed signal 340. In some examples, the regulator circuit 318 detects and outputs a difference between the sensed signal 340 and the offset signal 324. For example, the offset control module 320 is configured such that the sensed signal 340 and the offset signal 324 (i.e., respective amplitudes and phases of the sensed signal 340 and the offset signal 324) are the same when there is no contact between the sensor module 304 (e.g., the one or more sensing electrodes) and an object such as the finger 332. In some examples, the offset control module 320 is configured to adjust a phase and an amplitude of the offset signal 324 such that the output of the regulator circuit 318 (e.g., an output signal 344, corresponding to an output current) becomes substantially zero when there is no contact between the sensor module 304 (the one or more sensing electrodes) and the object.

In other words, the offset control module 320 is configured to adjust the phase and the amplitude of the offset signal 324 such that the phase and the amplitude of the offset signal 324 respectively coincide with a phase and an amplitude of the sensed signal 340 when the sensing electrodes of the sensor module 304 do not sense the proximity of or contact with an object. For example, the parasitic capacitances Crs and Crg modify the amplitude and phase of the control signal 316. The offset control module 320 adjusts the amplitude and the phase of the offset signal 324 to compensate for the changes to the control signal 316 caused by the parasitic capacitances Crs and Crg. The output of the regulator circuit 318 (i.e., the output signal 344) indicates whether there is contact between the sensor module 304 and the finger 332 or, in some examples, a proximity of the finger 332 to the sensor module 304 based on a comparison between the sensed signal 340 and the offset signal 324.

The regulator circuit 318 receives the control signal 316 (e.g., as an input voltage of the regulator circuit 318) from the reference signal generator 312. The regulator circuit 318 is configured to regulate a voltage coupled to the sensor module 304 (e.g., a voltage of the control signal 316). In some examples, the voltage coupled to the sensor module 304 corresponds to a voltage coupled to an optional sensor input/output (I/O) pad 348 that is further coupled to an output of the sensor module 304. Accordingly, the sensed signal 340 corresponds to an output voltage of the regulator circuit 318 that is generated based on the control signal 316 and is further modified by the detected capacitance 336. The regulator circuit 318 generates the output signal 344 (e.g., the output current) indicative of the sensed signal 340.

The sample-and-hold circuit 308 receives the output signal 344 as an input voltage. The control signal 316 (and, accordingly, the output signal 344) is a periodic signal, such as a sine wave, a square wave, etc. Therefore, the input voltage of the sample-and-hold circuit 308 varies. The sample-and-hold circuit 308 is configured to sample values of the input voltage and generate an output voltage 352 corresponding to an average of the sampled values of the input voltage (i.e., an input voltage average). In this manner, the output voltage 352 is indicative of the output signal 344 and, accordingly, the sensed signal 340. An ADC 356 converts samples of the output voltage 352 to digital values for further processing by the capacitive sensor system 300. The sample-and-hold circuit 308 of the present disclosure implements a switched capacitor circuit as described below in more detail.

Example conventional switched

capacitor circuits

400 and 404 are shown in FIGS. 4A and 4B, respectively. The switched

capacitor circuits

400 and 404 include an amplifier (e.g., an operational amplifier) 408 coupled to an input voltage Vin via one or more capacitors and switches. As shown in FIG. 4A, the input voltage is coupled to a positive (non-inversion) input terminal of the amplifier 408 and capacitors C1 and C2 are selectively coupled between the input voltage and a reference voltage and between the reference voltage and the positive input terminal using switches S1 and S2. An output of the amplifier 408 is coupled to a negative (inversion) input terminal of the amplifier 408.

Conversely, as shown in FIG. 4B, the input voltage is coupled to the negative input terminal of the amplifier 408 and capacitor C3 is selectively coupled between the input voltage and the negative input terminal, between the input voltage and ground, and between ground and the negative input terminal using switches S3, S4, S5, and S6. The output of the amplifier 408 is selectively coupled to the negative input terminal via a capacitor C4 using switches S7 and S8, and the capacitor C4 is selectively coupled to ground using switches S9 and S10. A capacitor C5 is coupled in parallel with the capacitor C4 between the output of the amplifier 408 and the negative input terminal. The positive input terminal is coupled to ground.

In each of the switched

capacitor circuits

400 and 404, respective capacitors are selectively coupled to the input voltage to sample the input voltage during a sampling period. In other words, the capacitors accrue charge in accordance with the input voltage during the sampling period. The charged capacitors are uncoupled from the input voltage and selectively coupled to the amplifier 408 to pass the charge (i.e., a voltage corresponding to the sampled input voltage) to the amplifier 408. Over time (e.g., a plurality of sampling cycles), the accrued charge reaches a value corresponding to the input voltage average.

Referring now to FIG. 5 and with continued reference to FIGS. 4A and 4B, example sample and hold averaging for input voltage signals (e.g., V1(t)) 500 and 504 using conventional switched capacitor circuits such as the switched

capacitor circuit

400 or 404 are shown. Typically, the input voltage signals 500 and 504 require a plurality of sampling cycles (e.g., sampling cycles of 1 ns, 2 ns, etc.) to reach a settled value. For example, as shown, the input voltage signals 500 and 504 reach a settled value (e.g., approaching 1.0 volts or 1.5 volts, respectively) over multiple cycles. However, since initial sampled input voltages are relatively low (e.g., approximately 0 volts, 0.5 volts, 0.75 volts, etc.), an input voltage average is weighted towards the initial, lower samples. Accordingly, the switches capacitor circuit requires approximately twenty cycles (i.e., a delay or startup time) for

respective output voltages

508 and 512 to settle at a value corresponding to the input voltage average.

Referring now to FIGS. 6A and 6B, example switched

capacitor circuits

600 and 604 according to the present disclosure are shown. The switched

capacitor circuits

600 and 604 function as a sample-and-hold circuit providing LPF functions. The switched

capacitor circuits

600 and 604 include a first capacitor C1 and at least one second capacitor C2 configured to be selectively coupled to a first input terminal (e.g., a positive or non-inversion input terminal) of an amplifier 608. For example, the amplifier 608 is an operational amplifier configured as a unity gain buffer. A second input terminal (e.g., a negative or inversion input terminal) of the amplifier 608 is coupled to the output of the amplifier 608. An ADC (e.g., the ADC 356) may be coupled to the output of the amplifier 608.

The first capacitor C1 is selectively coupled between an input voltage and ground and between ground and the positive input terminal using switches S1 and S2. In other words, the first switch S1 is configured to selectively couple the first capacitor C1 to the input voltage Vin to charge the first capacitor C1 and the second switch S2 is configured to selectively couple the first capacitor C1 to the positive input terminal.

The second capacitor C2 is selectively coupled to an output (i.e., an output voltage) of the amplifier 608 and/or the positive input terminal of the amplifier 608 using switches S3 and S4. In other words, the third switch S3 is configured to selectively couple the second capacitor C2 to the positive input terminal and the fourth switch S4 is configured to selectively couple the second capacitor C2 to the output of the amplifier 608. For example, the fourth switch S4 is configured to selectively couple the second capacitor C2 to the output of the amplifier 608 during a first sampling period and the third switch S3 is configured to selectively couple the second capacitor C2 to the positive input terminal during a second sampling period. The second capacitor C2 is coupled to the output of the amplifier 608 to preset a charge of the second capacitor C2 in accordance with the output of the amplifier 608. In this manner, the startup time (a time required for the output of the amplifier 608 to reach an input voltage average) is reduced as described below in more detail.

The switches S1-S4 are selectively opened and closed to preset the charge of the second capacitor C2 and to acquire the input voltage. For example, a sampling control module (e.g., a controller) 612 is configured to control timing of the opening and the closing of the switches S1-S4 using one or more control signals 616. With reference to FIG. 6A, during acquisition of a first sample of the input voltage (e.g., a first sampling cycle or period), the switch S1 is closed and the switch S2 is opened to store the first sample in the first capacitor C1. Further, the switch S3 is opened and the switch S4 is closed to couple the second capacitor C2 to the output of the amplifier 608. The switch S2 is then opened while the switch S1 is closed to provide the first sample to the positive input terminal of the amplifier 608. Upon completion of the acquisition of the first sample, the output of the amplifier 608 is equal to the input voltage of the first sample. Since the output of the amplifier 608 corresponds to the input voltage of the first sample stored by the first capacitor C1, the voltage on the first capacitor C1 is also buffered (i.e., stored) onto the second capacitor C2 via the output of the amplifier 608.

Subsequent to the acquisition of the first sample of the input voltage, the switch S3 is closed and the switch S4 is opened to disconnect the second capacitor C2 from the output of the amplifier 608 and to couple the second capacitor C2 to the positive input terminal of the amplifier 608. Accordingly, during acquisition of a second and subsequent samples of the input voltage, both the first capacitor C1 and the second capacitor C2 are coupled to the positive input terminal of the amplifier 608 and the output of the amplifier 608 corresponds to an average of a previous sample stored on the second capacitor and a current sample provided by the first capacitor C1.

In some examples, capacitances of the first capacitor C1 and the second capacitor C2 may be substantially equal. Increasing the capacitance (e.g., size) of the second capacitor C2 relative to the first capacitor C1 may shift the cutoff frequency of the LPF function. However, increasing the capacitance of the second capacitor C2 in this manner may increase the amount of time required for the output of the amplifier 608 to reach the input voltage average. As shown in FIG. 6B, instead of increasing the capacitance of the second capacitor C2, the switched capacitor circuit 604 includes a plurality of capacitors (i.e., two or more capacitors, including the second capacitor C2 and at least a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, etc.) configured to be coupled to the output of the amplifier 608 using the plurality of switches S3, S4, S5, S6, and S7.

Each of the capacitors C2-C7 may have a capacitance that is substantially equal to the first capacitor C1. When the capacitances are substantially equal, the output of the amplifier 608 corresponds to an equally weighted average of input samples. In other examples, capacitances of one or more of the capacitances C2-C7 may differ from the capacitance of the first capacitor C1 (e.g., at least capacitances of the first capacitor C1 and the second capacitor C2 are different). In this manner, the samples may be weighted differently.

In the example shown in FIG. 6B, the plurality of switches S3-S7 are configured to selectively couple selected ones of the capacitors C2-C5 (a plurality of second capacitors) to either the positive input terminal or the output of the amplifier 608 as described below in more detail. For example, during acquisition of a first sample of the input voltage (e.g., a first sampling cycle or period), the switch S1 is closed and the switch S2 is opened to store the first sample in the first capacitor C1. Further, the switch S3 is opened and the switches S4-S7 are closed to couple each of the capacitors C2-C5 to the output of the amplifier 608. The switch S2 is then opened while the switch S1 is closed to provide the first sample to the positive input terminal of the amplifier 608. Upon completion of the acquisition of the first sample, the output of the amplifier 608 is equal to the input voltage of the first sample. Since the output of the amplifier 608 corresponds to the input voltage of the first sample stored by the first capacitor C1, the voltage on the first capacitor C1 is also buffered (i.e., stored) onto each of the capacitors C2-C5 via the output of the amplifier 608.

During acquisition of a second sample of the input voltage (e.g., a second sampling cycle or period), the switch S1 is closed and the switch S2 is opened to store the second sample in the first capacitor C1. Further, the switches S3 and S4 are opened and the switches S5-S7 are closed to couple each of the capacitors C3-C5 to the output of the amplifier 608. The switch S2 is then opened while the switch S1 is closed to provide the second sample to the positive input terminal of the amplifier 608. Further, the switch S3 is closed to couple the second capacitor C2 to the positive input terminal of the amplifier 608, the switch S4 remains open, and the switches S5-S7 remain closed.

Accordingly, during acquisition of the second sample of the input voltage, both the first capacitor C1 and the second capacitor C2 are coupled to the positive input terminal of the amplifier 608 and the output of the amplifier 608 corresponds to an average of the first sample stored on the second capacitor C2 and the second sample provided by the first capacitor C1. In other words, the output of the amplifier 608 corresponds to an average of respective charges of the first capacitor C1 and the second capacitor C2. Since the switches S5-S7 are closed and the capacitors C3-C5 are coupled to the output of the amplifier 608, the average of the first sample and the second sample is stored on each of the capacitors C3-C5.

In subsequent (e.g., third, fourth, and fifth) sampling periods, the switch that is opened during acquisition of the sample shifts from the switch S4 to the switch S5, from the switch S5 to the switch S6, and from the switch S6 to the switch S7, respectively. For example, the third switch S3 and the fourth switch S4 are configured to selectively couple the third capacitor C3 to the positive input terminal while the fifth switch S5 is configured to selectively couple the third capacitor C3 to the output of the amplifier 608. In other words, during acquisition of the third sample, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are coupled to the positive input terminal of the amplifier 608 and the output of the amplifier 608 corresponds to an average of the first sample stored on the second capacitor C2, the second sample stored on the third capacitor C3, and the third sample provided by the first capacitor C1.

Similarly, the third switch S3, the fourth switch S4, and the fifth switch S5 are configured to selectively couple the fourth capacitor C4 to the positive input terminal while the sixth switch S6 is configured to selectively couple the fourth capacitor C4 to the output of the amplifier 608. Accordingly, during acquisition of the fourth sample, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are coupled to the positive input terminal of the amplifier 608 and the output of the amplifier 608 corresponds to an average of the first sample stored on the second capacitor C2, the second sample stored on the third capacitor C3, the third sample stored on the fourth capacitor C4, and the fourth sample provided by the first capacitor C1.

The third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are configured to selectively couple the fifth capacitor C5 to the positive input terminal while the seventh switch S7 is configured to selectively couple the fifth capacitor C5 to the output of the amplifier 608. Accordingly, during acquisition of the fifth sample, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are coupled to the positive input terminal of the amplifier 608 and the output of the amplifier 608 corresponds to an average of the first sample stored on the second capacitor C2, the second sample stored on the third capacitor C3, the third sample stored on the fourth capacitor C4, the fourth sample stored on the fifth capacitor C5, and the fifth sample provided by the first capacitor C1. In this manner, each of the first five samples is equally weighted and the amount of time required (i.e., the startup time) for the output of the amplifier 608 to reach the input voltage average is significantly reduced.

In one example, as described above, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are configured to couple the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the output of the amplifier 608 during a first sampling period, couple the second capacitor C2 to the positive input terminal and couple the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the output of the amplifier 608 during a second sampling period, couple the second capacitor C2 and the third capacitor C3 to the positive input terminal and couple the fourth capacitor C4 and the fifth capacitor C5 to the output of the amplifier 608 during a third sampling period, couple the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to the positive input terminal and couple the fifth capacitor C5 to the output of the amplifier 608 during a fourth sampling period, and couple the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the positive input terminal during a fifth sampling period.

The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless explicitly described as being "direct," when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean "at least one of A, at least one of B, and at least one of C."

In the figures, the direction of an arrow, as indicated by the arrowhead, generally demonstrates the flow of information (such as data or instructions) that is of interest to the illustration. For example, when element A and element B exchange a variety of information but information transmitted from element A to element B is relevant to the illustration, the arrow may point from element A to element B. This unidirectional arrow does not imply that no other information is transmitted from element B to element A. Further, for information sent from element A to element B, element B may send requests for, or receipt acknowledgements of, the information to element A.

In this application, including the definitions below, the term "module" or the term "controller" may be replaced with the term "circuit." The term "module" may refer to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog/digital discrete circuit; a digital, analog, or mixed analog/digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.

The module may include one or more interface circuits. In some examples, the interface circuits may include wired or wireless interfaces that are connected to a local area network (LAN), the Internet, a wide area network (WAN), or combinations thereof. The functionality of any given module of the present disclosure may be distributed among multiple modules that are connected via interface circuits. For example, multiple modules may allow load balancing. In a further example, a server (also known as remote, or cloud) module may accomplish some functionality on behalf of a client module.

The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, data structures, and/or objects. The term shared processor circuit encompasses a single processor circuit that executes some or all code from multiple modules. The term group processor circuit encompasses a processor circuit that, in combination with additional processor circuits, executes some or all code from one or more modules. References to multiple processor circuits encompass multiple processor circuits on discrete dies, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or a combination of the above. The term shared memory circuit encompasses a single memory circuit that stores some or all code from multiple modules. The term group memory circuit encompasses a memory circuit that, in combination with additional memories, stores some or all code from one or more modules.

The term memory circuit is a subset of the term computer-readable medium. The term computer-readable medium, as used herein, does not encompass transitory electrical or electromagnetic signals propagating through a medium (such as on a carrier wave); the term computer-readable medium may therefore be considered tangible and non-transitory. Non-limiting examples of a non-transitory, tangible computer-readable medium are nonvolatile memory circuits (such as a flash memory circuit, an erasable programmable read-only memory circuit, or a mask read-only memory circuit), volatile memory circuits (such as a static random access memory circuit or a dynamic random access memory circuit), magnetic storage media (such as an analog or digital magnetic tape or a hard disk drive), and optical storage media (such as a CD, a DVD, or a Blu-ray Disc).

The apparatuses and methods described in this application may be partially or fully implemented by a special purpose computer created by configuring a general purpose computer to execute one or more particular functions embodied in computer programs. The functional blocks, flowchart components, and other elements described above serve as software specifications, which can be translated into the computer programs by the routine work of a skilled technician or programmer.

The computer programs include processor-executable instructions that are stored on at least one non-transitory, tangible computer-readable medium. The computer programs may also include or rely on stored data. The computer programs may encompass a basic input/output system (BIOS) that interacts with hardware of the special purpose computer, device drivers that interact with particular devices of the special purpose computer, one or more operating systems, user applications, background services, background applications, etc.

The computer programs may include: (i) descriptive text to be parsed, such as HTML (hypertext markup language), XML (extensible markup language), or JSON (JavaScript Object Notation) (ii) assembly code, (iii) object code generated from source code by a compiler, (iv) source code for execution by an interpreter, (v) source code for compilation and execution by a just-in-time compiler, etc. As examples only, source code may be written using syntax from languages including C, C++, C#, Objective-C, Swift, Haskell, Go, SQL, R, Lisp, Java (registered trademark), Fortran, Perl, Pascal, Curl, OCaml, Javascript (registered trademark), HTML5 (Hypertext Markup Language 5th revision), Ada, ASP (Active Server Pages), PHP (PHP: Hypertext Preprocessor), Scala, Eiffel, Smalltalk, Erlang, Ruby, Flash (registered trademark), Visual Basic (registered trademark), Lua, MATLAB, SIMULINK, and Python (registered trademark).

100: electronic device
104: sensor module
108: reference signal generator
110: control signal
112: offset control module
116: optional second reference signal generator
118: sensed signal
120: offset signal
124: regulator circuit
128: output signal
200: digital sinewave generator
204: analog DAC
208: LPF
212: multiplier
216: LPF
300: capacitive sensor system
304: sensor module
312: reference signal generator
316: control signal
318: regulator circuit
320: offset control module
324: offset signal
332: finger
336: capacitance
340: sensed signal
344: output signal
308: sample-and-hold circuit
352: output voltage
356: ADC
400: switched capacitor circuit
408: amplifier
500: input voltage signal
504: input voltage signal
508: output voltage
512: output voltage
600: switched capacitor circuit
604: switched capacitor circuit
608: amplifier
612: sampling control module
616: control signal

Claims

　　　　A switched capacitor circuit for a capacitive sensor system, the switched capacitor circuit comprising:
　　　　an amplifier having a first input terminal, a second input terminal, and an output, wherein the output is coupled to the second input terminal, wherein the first input terminal is a non-inversion input terminal, and wherein the second input terminal is an inversion input terminal;
a first capacitor;
　　　　a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor;
　　　　a second switch configured to selectively couple the first capacitor to the first input terminal;
a second capacitor;
　　　　a third switch configured to selectively couple the second capacitor to the first input terminal; and
　　　　a fourth switch configured to selectively couple the second capacitor to the output of the amplifier.
　　　　The switched capacitor circuit of claim 1, wherein the amplifier is an operational amplifier configured as a unity gain buffer.
　　　　The switched capacitor circuit of claim 1, wherein capacitances of the first capacitor and the second capacitor are substantially equal.
　　　　The switched capacitor circuit of claim 1, wherein capacitances of the first capacitor and the second capacitor are different.
　　　　The switched capacitor circuit of claim 1, wherein the output of the amplifier corresponds to an average of respective charges of the first capacitor and the second capacitor.
　　　　The switched capacitor of claim 1, wherein the fourth switch is configured to couple the second capacitor to the output of the amplifier during a first sampling period and the third switch is configured to couple the second capacitor to the first input terminal during a second sampling period.
　　　　The switched capacitor circuit of claim 1, further comprising:
　　　　a third capacitor, wherein the third switch and the fourth switch are configured to selectively couple the third capacitor to the first input terminal; and
　　　　a fifth switch configured to selectively couple the third capacitor to the output of the amplifier.
　　　　The switched capacitor circuit of claim 7, further comprising:
　　　　a fourth capacitor, wherein the third switch, the fourth switch, and the fifth switch are configured to selectively couple the fourth capacitor to the first input terminal; and
　　　　a sixth switch configured to selectively couple the fourth capacitor to the output of the amplifier.
　　　　The switched capacitor circuit of claim 8, further comprising:
　　　　a fifth capacitor, wherein the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to selectively couple the fifth capacitor to the first input terminal; and
　　　　a seventh switch configured to selectively couple the fifth capacitor to the output of the amplifier.
　　　　The switched capacitor circuit of claim 9, wherein the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are configured to:
　　　　couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a first sampling period;
　　　　couple the second capacitor to the first input terminal and couple the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a second sampling period;
　　　　couple the second capacitor and the third capacitor to the first input terminal and couple the fourth capacitor and the fifth capacitor to the output of the amplifier during a third sampling period;
　　　　couple the second capacitor, the third capacitor, and the fourth capacitor to the first input terminal and couple the fifth capacitor to the output of the amplifier during a fourth sampling period; and
　　　　couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the first input terminal during a fifth sampling period.
　　　　The switched capacitor circuit of claim 1, further comprising a sampling control module configured to control timing of opening and closing of the first switch, the second switch, the third switch, and the fourth switch.
　　　　A capacitive sensing system comprising the switched capacitor circuit of claim 1 and further comprising an analog-to-digital converter coupled to the output of the amplifier.
　　　　The capacitive sensing system of claim 12, further comprising a sensor module configured to generate a sensed signal indicative of at least one of contact with and proximity to an object, wherein the input voltage corresponds to the sensed signal.
　　　　A switched capacitor circuit for a capacitive sensor system, the switched capacitor circuit comprising:
　　　　an amplifier having a first input terminal, a second input terminal, and an output, wherein the output is coupled to the second input terminal, and wherein the amplifier is configured as a unity gain buffer;
　　　　a first capacitor;
　　　　a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor;
　　　　a second switch configured to selectively couple the first capacitor to the first input terminal;
　　　　a plurality of second capacitors; and
　　　　a plurality of switches configured to selectively couple selected ones of the plurality of second capacitors to either the first input terminal or the output of the amplifier.
　　　　The switched capacitor circuit of claim 14, wherein the first input terminal is a non-inversion input terminal and the second input terminal is an inversion input terminal.