WO2003007371A2 - Cellule a transistors - Google Patents

Cellule a transistors Download PDF

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Publication number
WO2003007371A2
WO2003007371A2 PCT/EP2002/007306 EP0207306W WO03007371A2 WO 2003007371 A2 WO2003007371 A2 WO 2003007371A2 EP 0207306 W EP0207306 W EP 0207306W WO 03007371 A2 WO03007371 A2 WO 03007371A2
Authority
WO
WIPO (PCT)
Prior art keywords
transistor cell
individual transistors
cell according
heat sink
transistors
Prior art date
Application number
PCT/EP2002/007306
Other languages
German (de)
English (en)
Other versions
WO2003007371A3 (fr
Inventor
Wolfgang Keller
Jan-Erik Mueller
Martin Pfost
Hans-Peter Zwicknagl
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to AU2002336922A priority Critical patent/AU2002336922A1/en
Publication of WO2003007371A2 publication Critical patent/WO2003007371A2/fr
Publication of WO2003007371A3 publication Critical patent/WO2003007371A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a transistor cell.
  • the present invention relates in particular to a power transistor cell (e.g. heterobipolar transistor power cells or MMIC power cells) which is thermally optimized by air bridges.
  • a power transistor cell e.g. heterobipolar transistor power cells or MMIC power cells
  • HBT heterobipolar transistors
  • One area of application is mobile communication technology, for example.
  • HBT and HBT-MMIC monolithic microwave integrated circuit
  • HBTs achieve high power amplification and high efficiency.
  • these advantages often cannot be used due to the poor thermal conductivity of the semiconductor substrate material (e.g. gallium arsenide (GaAs)).
  • GaAs gallium arsenide
  • the substrates used can, for example, be thinned to a thickness that corresponds to the distance between the heat sources.
  • Metal-filled wells etched into the back of the substrate can be used as heat sinks below the transistors. From the back of the substrate to the connection contact surfaces on the top, openings (via holes) which are coated with gold can be used for heat dissipation.
  • the transistors can be mounted using a so-called "flip-chip" assembly technique. It is also possible to mount the transistors on the heat sinks from the emitter connection surfaces via support bumps and to connect the collector and base regions on the back of the substrate. Corresponding openings are provided for the electrical connection. It is also possible to epitaxially grow the semiconductor layers of the transistor onto a heat-conducting substrate.
  • air bridges are made of electrically and thermally conductive material, preferably a suitable metal, and electrically and thermally connect the contacts of the individual transistors of a cell to one another in a bridge-like manner.
  • air bridges are described for example in the following publications.
  • the individual transistors in particular transistor fingers, are arranged so close to one another that they heat up each other.
  • the transistors at the edge of the cell are significantly colder than those in the middle.
  • warmer transistors in particular warmer transistor fingers, have a low threshold voltage and therefore carry disproportionately more current. This is problematic because this inhomogeneity results in unfavorable electrical properties and premature aging. Therefore, stabilization measures, e.g. Base ballast resistors used. However, these sometimes considerably impair the electrical properties of the transistor cell.
  • a transistor cell in particular a power transistor cell, is provided from individual transistors, each with at least one separate electrical connection contact, the connection contacts
  • Individual transistors are each thermally conductively connected to at least one heat sink and these thermally conductive connections each have a predetermined thermal resistance.
  • the transistor cell according to the invention is characterized in that the thermal resistances of the thermally conductive connections are selected such that the temperature differences between all individual transistors of the transistor cell are less than 5% during operation.
  • the transistor cell according to the invention is based on the consideration that heat dissipation adapted to the temperature conditions during operation is provided for the individual transistors in the transistor cell.
  • the heat dissipation of the colder transistors (these are usually those at the edge of the cell) can be deliberately deteriorated so that they reach the same temperature as the warmer transistors (usually those in the middle of the cell). This can be achieved without significantly increasing the temperature of the hottest transistors.
  • the transistor cell according to the invention has the advantage that the temperature differences between the individual transistors are significantly reduced without their electrical properties being impaired.
  • those previously used have the advantage that the temperature differences between the individual transistors are significantly reduced without their electrical properties being impaired.
  • Stabilization measures such as base ballast resistances in the case of bipolar transistors, are designed to be less aggressive or are omitted entirely. In this way, good thermal properties and good electrical behavior are achieved at the same time.
  • the temperature differences between all individual transistors of the transistor cell during operation are less than 2%, preferably less than 1%.
  • connection contacts of the individual transistors are thermally conductively connected to the heat sink and to one another via an air bridge, preferably an electrically conductive air bridge.
  • all the transistors of the transistor cell are thus connected to the heat sink essentially via a single interconnected structure.
  • Transistors different thermal resistances are generated.
  • the air bridge has a substantially two-dimensional extent in a plane parallel to a semiconductor substrate in which the individual transistors are arranged.
  • an air bridge is thus used which not only extends substantially in the direction of a sequence of individual transistors aligned in a row, but which is also substantially expanded perpendicular to this direction in the plane of the substrate top.
  • such an air bridge can be made relatively thick and therefore good heat conductor and, on the other hand, it can be connected to the heat sink via additional thermal contacts on larger contact surfaces. Overall, this results in a significantly reduced thermal resistance for all individual transistors.
  • the air bridge has constrictions and / or cutouts, so that the thermal resistances of the thermal connections from predetermined individual transistors to the heat sink are greater than the thermal resistances of the thermal connections from the remaining individual transistors to the heat sink. Constrictions and / or cutouts in the
  • Airlift can be taken into account in a simple manner during the manufacture of the airlift, so that there is thus an inexpensive possibility of specifically influencing the thermal resistances for the individual transistors.
  • the air bridge comprises at least two thermally conductive layers. It is particularly preferred if the constrictions and / or recesses are formed in only one of the two layers.
  • the air bridge is connected to the heat sink via contact pillars. It is further preferred if predetermined contact pillars have a greater thermal resistance, so that the thermal resistances of the thermal connections from predetermined individual transistors to the heat sink are greater than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink. An essentially identical effect can also be achieved in that the contact posts are omitted or interrupted at predetermined points at which contact posts would be provided, if one wanted to generate the same thermal resistances as possible.
  • the heat sink is arranged in the semiconductor substrate in which the individual transistors are arranged.
  • the heat sink is arranged in a carrier which is connected to the semiconductor substrate in which the individual transistors are arranged. It is particularly preferred if the contact pillars, which are connected to the heat sink via the air bridge, are designed as bumps.
  • the individual transistors are bipolar transistors, in particular heterobipolar transistors, each having an emitter, a base, and a collector, with for each transistor at least one emitter finger as a connection contact of the emitter, a base finger as a connection contact of the base, or a collector contact as a connection contact of the Collector is formed and the emitter fingers, the base fingers or the collector contacts are thermally conductively connected to one another via an air bridge with the heat sink. It is particularly preferred if the air bridge is thermally conductively connected to the emitter fingers of the individual transistors.
  • FIG. 1 shows a cross section of the central area of a first embodiment of the transistor cell according to the invention
  • Fig. 2 shows a plan view of FIG. 1
  • FIG. 3 shows the edge area of a first embodiment of the transistor cell according to the invention
  • 4 is a plan view of the structure shown in FIG. 3,
  • FIG. 5 shows a further embodiment of the transistor cell according to the invention in a top view
  • Fig. 6 shows a further embodiment of the transistor cell according to the invention in a plan.
  • Fig. 7 shows a further embodiment of the transistor cell according to the invention in a plan
  • Fig. 8 is a section through the structure shown in Fig. 7, and
  • 9a, 9b the temperature distribution within a transistor cell according to the invention in comparison to a conventional transistor cell.
  • a thermally conductive and preferably also electrically conductive air bridge 1 connects the emitter fingers 5 applied as contacts on the emitters 2 to one another. In the case of an electrically conductive air bridge, a separate electrical connection of the emitter fingers 5 is omitted.
  • the air bridge 1 comprises an upper electroplating layer 1 a and a lower electroplating layer 1 b. On the base area 3 there are likewise finger-shaped connection contacts as base fingers 6. Collector contacts 7 are correspondingly applied to the collector area 4. According to the invention, there are no restrictions on the shape of the contacts compared to the configurations customary in conventional power transistor cells, apart from the fact that suitable mounting surfaces must be present for the air bridge.
  • Contact pillars 8 are also shown in Fig. 1.
  • the thermal and preferably also electrical connection between the air bridge 1 and the upper side of the semiconductor substrate 9 or emitter connection surfaces present on the upper side of the semiconductor substrate 9 is produced with these contact pillars.
  • the area in which the contact pillars are seated should preferably be as large as possible. It can take up the entire free chip area, except the areas for the base and collector connection areas.
  • Fig. 2 shows the arrangement of Fig. 1 in supervision.
  • the large-area airlift 1 is drawn in here with straight edges in the upward and downward direction in the plane of the drawing and with break lines to the left and right, which indicate a further expansion of the airlift 1.
  • the airlift continues to the left and right according to the number of individual transistors present.
  • the emitter fingers 5, the base fingers 6 and the collector contacts 7 and the contact pillars 8 are drawn in with dashed lines as hidden contours.
  • the base fingers 6 are electrically conductively connected to a base pad 12; the collector contacts 7 are electrically conductively connected to a collector connection surface 13.
  • the components shown are not all on the same level.
  • the transistor cell thus has an air bridge 1 which is parallel to a semiconductor substrate in one plane which the individual transistors are arranged has an essentially two-dimensional dimension.
  • the air bridge 1 uses both the emitter fingers 5 of the individual transistors provided as contacts of the emitters and the common emitter connection surface 11 as contact surfaces for the contact pillars of the air bridge.
  • the airlift is therefore seated on the emitter fingers 5, as can be seen in FIG. 1.
  • the contact pillars 8, 8a can be placed partly on the top 14 of the chip made of semiconductor material (contact pillars 8a in FIG. 2), partly on the emitter connection surface 11 (contact pillars 8 in FIG. 2).
  • the air bridge 1 and the contact pillars 8 are preferably electrically conductive, and the electrical connection of the emitter fingers 5 is effected via the contact pillars 8 seated on the emitter connection surface 11.
  • the common collector connection surface 13 is completely or partially spanned by the air bridge 1.
  • the air bridge 1 preferably also spans in whole or in part over the base pad 12, via which the base regions of the individual transistors are controlled. Also the
  • pads can be arranged and dimensioned as desired.
  • the top 14 of the chip and the emitter pad 11 thus each form one
  • the air bridge 1 represents a thermally conductive connection to the heat sinks, which has a predetermined thermal resistance.
  • Airlift is designed in the central area of the transistor cell so that the transistors in the central area of the Transistor cell essentially all have to overcome the same thermal resistance.
  • the individual transistors of the transistor cell in particular the transistor fingers, are arranged so close together that they heat each other up. As a consequence, the transistors at the edge of the cell are significantly colder than those in the middle.
  • FIGS. 1 and 2 have hitherto illustrated the central region of an embodiment of the transistor cell according to the invention
  • FIGS. 3 and 4 show the edge region of this embodiment of the transistor cell according to the invention.
  • the upper electroplating layer 1 a of the air bridge 1 has a cutout 20 above the outermost transistor of the transistor cell. Accordingly, the thermal connection between the outermost transistor and the heat sinks 11, 14 has a significantly increased thermal resistance, since the heat in the region of the recess 20 can only be transported by the lower electroplating layer 1b. In this way, the heat dissipation of the transistor at the edge of the cell, which is colder in a conventional construction, can be deliberately deteriorated, so that it reaches the same temperature as that in a conventional construction, hotter transistors in the center of the cell. Thermal resistances of the thermally conductive connections are chosen so that the temperature differences between all individual transistors of the transistor cell are less than 5% during operation.
  • FIGS. 5 and 6 each show a further embodiment of the transistor cell according to the invention in a top view, wherein in the embodiment shown in FIG. 5 the recess 20 in the upper electroplating layer 1 a is designed in a different way than in the embodiment shown in FIG. 4.
  • the recess 20 is provided in the two electroplating layers 1 a and 1 b. Again, the recess 20 is arranged so that the thermal resistance of the thermal connection from the outermost
  • FIG. 7 shows a further embodiment of the transistor cell according to the invention in a top view.
  • a first, extended contact pillar 8a and two further contact pillars 8b are provided, the two contact pillars 8b having a greater thermal resistance than the contact pillar 8a, so that the thermal resistances of the thermal connections from the outermost individual transistor to the
  • Heat sink 14 is greater than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink 14.
  • the different contact pillars are achieved by cutouts 21 in the lower electroplating layer 1b (FIG. 8).
  • FIGS. 9a and 9b show the temperature distribution within a transistor cell according to the invention (FIG. 9b) in comparison to a temperature distribution within a conventional transistor cell (FIG. 9a).
  • the temperature increase is shown along a section line through eight transistor fingers.
  • the transistor cell according to the invention has the advantage that the temperature differences between the individual transistors are significantly reduced without their electrical properties being impaired.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Primary Cells (AREA)

Abstract

Cellule à transistors reposant sur l'exigence selon laquelle une dissipation de chaleur adaptée aux conditions de température en fonctionnement doit être prévue pour les transistors individuels d'une cellule à transistors. Ainsi, par exemple, la dissipation de chaleur des transistors plus froids se trouvant sur le bord de la cellule peut-elle être détériorée à dessein afin que lesdits transistors atteignent la même température que les transistors plus chauds situés au milieu de la cellule. Il est possible d'y parvenir sans que la température des transistors les plus chauds soit considérablement augmentée.
PCT/EP2002/007306 2001-07-10 2002-07-02 Cellule a transistors WO2003007371A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002336922A AU2002336922A1 (en) 2001-07-10 2002-07-02 Transistor cell

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10133362.5 2001-07-10
DE2001133362 DE10133362A1 (de) 2001-07-10 2001-07-10 Transistorzelle

Publications (2)

Publication Number Publication Date
WO2003007371A2 true WO2003007371A2 (fr) 2003-01-23
WO2003007371A3 WO2003007371A3 (fr) 2003-09-18

Family

ID=7691195

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/007306 WO2003007371A2 (fr) 2001-07-10 2002-07-02 Cellule a transistors

Country Status (3)

Country Link
AU (1) AU2002336922A1 (fr)
DE (1) DE10133362A1 (fr)
WO (1) WO2003007371A2 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0693778A2 (fr) * 1994-07-20 1996-01-24 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur avec dissipateur de chaleur intégré
US5616950A (en) * 1992-05-29 1997-04-01 Texas Instruments Incorporated Thermally uniform transistor
US5719433A (en) * 1995-07-25 1998-02-17 Thomson-Csf Semiconductor component with integrated heat sink
US5734193A (en) * 1994-01-24 1998-03-31 The United States Of America As Represented By The Secretary Of The Air Force Termal shunt stabilization of multiple part heterojunction bipolar transistors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3019884B2 (ja) * 1991-09-05 2000-03-13 松下電器産業株式会社 半導体装置およびその製造方法
US5859447A (en) * 1997-05-09 1999-01-12 Yang; Edward S. Heterojunction bipolar transistor having heterostructure ballasting emitter
DE19734509C2 (de) * 1997-08-08 2002-11-07 Infineon Technologies Ag Leistungstransistorzelle
JP2001168094A (ja) * 1999-12-06 2001-06-22 Murata Mfg Co Ltd 配線構造、配線形成方法及び半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616950A (en) * 1992-05-29 1997-04-01 Texas Instruments Incorporated Thermally uniform transistor
US5734193A (en) * 1994-01-24 1998-03-31 The United States Of America As Represented By The Secretary Of The Air Force Termal shunt stabilization of multiple part heterojunction bipolar transistors
EP0693778A2 (fr) * 1994-07-20 1996-01-24 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur avec dissipateur de chaleur intégré
US5719433A (en) * 1995-07-25 1998-02-17 Thomson-Csf Semiconductor component with integrated heat sink

Also Published As

Publication number Publication date
AU2002336922A1 (en) 2003-01-29
WO2003007371A3 (fr) 2003-09-18
DE10133362A1 (de) 2003-01-30

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